RegAllocBase.cpp Source File (original) (raw)

34#include

36using namespace llvm;

38#define DEBUG_TYPE "regalloc"

40 STATISTIC(NumNewQueued, "Number of new live ranges queued");

57void RegAllocBase::anchor() {}

63 VRM = &vrm;

64 LIS = &lis;

68}

73void RegAllocBase::seedLiveRegs() {

79 continue;

81 }

82}

87 seedLiveRegs();

91 assert( VRM ->hasPhys(VirtReg->reg()) && "Register already assigned");

95 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');

98 continue;

99 }

100

101

103

104

105

106

109 << ':' << *VirtReg << '\n');

110

112

113 VirtRegVec SplitVRegs;

115

116 if (AvailablePhysReg == ~0u) {

117

118

121 MI = &MIR;

122 if (MI->isInlineAsm())

123 break;

124 }

125

128

129

131 } else if (AvailablePhysReg)

133

134 for (Register Reg : SplitVRegs) {

136

138 assert( VRM ->hasPhys(SplitVirtReg->reg()) && "Register already assigned");

140 assert(SplitVirtReg->empty() && "Non-empty but used interval");

141 LLVM_DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');

144 continue;

145 }

146 LLVM_DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");

148 "expect split value in virtual register");

150 ++NumNewQueued;

151 }

152 }

153}

154

159 DeadInst->eraseFromParent();

160 }

162}

163

166

167 assert(Reg.isVirtual() && "Can only enqueue virtual registers");

168

170 return;

171

175 } else {

177 << " in skipped register class\n");

178 }

179}

180

184

185

186

189 if (EmitError)

191

194

196 if (AllocOrder.empty()) {

197

198

199

201

202 if (EmitError) {

204 "no registers from class available to allocate", Fn,

206 }

207

208 assert(!RawRegs.empty() && "register classes cannot have no registers");

209 return RawRegs.front();

210 }

211

212 if (EmitError) {

215 "inline assembly requires more registers than available");

216 } else {

218 "ran out of registers during register allocation", Fn,

220 }

221 }

222

223 return AllocOrder.front();

224}

Module.h This file contains the declarations for the Module class.

static cl::opt< bool, true > VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), cl::Hidden, cl::desc("Verify during register allocation"))

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

const T & front() const

front - Get the first element.

bool empty() const

empty - Check if the array is empty.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

This is an important class for using LLVM in a threaded context.

void diagnose(const DiagnosticInfo &DI)

Report a message to the currently installed diagnostic handler.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasInterval(Register Reg) const

void RemoveMachineInstrFromMaps(MachineInstr &MI)

LiveInterval & getInterval(Register Reg)

void removeInterval(Register Reg)

Interval removal.

void invalidateVirtRegs()

Invalidate cached interference queries after modifying virtual register live ranges.

void assign(const LiveInterval &VirtReg, MCRegister PhysReg)

Assign VirtReg to PhysReg.

Wrapper class representing physical registers. Should be passed by value.

MachineFunctionProperties & set(Property P)

bool hasProperty(Property P) const

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

Representation of each machine instruction.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

void emitInlineAsmError(const Twine &ErrMsg) const

Emit an error referring to the source location of this instruction.

void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

bool reg_nodbg_empty(Register RegNo) const

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

virtual void aboutToRemoveInterval(const LiveInterval &LI)

Method called when the allocator is about to remove a LiveInterval.

virtual MCRegister selectOrSplit(const LiveInterval &VirtReg, SmallVectorImpl< Register > &splitLVRs)=0

MCPhysReg getErrorAssignment(const TargetRegisterClass &RC, const MachineInstr *CtxMI=nullptr)

Query a physical register to use as a filler in contexts where the allocation has failed.

void enqueue(const LiveInterval *LI)

enqueue - Add VirtReg to the priority queue of unassigned registers.

void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)

SmallPtrSet< MachineInstr *, 32 > DeadRemats

Inst which is a def of an original reg and whose defs are already all dead after remat is saved in De...

virtual Spiller & spiller()=0

const TargetRegisterInfo * TRI

static const char TimerGroupName[]

static const char TimerGroupDescription[]

virtual const LiveInterval * dequeue()=0

dequeue - Return the next unassigned register, or NULL.

virtual void postOptimization()

RegisterClassInfo RegClassInfo

MachineRegisterInfo * MRI

virtual void enqueueImpl(const LiveInterval *LI)=0

enqueue - Add VirtReg to the priority queue of unassigned registers.

bool shouldAllocateRegister(Register Reg)

Get whether a given register should be allocated.

static bool VerifyEnabled

VerifyEnabled - True when -verify-regalloc is given.

void runOnMachineFunction(const MachineFunction &MF)

runOnFunction - Prepare to answer questions about MF.

ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const

getOrder - Returns the preferred allocation order for RC.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

virtual void postOptimization()

ArrayRef< MCPhysReg > getRegisters() const

const char * getRegClassName(const TargetRegisterClass *Class) const

Returns the name of the register class.

MachineRegisterInfo & getRegInfo() const

void assignVirt2Phys(Register virtReg, MCRegister physReg)

creates a mapping for the specified virtual register to the specified physical register

MachineFunction & getMachineFunction() const

bool hasPhys(Register virtReg) const

returns true if the specified virtual register is mapped to a physical register

const TargetRegisterInfo & getTargetRegInfo() const

LocationClass< Ty > location(Ty &L)

This is an optimization pass for GlobalISel generic memory operations.

bool TimePassesIsEnabled

If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

This class is basically a combination of TimeRegion and Timer.