RegAllocBasic.cpp Source File (original) (raw)

34using namespace llvm;

36#define DEBUG_TYPE "regalloc"

46 false, false)

64 if (VRM->hasPhys(VirtReg)) {

65 Matrix->unassign(LI);

66 aboutToRemoveInterval(LI);

67 return true;

68 }

74 return false;

75}

77void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) {

78 if ( VRM ->hasPhys(VirtReg))

79 return;

82 LiveInterval &LI = LIS->getInterval(VirtReg);

85}

115

117 SpillerInstance.reset();

118}

119

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131

132 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

135 if (!Intf->isSpillable() || Intf->weight() > VirtReg.weight())

136 return false;

138 }

139 }

141 << " interferences with " << VirtReg << "\n");

142 assert(!Intfs.empty() && "expected interference");

143

144

146

147 if ( VRM ->hasPhys(Spill->reg()))

148 continue;

149

150

151

152 Matrix->unassign(*Spill);

153

154

157 }

158 return true;

159}

160

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178

179 auto Order =

182 assert(PhysReg.isValid());

183

184 switch (Matrix->checkInterference(VirtReg, PhysReg)) {

186

187 return PhysReg;

188

190

191 PhysRegSpillCands.push_back(PhysReg);

192 continue;

193

194 default:

195

196 continue;

197 }

198 }

199

200

201 for (MCRegister &PhysReg : PhysRegSpillCands) {

203 continue;

204

205 assert( Matrix ->checkInterference(VirtReg, PhysReg) &&

206 "Interference after spill.");

207

208 return PhysReg;

209 }

210

211

212 LLVM_DEBUG(dbgs() << "spilling: " << VirtReg << '\n');

214 return ~0u;

217

218

219

220 return 0;

221}

222

224 LLVM_DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"

225 << "********** Function: " << mf.getName() << '\n');

226

227 MF = &mf;

231

239

240 SpillerInstance.reset(

242

245

246

247 LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");

248

250 return true;

251}

252

256

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator)

This file declares the RABasic class, which provides a minimal implementation of the basic register a...

A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.

static AllocationOrder create(Register VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)

Create a new AllocationOrder for VirtReg.

Represent the analysis usage information of a pass.

LLVM_ABI AnalysisUsage & addRequiredID(const void *ID)

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

FunctionPass class - This class is used to implement most global optimizations.

Query interferences between a single live virtual register and a live interval union.

const SmallVectorImpl< const LiveInterval * > & interferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())

LiveInterval - This class represents the liveness of a register, or stack slot.

bool isSpillable() const

isSpillable - Can this interval be spilled?

@ IK_VirtReg

Virtual register interference.

@ IK_Free

No interference, go ahead and assign.

Wrapper class representing physical registers. Should be passed by value.

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass(char &ID)

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

AnalysisType & getAnalysis() const

getAnalysis() - This function is used by subclasses to get to the analysis information ...

An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.

RABasic provides a minimal implementation of the basic register allocation algorithm.

void getAnalysisUsage(AnalysisUsage &AU) const override

RABasic analysis usage.

Definition RegAllocBasic.cpp:90

MCRegister selectOrSplit(const LiveInterval &VirtReg, SmallVectorImpl< Register > &SplitVRegs) override

Definition RegAllocBasic.cpp:173

void releaseMemory() override

releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...

Definition RegAllocBasic.cpp:116

Spiller & spiller() override

RABasic(const RegAllocFilterFunc F=nullptr)

Definition RegAllocBasic.cpp:87

bool runOnMachineFunction(MachineFunction &mf) override

Perform register allocation.

Definition RegAllocBasic.cpp:223

bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg, SmallVectorImpl< Register > &SplitVRegs)

Definition RegAllocBasic.cpp:124

RegAllocBase(const RegAllocFilterFunc F=nullptr)

void enqueue(const LiveInterval *LI)

enqueue - Add VirtReg to the priority queue of unassigned registers.

void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)

SmallPtrSet< MachineInstr *, 32 > DeadRemats

Inst which is a def of an original reg and whose defs are already all dead after remat is saved in De...

const TargetRegisterInfo * TRI

virtual void postOptimization()

RegisterClassInfo RegClassInfo

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

virtual void spill(LiveRangeEdit &LRE, AllocationOrder *Order=nullptr)=0

spill - Spill the LRE.getParent() live interval.

Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.

void calculateSpillWeightsAndHints()

Compute spill weights and allocation hints for all virtual register live intervals.

This is an optimization pass for GlobalISel generic memory operations.

std::function< bool(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)> RegAllocFilterFunc

Filter function for register classes during regalloc.

LLVM_ABI char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

auto reverse(ContainerTy &&C)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI FunctionPass * createBasicRegisterAllocator()

BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...

Definition RegAllocBasic.cpp:253

Spiller * createInlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF, VirtRegMap &VRM, VirtRegAuxInfo &VRAI, LiveRegMatrix *Matrix=nullptr)

Create and return a spiller that will insert spill code directly instead of deferring though VirtRegM...

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

LLVM_ABI char & RABasicID

Basic register allocator.

Definition RegAllocBasic.cpp:43