RegBankSelect.cpp Source File (original) (raw)

32#include "llvm/Config/llvm-config.h"

43#include

44#include

45#include

46#include

47#include

48#include

50#define DEBUG_TYPE "regbankselect"

52using namespace llvm;

57 "Run the Fast mode (default mapping)"),

59 "Use the Greedy mode (best local mapping)")));

64 "Assign register bank of generic virtual registers",

65 false, false);

70 "Assign register bank of generic virtual registers", false,

76 OptMode = RegBankSelectMode;

77 if (RegBankSelectMode != RunningMode)

78 LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");

79 }

80}

84 assert(RBI && "Cannot work without RegisterBankInfo");

90 } else {

91 MBFI = nullptr;

92 MBPI = nullptr;

93 }

95 MORE = std::make_unique(MF, MBFI);

96}

109

112 bool &OnlyAssign) const {

113

114 OnlyAssign = false;

115

116

118 return false;

119

122

123

124 OnlyAssign = CurRegBank == nullptr;

125 LLVM_DEBUG(dbgs() << "Does assignment already match: ";

126 if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none";

127 dbgs() << " against ";

128 assert(DesiredRegBank && "The mapping must be valid");

129 dbgs() << *DesiredRegBank << '\n';);

130 return CurRegBank == DesiredRegBank;

131}

132

137

139 "need new vreg for each breakdown");

140

141

142 assert(!NewVRegs.empty() && "We should not have to repair");

143

146

147

149 Register Dst = *NewVRegs.begin();

150

151

152

155

157 "We are about to create several defs for Dst");

158

159

160

161

162 MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY)

163 .addDef(Dst)

164 .addUse(Src);

167 << " to: " << printReg(Dst) << ':'

169 } else {

170

171

173

175 if (MO.isDef()) {

176 unsigned MergeOp;

179 MergeOp = TargetOpcode::G_BUILD_VECTOR;

180 else {

185 0) &&

186 "don't understand this value breakdown");

187

188 MergeOp = TargetOpcode::G_CONCAT_VECTORS;

189 }

190 } else

191 MergeOp = TargetOpcode::G_MERGE_VALUES;

192

193 auto MergeBuilder =

194 MIRBuilder.buildInstrNoInsert(MergeOp)

195 .addDef(MO.getReg());

196

197 for (Register SrcReg : NewVRegs)

198 MergeBuilder.addUse(SrcReg);

199

200 MI = MergeBuilder;

201 } else {

203 MIRBuilder.buildInstrNoInsert(TargetOpcode::G_UNMERGE_VALUES);

204 for (Register DefReg : NewVRegs)

205 UnMergeBuilder.addDef(DefReg);

206

208 MI = UnMergeBuilder;

209 }

210 }

211

213 report_fatal_error("need testcase to support multiple insertion points");

214

215

216

217

218 std::unique_ptr<MachineInstr *[]> NewInstrs(

220 bool IsFirst = true;

221 unsigned Idx = 0;

222 for (const std::unique_ptr &InsertPt : RepairPt) {

224 if (IsFirst)

225 CurMI = MI;

226 else

227 CurMI = MIRBuilder.getMF().CloneMachineInstr(MI);

228 InsertPt->insert(*CurMI);

229 NewInstrs[Idx++] = CurMI;

230 IsFirst = false;

231 }

232

233

234 return true;

235}

236

240 assert(MO.isReg() && "We should only repair register operand");

242

243 bool IsSameNumOfValues = ValMapping.NumBreakDowns == 1;

245

246

248

249

250

251

252

253

254

255

256

257

258

260 return RBI->getBreakDownCost(ValMapping, CurRegBank);

261

262 if (IsSameNumOfValues) {

264

265

267 std::swap(CurRegBank, DesiredRegBank);

268

269

270

271

272

273

274

275

276

277

278

279 unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank,

281

282 if (Cost != std::numeric_limits::max())

284

285 }

286 return std::numeric_limits::max();

287}

288

293 "Do not know how to map this instruction");

294

299 PossibleMappings) {

302 if (CurCost < Cost) {

303 LLVM_DEBUG(dbgs() << "New best: " << CurCost << '\n');

304 Cost = CurCost;

305 BestMapping = CurMapping;

306 RepairPts.clear();

309 }

310 }

311 if (!BestMapping && MI.getMF()->getTarget().Options.GlobalISelAbort !=

313

314

315

316 BestMapping = *PossibleMappings.begin();

319 } else

320 assert(BestMapping && "No suitable mapping for instruction");

321 return *BestMapping;

322}

323

328 assert(RepairPt.hasSplit() && "We should not have to adjust for split");

329

330

331 assert((MI.isPHI() || MI.isTerminator()) && "Why do we split?");

332

334 "Repairing placement does not match operand");

335

336

337

338

339

340 assert((.isPHI() || !MO.isDef()) && "Need split for phi def?");

341

342

343 if (!MO.isDef()) {

344 if (MI.isTerminator()) {

345 assert(&MI != &(*MI.getParent()->getFirstTerminator()) &&

346 "Need to split for the first terminator?!");

347 } else {

348

349

350

352

354 }

355 return;

356 }

357

358

359

360

361

362

363

364

365

366

368 "This code is for the def of a terminator");

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

403 if (Reg.isPhysical()) {

404

405

406

407

408

409

410

411

412

413

414

415 assert(&MI == &(*MI.getParent()->getFirstTerminator()) &&

416 "Do not know which outgoing edges are relevant");

419 "Do not know where each terminator ends up");

421

422

423

424 assert( Next ->readsRegister(Reg, nullptr) &&

425 "Need to split between terminators");

426

427 } else {

428

430

431

432

433

434 assert(false && "Repairing cost may not be accurate");

435 } else {

436

437

438

440 }

441 }

442}

443

448 assert((MBFI || !BestCost) && "Costs comparison require MBFI");

449

450 if (!InstrMapping.isValid())

452

453

456 bool Saturated = Cost.addLocalCost(InstrMapping.getCost());

457 assert(!Saturated && "Possible mapping saturated the cost");

459 LLVM_DEBUG(dbgs() << "With: " << InstrMapping << '\n');

460 RepairPts.clear();

461 if (BestCost && Cost > *BestCost) {

462 LLVM_DEBUG(dbgs() << "Mapping is too expensive from the start\n");

464 }

466

467

468

469

470

475 continue;

477 if (!Reg)

478 continue;

479 LLT Ty = MRI.getType(Reg);

480 if (!Ty.isValid())

481 continue;

482

485 InstrMapping.getOperandMapping(OpIdx);

486

487 bool Assign;

490 continue;

491 }

492 if (Assign) {

493 LLVM_DEBUG(dbgs() << "=> is free (simple assignment).\n");

496 continue;

497 }

498

499

503

504

505

506

509

510

512 LLVM_DEBUG(dbgs() << "Mapping involves impossible repairing\n");

514 }

515

516

517

518 if (!BestCost || Saturated)

519 continue;

520

521

522

523 assert(MBFI && MBPI && "Cost computation requires MBFI and MBPI");

524

525

526

527

528

529

530

531

532

533

534

536

537

538 if (RepairCost == std::numeric_limits::max())

540

541

542 const uint64_t PercentageForBias = 5;

543 uint64_t Bias = (RepairCost * PercentageForBias + 99) / 100;

544

545

546

547

548 assert(((RepairCost < RepairCost * PercentageForBias) &&

549 (RepairCost * PercentageForBias <

550 RepairCost * PercentageForBias + 99)) &&

551 "Repairing involves more than a billion of instructions?!");

552 for (const std::unique_ptr &InsertPt : RepairPt) {

553 assert(InsertPt->canMaterialize() && "We should not have made it here");

554

555 if (!InsertPt->isSplit())

556 Saturated = Cost.addLocalCost(RepairCost);

557 else {

558 uint64_t CostForInsertPt = RepairCost;

559

560

561 assert(CostForInsertPt + Bias > CostForInsertPt &&

562 "Repairing + split bias overflows");

563 CostForInsertPt += Bias;

564 uint64_t PtCost = InsertPt->frequency(*this) * CostForInsertPt;

565

566 if ((Saturated = PtCost < CostForInsertPt))

567 Cost.saturate();

568 else

569 Saturated = Cost.addNonLocalCost(PtCost);

570 }

571

572

573

574 if (BestCost && Cost > *BestCost) {

575 LLVM_DEBUG(dbgs() << "Mapping is too expensive, stop processing\n");

577 }

578

579

580

581 if (Saturated)

582 break;

583 }

584 }

587}

588

592

594

595

597 if (!RepairPt.canMaterialize() ||

599 return false;

601 "This should not make its way in the list");

602 unsigned OpIdx = RepairPt.getOpIdx();

605 InstrMapping.getOperandMapping(OpIdx);

607

608 switch (RepairPt.getKind()) {

611 "Reassignment should only be for simple mapping");

613 break;

615

616 if (MI.isDebugInstr())

617 break;

620 return false;

621 break;

622 default:

624 }

625 }

626

627

628 LLVM_DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n');

630

631 return true;

632}

633

636

637 unsigned Opc = MI.getOpcode();

639 assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||

640 Opc == TargetOpcode::G_ASSERT_SEXT ||

641 Opc == TargetOpcode::G_ASSERT_ALIGN) &&

642 "Unexpected hint opcode!");

643

644

646 RBI->getRegBank(MI.getOperand(1).getReg(), *MRI, *TRI);

647

648

649 assert(RB && "Expected source register to have a register bank?");

650 LLVM_DEBUG(dbgs() << "... Hint always uses source's register bank.\n");

651 MRI->setRegBank(MI.getOperand(0).getReg(), *RB);

652 return true;

653 }

654

655

657

660 BestMapping = &RBI->getInstrMapping(MI);

662 (void)DefaultCost;

664 return false;

665 } else {

667 RBI->getInstrPossibleMappings(MI);

668 if (PossibleMappings.empty())

669 return false;

671 }

672

673 assert(BestMapping->verify(MI) && "Invalid instruction mapping");

674

675 LLVM_DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n');

676

677

678

680}

681

683

684

685

688

689

693

694 while (!WorkList.empty()) {

696

697

698

700 continue;

701

702

703

704 if (MI.isInlineAsm())

705 continue;

706

707

708 if (MI.isImplicitDef())

709 continue;

710

713 "unable to map instruction", MI);

714 return false;

715 }

716 }

717 }

718

719 return true;

720}

721

723#ifndef NDEBUG

727 "instruction is not legal", *MI);

728 return false;

729 }

730 }

731#endif

732 return true;

733}

734

736

738 return false;

739

743 if (F.hasOptNone())

746

747#ifndef NDEBUG

749 return false;

750#endif

751

753

755 return false;

756}

757

758

759

760

764

765 : Kind(Kind), OpIdx(OpIdx),

768 assert(MO.isReg() && "Trying to repair a non-reg operand");

769

771 return;

772

773

774 bool Before = !MO.isDef();

775

776

777 if (.isPHI() && .isTerminator()) {

779

780 return;

781 }

782

783

784 if (MI.isPHI()) {

785

786

787

788 if (!Before) {

790 if (It != MI.getParent()->end())

792 else

794 return;

795 }

796

798

799

802 for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It)

803 if (It->modifiesRegister(Reg, &TRI)) {

804

805

807 return;

808 }

809

810

811

812

813

814 if (It == Pred.end())

816 else

818 } else {

819

820

821

822 if (Before) {

823

825 auto REnd = MI.getParent()->rend();

826

827 for (; It != REnd && It->isTerminator(); ++It) {

829 "copy insertion in middle of terminators not handled");

830 }

831

832 if (It == REnd) {

834 return;

835 }

836

837

839 return;

840 }

841

842

844 ++It != End;)

845

847 "Do not know where to split");

848

850 for (auto &Succ : Src.successors())

852 }

853}

854

859

861 bool Beginning) {

863}

864

869

873 HasSplit |= Point.isSplit();

874 InsertPoints.emplace_back(&Point);

875}

876

878 bool Before)

879 : Instr(Instr), Before(Before) {

880

881

882 assert((!Before || !Instr.isPHI()) &&

883 "Splitting before phis requires more points");

884 assert((!Before || !Instr.getNextNode() || !Instr.getNextNode()->isPHI()) &&

885 "Splitting between phis does not make sense");

886}

887

889 if (isSplit()) {

890

891

892

893

894

895

896

897

898

899

900

901

902

904 }

905

906

907

908}

909

911

912 if (!Before)

913 return Instr.isTerminator();

914

915

916 return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();

917}

918

920

921

925 return 1;

927}

928

936

938

939

940

941

942 assert(Src.isSuccessor(DstOrSplit) && DstOrSplit->isPredecessor(&Src) &&

943 "This point has already been split");

945 assert(NewBB && "Invalid call to materialize");

946

947 DstOrSplit = NewBB;

948}

949

954 return 1;

957 return MBFI->getBlockFreq(DstOrSplit).getFrequency();

958

959 auto *MBPIWrapper =

962 MBPIWrapper ? &MBPIWrapper->getMBPI() : nullptr;

964 return 1;

965

966 return (MBFI->getBlockFreq(&Src) * MBPI->getEdgeProbability(&Src, DstOrSplit))

967 .getFrequency();

968}

969

971

972

973

974 assert(Src.succ_size() > 1 && DstOrSplit->pred_size() > 1 &&

975 "Edge is not critical");

976 return Src.canSplitCriticalEdge(DstOrSplit);

977}

978

980 : LocalFreq(LocalFreq.getFrequency()) {}

981

983

984 if (LocalCost + Cost < LocalCost) {

986 return true;

987 }

988 LocalCost += Cost;

989 return isSaturated();

990}

991

993

994 if (NonLocalCost + Cost < NonLocalCost) {

996 return true;

997 }

998 NonLocalCost += Cost;

999 return isSaturated();

1000}

1001

1002bool RegBankSelect::MappingCost::isSaturated() const {

1005}

1006

1011

1015

1017

1018 if (*this == Cost)

1019 return false;

1020

1021

1024

1025

1026 if (isSaturated() || Cost.isSaturated())

1027 return isSaturated() < Cost.isSaturated();

1028

1029

1030

1031

1032

1033

1037

1038

1039

1040 if (NonLocalCost == Cost.NonLocalCost)

1041

1042

1043 return LocalCost < Cost.LocalCost;

1044

1045

1046

1047 ThisLocalAdjust = 0;

1048 OtherLocalAdjust = 0;

1049 if (LocalCost < Cost.LocalCost)

1050 OtherLocalAdjust = Cost.LocalCost - LocalCost;

1051 else

1052 ThisLocalAdjust = LocalCost - Cost.LocalCost;

1053 } else {

1054 ThisLocalAdjust = LocalCost;

1055 OtherLocalAdjust = Cost.LocalCost;

1056 }

1057

1058

1059 uint64_t ThisNonLocalAdjust = 0;

1060 uint64_t OtherNonLocalAdjust = 0;

1061 if (NonLocalCost < Cost.NonLocalCost)

1062 OtherNonLocalAdjust = Cost.NonLocalCost - NonLocalCost;

1063 else

1064 ThisNonLocalAdjust = NonLocalCost - Cost.NonLocalCost;

1065

1066 uint64_t ThisScaledCost = ThisLocalAdjust * LocalFreq;

1067

1068 bool ThisOverflows = ThisLocalAdjust && (ThisScaledCost < ThisLocalAdjust ||

1069 ThisScaledCost < LocalFreq);

1070 uint64_t OtherScaledCost = OtherLocalAdjust * Cost.LocalFreq;

1071

1072 bool OtherOverflows =

1073 OtherLocalAdjust &&

1074 (OtherScaledCost < OtherLocalAdjust || OtherScaledCost < Cost.LocalFreq);

1075

1076 ThisOverflows |= ThisNonLocalAdjust &&

1077 ThisScaledCost + ThisNonLocalAdjust < ThisNonLocalAdjust;

1078 ThisScaledCost += ThisNonLocalAdjust;

1079 OtherOverflows |= OtherNonLocalAdjust &&

1080 OtherScaledCost + OtherNonLocalAdjust < OtherNonLocalAdjust;

1081 OtherScaledCost += OtherNonLocalAdjust;

1082

1083

1084 if (ThisOverflows && OtherOverflows)

1085 return false;

1086

1087 if (ThisOverflows || OtherOverflows)

1088 return ThisOverflows < OtherOverflows;

1089

1090 return ThisScaledCost < OtherScaledCost;

1091}

1092

1094 return LocalCost == Cost.LocalCost && NonLocalCost == Cost.NonLocalCost &&

1095 LocalFreq == Cost.LocalFreq;

1096}

1097

1098#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

1101 dbgs() << '\n';

1102}

1103#endif

1104

1107 OS << "impossible";

1108 return;

1109 }

1110 if (isSaturated()) {

1111 OS << "saturated";

1112 return;

1113 }

1114 OS << LocalFreq << " * " << LocalCost << " + " << NonLocalCost;

1115}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define clEnumValN(ENUMVAL, FLAGNAME, DESC)

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

#define LLVM_LIKELY(EXPR)

Interface for Targets to specify which operations they can successfully select and how the others sho...

MachineInstr unsigned OpIdx

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.

static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))

static cl::opt< RegBankSelect::Mode > RegBankSelectMode(cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast", "Run the Fast mode (default mapping)"), clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy", "Use the Greedy mode (best local mapping)")))

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

This file defines the SmallVector class.

Target-Independent Code Generator Pass Configuration Options pass.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

uint64_t getFrequency() const

Returns the frequency as a fixpoint number scaled by the entry frequency.

constexpr unsigned getScalarSizeInBits() const

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

const MachineBlockFrequencyInfo & getMBFI() const

MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<> > *LiveInSets=nullptr, MachineDomTreeUpdater *MDTU=nullptr)

MachineInstrBundleIterator< MachineInstr, true > reverse_iterator

MachineInstrBundleIterator< MachineInstr > iterator

LLVM_ABI BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const

getblockFreq - Return block frequency.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Pass interface - Implemented by all 'passes'.

AnalysisType & getAnalysis() const

getAnalysis() - This function is used by subclasses to get to the analysis information ...

Insertion point on an edge.

uint64_t frequency(const Pass &P) const override

Frequency of the insertion point.

Definition RegBankSelect.cpp:950

bool canMaterialize() const override

Check whether this insertion point can be materialized.

Definition RegBankSelect.cpp:970

Abstract class used to represent an insertion point in a CFG.

bool WasMaterialized

Tell if the insert point has already been materialized.

virtual void materialize()=0

Materialize the insertion point.

virtual bool canMaterialize() const

Check whether this insertion point can be materialized.

virtual bool isSplit() const

Does this point involve splitting an edge or block?

Insertion point before or after an instruction.

InstrInsertPoint(MachineInstr &Instr, bool Before=true)

Create an insertion point before (Before=true) or after Instr.

Definition RegBankSelect.cpp:877

bool isSplit() const override

Does this point involve splitting an edge or block?

Definition RegBankSelect.cpp:910

uint64_t frequency(const Pass &P) const override

Frequency of the insertion point.

Definition RegBankSelect.cpp:919

Insertion point at the beginning or end of a basic block.

uint64_t frequency(const Pass &P) const override

Frequency of the insertion point.

Definition RegBankSelect.cpp:929

Helper class used to represent the cost for mapping an instruction.

void saturate()

Saturate the cost to the maximal representable value.

Definition RegBankSelect.cpp:1007

bool operator==(const MappingCost &Cost) const

Check if this is equal to Cost.

Definition RegBankSelect.cpp:1093

bool addLocalCost(uint64_t Cost)

Add Cost to the local cost.

Definition RegBankSelect.cpp:982

void dump() const

Print this on dbgs() stream.

Definition RegBankSelect.cpp:1099

static MappingCost ImpossibleCost()

Return an instance of MappingCost that represents an impossible mapping.

Definition RegBankSelect.cpp:1012

bool addNonLocalCost(uint64_t Cost)

Add Cost to the non-local cost.

Definition RegBankSelect.cpp:992

bool operator<(const MappingCost &Cost) const

Check if this is less than Cost.

Definition RegBankSelect.cpp:1016

void print(raw_ostream &OS) const

Print this on OS;.

Definition RegBankSelect.cpp:1105

Struct used to represent the placement of a repairing point for a given operand.

unsigned getNumInsertPoints() const

bool canMaterialize() const

RepairingPlacement(MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingKind Kind=RepairingKind::Insert)

Create a repairing placement for the OpIdx-th operand of MI.

Definition RegBankSelect.cpp:761

unsigned getOpIdx() const

RepairingKind

Define the kind of action this repairing needs.

@ Insert

Reparing code needs to happen before InsertPoints.

@ None

Nothing to repair, just drop this action.

@ Reassign

(Re)assign the register bank of the operand.

@ Impossible

Mark this repairing placement as impossible.

void switchTo(RepairingKind NewKind)

Change the type of this repairing placement to NewKind.

void addInsertPoint(MachineBasicBlock &MBB, bool Beginning)

Definition RegBankSelect.cpp:860

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

Mode

List of the modes supported by the RegBankSelect pass.

@ Fast

Assign the register banks as fast as possible (default).

@ Greedy

Greedily minimize the cost of assigning register banks.

bool checkFunctionIsLegal(MachineFunction &MF) const

Check that our input is fully legal: we require the function to have the Legalized property,...

Definition RegBankSelect.cpp:722

MachineIRBuilder MIRBuilder

Helper class used for every code morphing.

MachineBlockFrequencyInfo * MBFI

Get the frequency of blocks.

Mode OptMode

Optimization mode of the pass.

const RegisterBankInfo::InstructionMapping & findBestMapping(MachineInstr &MI, RegisterBankInfo::InstructionMappings &PossibleMappings, SmallVectorImpl< RepairingPlacement > &RepairPts)

Find the best mapping for MI from PossibleMappings.

Definition RegBankSelect.cpp:289

bool assignInstr(MachineInstr &MI)

Assign the register bank of each operand of MI.

Definition RegBankSelect.cpp:634

bool assignRegisterBanks(MachineFunction &MF)

Walk through MF and assign a register bank to every virtual register that are still mapped to nothing...

Definition RegBankSelect.cpp:682

void init(MachineFunction &MF)

Initialize the field members using MF.

Definition RegBankSelect.cpp:82

void tryAvoidingSplit(RegBankSelect::RepairingPlacement &RepairPt, const MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping) const

When RepairPt involves splitting to repair MO for the given ValMapping, try to change the way we repa...

Definition RegBankSelect.cpp:324

const TargetRegisterInfo * TRI

Information on the register classes for the current function.

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition RegBankSelect.cpp:98

MachineBranchProbabilityInfo * MBPI

Get the frequency of the edges.

bool assignmentMatch(Register Reg, const RegisterBankInfo::ValueMapping &ValMapping, bool &OnlyAssign) const

Check if Reg is already assigned what is described by ValMapping.

Definition RegBankSelect.cpp:110

uint64_t getRepairCost(const MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping) const

Return the cost of the instruction needed to map MO to ValMapping.

Definition RegBankSelect.cpp:237

MappingCost computeMapping(MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping, SmallVectorImpl< RepairingPlacement > &RepairPts, const MappingCost *BestCost=nullptr)

Compute the cost of mapping MI with InstrMapping and compute the repairing placement for such mapping...

Definition RegBankSelect.cpp:444

bool repairReg(MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping, RegBankSelect::RepairingPlacement &RepairPt, const iterator_range< SmallVectorImpl< Register >::const_iterator > &NewVRegs)

Insert repairing code for Reg as specified by ValMapping.

Definition RegBankSelect.cpp:133

MachineRegisterInfo * MRI

MRI contains all the register class/bank information that this pass uses and updates.

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

Definition RegBankSelect.cpp:735

const RegisterBankInfo * RBI

Interface to the target lowering info related to register banks.

std::unique_ptr< MachineOptimizationRemarkEmitter > MORE

Current optimization remark emitter. Used to report failures.

bool applyMapping(MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping, SmallVectorImpl< RepairingPlacement > &RepairPts)

Apply Mapping to MI.

Definition RegBankSelect.cpp:589

Helper class that represents how the value of an instruction may be mapped and what is the related co...

unsigned getNumOperands() const

Get the number of operands.

unsigned getCost() const

Get the cost.

bool verify(const MachineInstr &MI) const

Verifiy that this mapping makes sense for MI.

bool isValid() const

Check whether this object is valid.

Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...

void createVRegs(unsigned OpIdx)

Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.

iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const

Get all the virtual registers required to map the OpIdx-th operand of the instruction.

SmallVector< const InstructionMapping *, 4 > InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

typename SuperClass::const_iterator const_iterator

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Target-Independent Code Generator Pass Configuration Options.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const RegisterBankInfo * getRegBankInfo() const

If the information for the register banks is available, return it.

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

A range adaptor for a pair of iterators.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

ValuesClass values(OptsTy... Options)

Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...

This is an optimization pass for GlobalISel generic memory operations.

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)

Get the size of a range.

bool isPreISelGenericOptimizationHint(unsigned Opcode)

LLVM_ABI cl::opt< bool > DisableGISelLegalityCheck

auto reverse(ContainerTy &&C)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void reportGISelFailure(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)

Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

LLVM_ABI Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)

Create Printable object to print register classes or register banks on a raw_ostream.

const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)

Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.

LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)

Modify analysis usage so it preserves passes required for the SelectionDAG fallback.

FunctionAddr VTableAddr Next

bool isTargetSpecificOpcode(unsigned Opcode)

Check whether the given Opcode is a target-specific opcode.

iterator_range< pointer_iterator< WrappedIteratorT > > make_pointer_range(RangeT &&Range)

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

const RegisterBank * RegBank

unsigned Length

Length of this mapping in bits.

Helper struct that represents how a value is mapped through different register banks.

bool partsAllUniform() const

unsigned NumBreakDowns

Number of partial mapping to break down this value.

const PartialMapping * BreakDown

How the value is broken down between the different register banks.