RegisterPressure.cpp Source File (original) (raw)

30#include "llvm/Config/llvm-config.h"

36#include

37#include

38#include

39#include

40#include

41#include

42#include

43#include

44#include

46using namespace llvm;

53 assert((PrevMask & ~NewMask).none() && "Must not remove bits");

54 if (PrevMask.any() || NewMask.none())

55 return;

58 unsigned Weight = PSetI.getWeight();

59 for (; PSetI.isValid(); ++PSetI)

60 CurrSetPressure[*PSetI] += Weight;

61}

68 assert((NewMask & ~PrevMask).none() && "Must not add bits");

69 if (NewMask.any() || PrevMask.none())

70 return;

73 unsigned Weight = PSetI.getWeight();

74 for (; PSetI.isValid(); ++PSetI) {

75 assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");

76 CurrSetPressure[*PSetI] -= Weight;

77 }

78}

80#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

84 for (unsigned i = 0, e = SetPressure.size(); i < e; ++i) {

85 if (SetPressure[i] != 0) {

86 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << ' ';

87 }

88 }

89 dbgs() << "\n";

90}

94 dbgs() << "Max Pressure: ";

96 dbgs() << "Live In: ";

99 if (.LaneMask.all())

101 dbgs() << ' ';

102 }

103 dbgs() << '\n';

104 dbgs() << "Live Out: ";

107 if (.LaneMask.all())

109 dbgs() << ' ';

110 }

111 dbgs() << '\n';

112}

113

117 dbgs() << "Curr Pressure: ";

119 }

120 P.dump(TRI);

121}

122

125 const char *sep = "";

128 break;

129 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet())

131 sep = " ";

132 }

133 dbgs() << '\n';

134}

135

140

142 dbgs() << "[Excess=";

144 dbgs() << ", CriticalMax=";

146 dbgs() << ", CurrentMax=";

148 dbgs() << "]\n";

149}

150

151#endif

152

156 if (PreviousMask.any() || NewMask.none())

157 return;

158

159 PSetIterator PSetI = MRI->getPressureSets(VRegOrUnit);

160 unsigned Weight = PSetI.getWeight();

161 for (; PSetI.isValid(); ++PSetI) {

162 CurrSetPressure[*PSetI] += Weight;

163 P.MaxSetPressure[*PSetI] =

164 std::max(P.MaxSetPressure[*PSetI], CurrSetPressure[*PSetI]);

165 }

166}

167

173

174

181

182

189

190

191

193 if (TopIdx <= NextTop)

194 return;

197}

198

199

201 if (TopPos != PrevTop)

202 return;

205}

206

207

214

215

222

225 unsigned NumRegUnits = TRI.getNumRegs();

226 unsigned NumVirtRegs = MRI.getNumVirtRegs();

227 Regs.setUniverse(NumRegUnits + NumVirtRegs);

228 this->NumRegUnits = NumRegUnits;

229}

230

234

241

243 MBB = nullptr;

244 LIS = nullptr;

245

246 CurrSetPressure.clear();

247 LiveThruPressure.clear();

248 P.MaxSetPressure.clear();

249

250 if (RequireIntervals)

252 else

254

255 LiveRegs.clear();

256 UntiedDefs.clear();

257}

258

259

260

261

267 bool TrackLaneMasks, bool TrackUntiedDefs) {

269

270 MF = mf;

272 RCI = rci;

273 MRI = &MF->getRegInfo();

274 MBB = mbb;

275 this->TrackUntiedDefs = TrackUntiedDefs;

276 this->TrackLaneMasks = TrackLaneMasks;

277

278 if (RequireIntervals) {

279 assert(lis && "IntervalPressure requires LiveIntervals");

280 LIS = lis;

281 }

282

283 CurrPos = pos;

284 CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0);

285

286 P.MaxSetPressure = CurrSetPressure;

287

288 LiveRegs.init(*MRI);

289 if (TrackUntiedDefs)

290 UntiedDefs.setUniverse(MRI->getNumVirtRegs());

291}

292

293

295 if (RequireIntervals)

299}

300

301

303 if (RequireIntervals)

304 return static_cast<IntervalPressure&>(P).BottomIdx.isValid();

307}

308

312 if (IdxPos == MBB->end())

313 return LIS->getMBBEndIdx(MBB);

314 return LIS->getInstructionIndex(*IdxPos).getRegSlot();

315}

316

317

319 if (RequireIntervals)

321 else

323

324 assert(P.LiveInRegs.empty() && "inconsistent max pressure result");

325 P.LiveInRegs.reserve(LiveRegs.size());

326 LiveRegs.appendTo(P.LiveInRegs);

327}

328

329

331 if (RequireIntervals)

333 else

335

336 assert(P.LiveOutRegs.empty() && "inconsistent max pressure result");

337 P.LiveOutRegs.reserve(LiveRegs.size());

338 LiveRegs.appendTo(P.LiveOutRegs);

339}

340

341

344 assert(LiveRegs.size() == 0 && "no region boundary");

345 return;

346 }

351

352}

353

354

355

356

357

359 LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0);

367 }

368}

369

373 return Other.VRegOrUnit == VRegOrUnit;

374 });

375 if (I == RegUnits.end())

377 return I->LaneMask;

378}

379

385 return Other.VRegOrUnit == VRegOrUnit;

386 });

387 if (I == RegUnits.end()) {

389 } else {

391 }

392}

393

397 return Other.VRegOrUnit == VRegOrUnit;

398 });

399 if (I == RegUnits.end()) {

401 } else {

403 }

404}

405

411 return Other.VRegOrUnit == VRegOrUnit;

412 });

413 if (I != RegUnits.end()) {

414 I->LaneMask &= ~Pair.LaneMask;

415 if (I->LaneMask.none())

417 }

418}

419

430 if (Property(SR, Pos))

431 Result |= SR.LaneMask;

432 }

433 } else if (Property(LI, Pos)) {

434 Result = TrackLaneMasks

437 }

438

439 return Result;

440 } else {

442

443

444 if (LR == nullptr)

445 return SafeDefault;

447 }

448}

449

458

459namespace {

460

461

462

463

464

465class RegisterOperandsCollector {

466 friend class llvm::RegisterOperands;

467

468 RegisterOperands &RegOpers;

469 const TargetRegisterInfo &TRI;

470 const MachineRegisterInfo &MRI;

471 bool IgnoreDead;

472

473 RegisterOperandsCollector(RegisterOperands &RegOpers,

474 const TargetRegisterInfo &TRI,

475 const MachineRegisterInfo &MRI, bool IgnoreDead)

476 : RegOpers(RegOpers), TRI(TRI), MRI(MRI), IgnoreDead(IgnoreDead) {}

477

478 void collectInstr(const MachineInstr &MI) const {

479 for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)

480 collectOperand(*OperI);

481

482

483 for (const VRegMaskOrUnit &P : RegOpers.Defs)

485 }

486

487 void collectInstrLanes(const MachineInstr &MI) const {

488 for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)

489 collectOperandLanes(*OperI);

490

491

492 for (const VRegMaskOrUnit &P : RegOpers.Defs)

494 }

495

496

497 void collectOperand(const MachineOperand &MO) const {

499 return;

501 if (MO.isUse()) {

503 pushReg(Reg, RegOpers.Uses);

504 } else {

506

508 pushReg(Reg, RegOpers.Uses);

509

511 if (!IgnoreDead)

513 } else

514 pushReg(Reg, RegOpers.Defs);

515 }

516 }

517

518 void pushReg(Register Reg, SmallVectorImpl &RegUnits) const {

522 } else if (MRI.isAllocatable(Reg)) {

523 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))

526 }

527 }

528

529 void collectOperandLanes(const MachineOperand &MO) const {

531 return;

533 unsigned SubRegIdx = MO.getSubReg();

534 if (MO.isUse()) {

536 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses);

537 } else {

539

541 SubRegIdx = 0;

542

544 if (!IgnoreDead)

545 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs);

546 } else

547 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);

548 }

549 }

550

551 void pushRegLanes(Register Reg, unsigned SubRegIdx,

552 SmallVectorImpl &RegUnits) const {

554 LaneBitmask LaneMask = SubRegIdx != 0

555 ? TRI.getSubRegIndexLaneMask(SubRegIdx)

556 : MRI.getMaxLaneMaskForVReg(Reg);

557 addRegLanes(RegUnits, VRegMaskOrUnit(VirtRegOrUnit(Reg), LaneMask));

558 } else if (MRI.isAllocatable(Reg)) {

559 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))

562 }

563 }

564};

565

566}

567

571 bool TrackLaneMasks, bool IgnoreDead) {

572 RegisterOperandsCollector Collector(*this, TRI, MRI, IgnoreDead);

573 if (TrackLaneMasks)

575 else

577}

578

582 for (auto *RI = Defs.begin(); RI != Defs.end(); ) {

584 if (LR != nullptr) {

587

588

590 RI = Defs.erase(RI);

591 continue;

592 }

593 }

594 ++RI;

595 }

596}

597

602 for (auto *I = Defs.begin(); I != Defs.end();) {

605

606

608 if (VRegOrUnit.isVirtualReg() && AddFlagsMI != nullptr &&

609 (LiveAfter & ~I->LaneMask).none())

611

612 LaneBitmask ActualDef = I->LaneMask & LiveAfter;

613 if (ActualDef.none()) {

615 } else {

616 I->LaneMask = ActualDef;

617 ++I;

618 }

619 }

620

621

622 for (auto &[VRegOrUnit, LaneMask] : Uses)

624

625 if (AddFlagsMI != nullptr) {

629 continue;

632 if (LiveAfter.none())

634 }

635 }

636}

637

638

640 Size = N;

641 if (N <= Max) {

643 return;

644 }

645 Max = Size;

646 free(PDiffArray);

648}

649

661

662

667 for (; PSetI.isValid(); ++PSetI) {

668

669 PressureDiff::iterator I = nonconst_begin(), E = nonconst_end();

670 for (; I != E && I->isValid(); ++I) {

671 if (I->getPSet() >= *PSetI)

672 break;

673 }

674

675 if (I == E)

676 break;

677

678 if (->isValid() || I->getPSet() != *PSetI) {

680 for (PressureDiff::iterator J = I; J != E && PTmp.isValid(); ++J)

682 }

683

684 unsigned NewUnitInc = I->getUnitInc() + Weight;

685 if (NewUnitInc != 0) {

686 I->setUnitInc(NewUnitInc);

687 } else {

688

689 PressureDiff::iterator J;

690 for (J = std::next(I); J != E && J->isValid(); ++J, ++I)

691 *I = *J;

693 }

694 }

695}

696

697

705

709

712 return Other.VRegOrUnit == VRegOrUnit;

713 });

716 if (I == LiveInOrOut.end()) {

720 } else {

721 PrevMask = I->LaneMask;

722 NewMask = PrevMask | Pair.LaneMask;

723 I->LaneMask = NewMask;

724 }

725 increaseSetPressure(P.MaxSetPressure, *MRI, VRegOrUnit, PrevMask, NewMask);

726}

727

731

735

738 LaneBitmask LiveMask = LiveRegs.contains(P.VRegOrUnit);

739 LaneBitmask BumpedMask = LiveMask | P.LaneMask;

741 }

743 LaneBitmask LiveMask = LiveRegs.contains(P.VRegOrUnit);

744 LaneBitmask BumpedMask = LiveMask | P.LaneMask;

746 }

747}

748

749

750

751

752

753

756 assert(!CurrPos->isDebugOrPseudoInstr());

757

758

760

761

762

765

766 LaneBitmask PreviousMask = LiveRegs.erase(Def);

767 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;

768

769 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;

770 if (LiveOut.any()) {

772

775 PreviousMask = LiveOut;

776 }

777

778 if (NewMask.none()) {

779

780

781 if (TrackLaneMasks && LiveUses != nullptr)

783 }

784

786 }

787

789 if (RequireIntervals)

790 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();

791

792

798 if (NewMask == PreviousMask)

799 continue;

800

801

802 if (PreviousMask.none()) {

803 if (LiveUses != nullptr) {

804 if (!TrackLaneMasks) {

806 } else {

808 return Other.VRegOrUnit == VRegOrUnit;

809 });

810 bool IsRedef = I != LiveUses->end();

811 if (IsRedef) {

812

813 assert(I->LaneMask.none());

815 } else {

817 }

818 }

819 }

820

821

822 if (RequireIntervals) {

824 if (LiveOut.any())

826 }

827 }

828

830 }

831 if (TrackUntiedDefs) {

835 (LiveRegs.contains(VRegOrUnit) & Def.LaneMask).none())

836 UntiedDefs.insert(VRegOrUnit.asVirtualReg());

837 }

838 }

839}

840

842 assert(CurrPos != MBB->begin());

845

846

849

850

851 CurrPos = prev_nodbg(CurrPos, MBB->begin());

852

854 if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())

855 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();

856

857

860}

861

864 if (CurrPos->isDebugOrPseudoInstr()) {

865

866

867 assert(CurrPos == MBB->begin());

868 return;

869 }

870

873 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);

874 if (TrackLaneMasks) {

877 } else if (RequireIntervals) {

879 }

880

881 recede(RegOpers, LiveUses);

882}

883

884

886 assert(!TrackUntiedDefs && "unsupported mode");

887 assert(CurrPos != MBB->end());

890

892 if (RequireIntervals)

894

895

897 if (RequireIntervals)

899 else

901 }

902

905 LaneBitmask LiveMask = LiveRegs.contains(VRegOrUnit);

907 if (LiveIn.any()) {

911 }

912

913 if (RequireIntervals) {

915 if (LastUseMask.any()) {

916 LiveRegs.erase(VRegMaskOrUnit(VRegOrUnit, LastUseMask));

918 }

919 }

920 }

921

922

924 LaneBitmask PreviousMask = LiveRegs.insert(Def);

925 LaneBitmask NewMask = PreviousMask | Def.LaneMask;

927 }

928

929

931

932

933 CurrPos = next_nodbg(CurrPos, MBB->end());

934}

935

939 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);

940 if (TrackLaneMasks) {

943 }

945}

946

947

954 for (unsigned i = 0, e = OldPressureVec.size(); i < e; ++i) {

955 unsigned POld = OldPressureVec[i];

956 unsigned PNew = NewPressureVec[i];

957 int PDiff = (int)PNew - (int)POld;

958 if (!PDiff)

959 continue;

960

962 if (!LiveThruPressureVec.empty())

963 Limit += LiveThruPressureVec[i];

964

965 if (Limit > POld) {

966 if (Limit > PNew)

967 PDiff = 0;

968 else

969 PDiff = PNew - Limit;

970 } else if (Limit > PNew)

971 PDiff = Limit - POld;

972

973 if (PDiff) {

976 break;

977 }

978 }

979}

980

981

982

983

984

985

986

994

995 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();

996 for (unsigned i = 0, e = OldMaxPressureVec.size(); i < e; ++i) {

997 unsigned POld = OldMaxPressureVec[i];

998 unsigned PNew = NewMaxPressureVec[i];

999 if (PNew == POld)

1000 continue;

1001

1003 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < i)

1004 ++CritIdx;

1005

1006 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == i) {

1007 int PDiff = (int)PNew - CriticalPSets[CritIdx].getUnitInc();

1008 if (PDiff > 0) {

1011 }

1012 }

1013 }

1014

1015

1016 if (!Delta.CurrentMax.isValid() && PNew > MaxPressureLimit[i]) {

1020 break;

1021 }

1022 }

1023}

1024

1025

1026

1027

1028

1029

1030

1032 assert(->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");

1033

1035 if (RequireIntervals)

1036 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();

1037

1038

1040 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, true);

1042 if (TrackLaneMasks)

1044 else if (RequireIntervals)

1046

1047

1048

1050

1051

1053 LaneBitmask LiveAfter = LiveRegs.contains(P.VRegOrUnit);

1056 LaneBitmask LiveBefore = (LiveAfter & ~DefLanes) | UseLanes;

1057

1058

1059

1061 }

1062

1064 LaneBitmask LiveAfter = LiveRegs.contains(P.VRegOrUnit);

1065 LaneBitmask LiveBefore = LiveAfter | P.LaneMask;

1067 }

1068}

1069

1070

1071

1072

1073

1074

1075

1076

1077

1078

1079

1080

1081

1082

1088

1089

1090

1091 std::vector SavedPressure = CurrSetPressure;

1092 std::vector SavedMaxPressure = P.MaxSetPressure;

1093

1095

1097 LiveThruPressure);

1099 MaxPressureLimit, Delta);

1102

1103

1104 P.MaxSetPressure.swap(SavedMaxPressure);

1105 CurrSetPressure.swap(SavedPressure);

1106

1107#ifndef NDEBUG

1108 if (!PDiff)

1109 return;

1110

1111

1114 if (Delta != Delta2) {

1115 dbgs() << "PDiff: ";

1116 PDiff->dump(*TRI);

1117 dbgs() << "DELTA: " << *MI;

1119 dbgs() << "Excess1 " << TRI->getRegPressureSetName(Delta.Excess.getPSet())

1128 dbgs() << "Excess2 " << TRI->getRegPressureSetName(Delta2.Excess.getPSet())

1137 }

1138#endif

1139}

1140

1141

1142

1143

1144

1145

1146

1147

1148

1149

1150

1156 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();

1158 PDiffI = PDiff.begin(), PDiffE = PDiff.end();

1159 PDiffI != PDiffE && PDiffI->isValid(); ++PDiffI) {

1160

1161 unsigned PSetID = PDiffI->getPSet();

1162 unsigned Limit = RCI->getRegPressureSetLimit(PSetID);

1163 if (!LiveThruPressure.empty())

1164 Limit += LiveThruPressure[PSetID];

1165

1166 unsigned POld = CurrSetPressure[PSetID];

1167 unsigned MOld = P.MaxSetPressure[PSetID];

1168 unsigned MNew = MOld;

1169

1170 unsigned PNew = POld + PDiffI->getUnitInc();

1171 assert((PDiffI->getUnitInc() >= 0) == (PNew >= POld)

1172 && "PSet overflow/underflow");

1173 if (PNew > MOld)

1174 MNew = PNew;

1175

1177 unsigned ExcessInc = 0;

1178 if (PNew > Limit)

1179 ExcessInc = POld > Limit ? PNew - POld : PNew - Limit;

1180 else if (POld > Limit)

1181 ExcessInc = Limit - POld;

1182 if (ExcessInc) {

1185 }

1186 }

1187

1188 if (MNew == MOld)

1189 continue;

1191 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < PSetID)

1192 ++CritIdx;

1193

1194 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {

1195 int CritInc = (int)MNew - CriticalPSets[CritIdx].getUnitInc();

1196 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {

1199 }

1200 }

1201 }

1202

1203 if (!Delta.CurrentMax.isValid() && MNew > MaxPressureLimit[PSetID]) {

1206 }

1207 }

1208}

1209

1210

1211

1212

1219

1226 continue;

1229 if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {

1230 unsigned SubRegIdx = MO.getSubReg();

1231 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);

1232 LastUseMask &= ~UseMask;

1233 if (LastUseMask.none())

1235 }

1236 }

1237 return LastUseMask;

1238}

1239

1242 assert(RequireIntervals);

1246}

1247

1250 assert(RequireIntervals);

1252 *LIS, *MRI, TrackLaneMasks, VRegOrUnit, Pos.getBaseIndex(),

1254 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);

1255 return S != nullptr && S->end == Pos.getRegSlot();

1256 });

1257}

1258

1261 assert(RequireIntervals);

1266 return S != nullptr && S->start < Pos.getRegSlot(true) &&

1268 });

1269}

1270

1271

1272

1273

1274

1275

1276

1278 assert(->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");

1279

1281 if (RequireIntervals)

1282 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();

1283

1284

1286 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, false);

1287 if (TrackLaneMasks)

1289

1290 if (RequireIntervals) {

1294 if (LastUseMask.none())

1295 continue;

1296

1297

1298

1299

1300

1302 LastUseMask =

1303 findUseBetween(VRegOrUnit, LastUseMask, CurrIdx, SlotIdx, *MRI, LIS);

1304 if (LastUseMask.none())

1305 continue;

1306

1307 LaneBitmask LiveMask = LiveRegs.contains(VRegOrUnit);

1308 LaneBitmask NewMask = LiveMask & ~LastUseMask;

1310 }

1311 }

1312

1313

1315 LaneBitmask LiveMask = LiveRegs.contains(Def.VRegOrUnit);

1316 LaneBitmask NewMask = LiveMask | Def.LaneMask;

1318 }

1319

1320

1322}

1323

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1339

1340 std::vector SavedPressure = CurrSetPressure;

1341 std::vector SavedMaxPressure = P.MaxSetPressure;

1342

1344

1346 LiveThruPressure);

1348 MaxPressureLimit, Delta);

1351

1352

1353 P.MaxSetPressure.swap(SavedMaxPressure);

1354 CurrSetPressure.swap(SavedPressure);

1355}

1356

1357

1360 std::vector &PressureResult,

1361 std::vector &MaxPressureResult) {

1362

1363 PressureResult = CurrSetPressure;

1364 MaxPressureResult = P.MaxSetPressure;

1365

1367

1368

1369 P.MaxSetPressure.swap(MaxPressureResult);

1370 CurrSetPressure.swap(PressureResult);

1371}

1372

1373

1376 std::vector &PressureResult,

1377 std::vector &MaxPressureResult) {

1378

1379 PressureResult = CurrSetPressure;

1380 MaxPressureResult = P.MaxSetPressure;

1381

1383

1384

1385 P.MaxSetPressure.swap(MaxPressureResult);

1386 CurrSetPressure.swap(PressureResult);

1387}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

A common definition of LaneBitmask for use in TableGen and CodeGen.

Promote Memory to Register

static void computeExcessPressureDelta(ArrayRef< unsigned > OldPressureVec, ArrayRef< unsigned > NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef< unsigned > LiveThruPressureVec)

Find the max change in excess pressure across all sets.

Definition RegisterPressure.cpp:948

static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, VirtRegOrUnit VRegOrUnit, SlotIndex Pos)

Definition RegisterPressure.cpp:450

static void increaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, VirtRegOrUnit VRegOrUnit, LaneBitmask PrevMask, LaneBitmask NewMask)

Increase pressure for each pressure set provided by TargetRegisterInfo.

Definition RegisterPressure.cpp:49

static LaneBitmask getRegLanes(ArrayRef< VRegMaskOrUnit > RegUnits, VirtRegOrUnit VRegOrUnit)

Definition RegisterPressure.cpp:370

static void removeRegLanes(SmallVectorImpl< VRegMaskOrUnit > &RegUnits, VRegMaskOrUnit Pair)

Definition RegisterPressure.cpp:406

static void computeMaxPressureDelta(ArrayRef< unsigned > OldMaxPressureVec, ArrayRef< unsigned > NewMaxPressureVec, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit, RegPressureDelta &Delta)

Find the max change in max pressure that either surpasses a critical PSet limit or exceeds the curren...

Definition RegisterPressure.cpp:987

static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, VirtRegOrUnit VRegOrUnit, SlotIndex Pos, LaneBitmask SafeDefault, bool(*Property)(const LiveRange &LR, SlotIndex Pos))

Definition RegisterPressure.cpp:421

static void setRegZero(SmallVectorImpl< VRegMaskOrUnit > &RegUnits, VirtRegOrUnit VRegOrUnit)

Definition RegisterPressure.cpp:394

static LaneBitmask findUseBetween(VirtRegOrUnit VRegOrUnit, LaneBitmask LastUseMask, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo &MRI, const LiveIntervals *LIS)

Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).

Definition RegisterPressure.cpp:1213

static const LiveRange * getLiveRange(const LiveIntervals &LIS, VirtRegOrUnit VRegOrUnit)

Definition RegisterPressure.cpp:235

static void addRegLanes(SmallVectorImpl< VRegMaskOrUnit > &RegUnits, VRegMaskOrUnit Pair)

Definition RegisterPressure.cpp:380

static void decreaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, VirtRegOrUnit VRegOrUnit, LaneBitmask PrevMask, LaneBitmask NewMask)

Decrease pressure for each pressure set provided by TargetRegisterInfo.

Definition RegisterPressure.cpp:64

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

LiveInterval & getInterval(Register Reg)

LiveRange * getCachedRegUnit(MCRegUnit Unit)

Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...

Result of a LiveRange query.

bool isDeadDef() const

Return true if this instruction has a dead def.

This class represents the liveness of a register, stack slot, etc.

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

bool liveAt(SlotIndex index) const

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

LLVM_ABI void clear()

Definition RegisterPressure.cpp:231

LLVM_ABI void init(const MachineRegisterInfo &MRI)

Definition RegisterPressure.cpp:223

MachineInstrBundleIterator< const MachineInstr > const_iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Representation of each machine instruction.

LLVM_ABI void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)

Mark all subregister defs of register Reg with the undef flag.

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

getReg - Returns the register number.

bool isInternalRead() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Iterate over the pressure sets affected by the given physical or virtual register.

unsigned getWeight() const

Capture a change in pressure for a single pressure set.

unsigned getPSetOrMax() const

LLVM_ABI void dump() const

Definition RegisterPressure.cpp:137

List of PressureChanges in order of increasing, unique PSetID.

const PressureChange * const_iterator

LLVM_ABI void dump(const TargetRegisterInfo &TRI) const

Definition RegisterPressure.cpp:124

const_iterator end() const

LLVM_ABI void addPressureChange(VirtRegOrUnit VRegOrUnit, bool IsDec, const MachineRegisterInfo *MRI)

Add a change in pressure to the pressure diff of a given instruction.

Definition RegisterPressure.cpp:663

const_iterator begin() const

LLVM_ABI void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)

Record pressure difference induced by the given operand list to node with index Idx.

Definition RegisterPressure.cpp:650

LLVM_ABI void init(unsigned N)

Initialize an array of N PressureDiffs.

Definition RegisterPressure.cpp:639

LLVM_ABI void closeRegion()

Finalize the region boundaries and recored live ins and live outs.

Definition RegisterPressure.cpp:342

LLVM_ABI void discoverLiveIn(VRegMaskOrUnit Pair)

Add Reg to the live in set and increase max pressure.

Definition RegisterPressure.cpp:728

LLVM_ABI void closeBottom()

Set the boundary for the bottom of the region and summarize live outs.

Definition RegisterPressure.cpp:330

LLVM_ABI void recede(SmallVectorImpl< VRegMaskOrUnit > *LiveUses=nullptr)

Recede across the previous instruction.

Definition RegisterPressure.cpp:862

LLVM_ABI void bumpDownwardPressure(const MachineInstr *MI)

Record the downward impact of a single instruction on current register pressure.

Definition RegisterPressure.cpp:1277

LLVM_ABI void addLiveRegs(ArrayRef< VRegMaskOrUnit > Regs)

Force liveness of virtual registers or physical register units.

Definition RegisterPressure.cpp:698

LLVM_ABI void recedeSkipDebugValues()

Recede until we find an instruction which is not a DebugValue.

Definition RegisterPressure.cpp:841

LLVM_ABI void getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)

Consider the pressure increase caused by traversing this instruction bottom-up.

Definition RegisterPressure.cpp:1084

LLVM_ABI void initLiveThru(const RegPressureTracker &RPTracker)

Initialize the LiveThru pressure set based on the untied defs found in RPTracker.

Definition RegisterPressure.cpp:358

LLVM_ABI void bumpDeadDefs(ArrayRef< VRegMaskOrUnit > DeadDefs)

Definition RegisterPressure.cpp:736

RegPressureTracker(IntervalPressure &rp)

LLVM_ABI void dump() const

Definition RegisterPressure.cpp:115

LLVM_ABI void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)

Setup the RegPressureTracker.

Definition RegisterPressure.cpp:262

LLVM_ABI void discoverLiveInOrOut(VRegMaskOrUnit Pair, SmallVectorImpl< VRegMaskOrUnit > &LiveInOrOut)

Definition RegisterPressure.cpp:706

LLVM_ABI LaneBitmask getLiveThroughAt(VirtRegOrUnit VRegOrUnit, SlotIndex Pos) const

Definition RegisterPressure.cpp:1259

LLVM_ABI bool isBottomClosed() const

Does this pressure result have a valid bottom position and live outs.

Definition RegisterPressure.cpp:302

LLVM_ABI LaneBitmask getLiveLanesAt(VirtRegOrUnit VRegOrUnit, SlotIndex Pos) const

Definition RegisterPressure.cpp:1240

bool hasUntiedDef(Register VirtReg) const

LLVM_ABI void closeTop()

Set the boundary for the top of the region and summarize live ins.

Definition RegisterPressure.cpp:318

LLVM_ABI void getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)

Consider the pressure increase caused by traversing this instruction top-down.

Definition RegisterPressure.cpp:1336

LLVM_ABI void advance()

Advance across the current instruction.

Definition RegisterPressure.cpp:936

LLVM_ABI bool isTopClosed() const

Does this pressure result have a valid top position and live ins.

Definition RegisterPressure.cpp:294

LLVM_ABI void bumpUpwardPressure(const MachineInstr *MI)

Record the upward impact of a single instruction on current register pressure.

Definition RegisterPressure.cpp:1031

LLVM_ABI LaneBitmask getLastUsedLanes(VirtRegOrUnit VRegOrUnit, SlotIndex Pos) const

Definition RegisterPressure.cpp:1248

LLVM_ABI void increaseRegPressure(VirtRegOrUnit VRegOrUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)

Definition RegisterPressure.cpp:153

LLVM_ABI void getDownwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)

Get the pressure of each PSet after traversing this instruction top-down.

Definition RegisterPressure.cpp:1375

LLVM_ABI void reset()

Definition RegisterPressure.cpp:242

LLVM_ABI SlotIndex getCurrSlot() const

Get the SlotIndex for the first nondebug instruction including or after the current position.

Definition RegisterPressure.cpp:309

LLVM_ABI void decreaseRegPressure(VirtRegOrUnit VRegOrUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)

Definition RegisterPressure.cpp:168

LLVM_ABI void getUpwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)

Get the pressure of each PSet after traversing this instruction bottom-up.

Definition RegisterPressure.cpp:1359

LLVM_ABI void discoverLiveOut(VRegMaskOrUnit Pair)

Add Reg to the live out set and increase max pressure.

Definition RegisterPressure.cpp:732

LLVM_ABI void getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit) const

This is the fast version of querying register pressure that does not directly depend on current liven...

Definition RegisterPressure.cpp:1152

unsigned getRegPressureSetLimit(unsigned Idx) const

Get the register unit limit for the given pressure set index.

List of registers defined and used by a machine instruction.

SmallVector< VRegMaskOrUnit, 8 > Defs

List of virtual registers and register units defined by the instruction which are not dead.

LLVM_ABI void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)

Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...

Definition RegisterPressure.cpp:568

SmallVector< VRegMaskOrUnit, 8 > DeadDefs

List of virtual registers and register units defined by the instruction but dead.

LLVM_ABI void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)

Use liveness information to find out which uses/defs are partially undefined/dead and adjust the VReg...

Definition RegisterPressure.cpp:598

LLVM_ABI void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS)

Use liveness information to find dead defs not marked with a dead flag and move them to the DeadDefs ...

Definition RegisterPressure.cpp:579

SmallVector< VRegMaskOrUnit, 8 > Uses

List of virtual registers and register units read by the instruction.

Wrapper class representing virtual and physical registers.

MCRegister asMCReg() const

Utility to check-convert this value to a MCRegister.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

SlotIndex - An opaque wrapper around machine indexes.

SlotIndex getDeadSlot() const

Returns the dead def kill slot for the current instruction.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

iterator erase(const_iterator CI)

void push_back(const T &Elt)

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

A Use represents the edge between a Value definition and its users.

Wrapper class representing a virtual register or register unit.

constexpr bool isVirtualReg() const

constexpr MCRegUnit asMCRegUnit() const

constexpr Register asVirtualReg() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It, then continue incrementing it while it points to a debug instruction.

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)

IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It until it points to a non-debug instruction or to End and return the resulting iterator.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI void dumpRegSetPressure(ArrayRef< unsigned > SetPressure, const TargetRegisterInfo *TRI)

Definition RegisterPressure.cpp:82

IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)

Decrement It, then continue decrementing it while it points to a debug instruction.

LLVM_ABI Printable printVRegOrUnit(VirtRegOrUnit VRegOrUnit, const TargetRegisterInfo *TRI)

Create Printable object to print virtual registers and physical registers on a raw_ostream.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.

LLVM_ABI void reset()

Clear the result so it can be used for another round of pressure tracking.

Definition RegisterPressure.cpp:175

LLVM_ABI void openBottom(SlotIndex PrevBottom)

If the current bottom is not greater than the previous index, open it.

Definition RegisterPressure.cpp:208

SlotIndex TopIdx

Record the boundary of the region being tracked.

LLVM_ABI void openTop(SlotIndex NextTop)

If the current top is not less than or equal to the next index, open it.

Definition RegisterPressure.cpp:192

static constexpr LaneBitmask getAll()

constexpr bool none() const

constexpr bool any() const

static constexpr LaneBitmask getNone()

This represents a simple continuous liveness interval for a value.

Store the effects of a change in pressure on things that MI scheduler cares about.

PressureChange CriticalMax

PressureChange CurrentMax

LLVM_ABI void dump() const

Definition RegisterPressure.cpp:141

RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.

MachineBasicBlock::const_iterator TopPos

Record the boundary of the region being tracked.

MachineBasicBlock::const_iterator BottomPos

LLVM_ABI void openTop(MachineBasicBlock::const_iterator PrevTop)

If the current top is the previous instruction (before receding), open it.

Definition RegisterPressure.cpp:200

LLVM_ABI void reset()

Clear the result so it can be used for another round of pressure tracking.

Definition RegisterPressure.cpp:183

LLVM_ABI void openBottom(MachineBasicBlock::const_iterator PrevBottom)

If the current bottom is the previous instr (before advancing), open it.

Definition RegisterPressure.cpp:216

SmallVector< VRegMaskOrUnit, 8 > LiveOutRegs

SmallVector< VRegMaskOrUnit, 8 > LiveInRegs

List of live in virtual registers or physical register units.

LLVM_ABI void dump(const TargetRegisterInfo *TRI) const

Definition RegisterPressure.cpp:93

std::vector< unsigned > MaxSetPressure

Map of max reg pressure indexed by pressure set ID, not class ID.