RegisterPressure.cpp Source File (original) (raw)

30#include "llvm/Config/llvm-config.h"

36#include

37#include

38#include

39#include

40#include

41#include

42#include

43#include

44#include

46using namespace llvm;

52 assert((PrevMask & ~NewMask).none() && "Must not remove bits");

53 if (PrevMask.any() || NewMask.none())

54 return;

57 unsigned Weight = PSetI.getWeight();

58 for (; PSetI.isValid(); ++PSetI)

59 CurrSetPressure[*PSetI] += Weight;

60}

66 assert((NewMask & ~PrevMask).none() && "Must not add bits");

67 if (NewMask.any() || PrevMask.none())

68 return;

71 unsigned Weight = PSetI.getWeight();

72 for (; PSetI.isValid(); ++PSetI) {

73 assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");

74 CurrSetPressure[*PSetI] -= Weight;

75 }

76}

78#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

82 bool Empty = true;

83 for (unsigned i = 0, e = SetPressure.size(); i < e; ++i) {

84 if (SetPressure[i] != 0) {

85 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n';

86 Empty = false;

87 }

88 }

89 if (Empty)

90 dbgs() << "\n";

91}

95 dbgs() << "Max Pressure: ";

97 dbgs() << "Live In: ";

100 if (.LaneMask.all())

102 dbgs() << ' ';

103 }

104 dbgs() << '\n';

105 dbgs() << "Live Out: ";

108 if (.LaneMask.all())

110 dbgs() << ' ';

111 }

112 dbgs() << '\n';

113}

114

118 dbgs() << "Curr Pressure: ";

120 }

122}

123

126 const char *sep = "";

129 break;

130 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet())

132 sep = " ";

133 }

134 dbgs() << '\n';

135}

136

140}

141

143 dbgs() << "[Excess=";

145 dbgs() << ", CriticalMax=";

147 dbgs() << ", CurrentMax=";

149 dbgs() << "]\n";

150}

151

152#endif

153

157 if (PreviousMask.any() || NewMask.none())

158 return;

159

161 unsigned Weight = PSetI.getWeight();

162 for (; PSetI.isValid(); ++PSetI) {

163 CurrSetPressure[*PSetI] += Weight;

165 std::max(P.MaxSetPressure[*PSetI], CurrSetPressure[*PSetI]);

166 }

167}

168

172 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask);

173}

174

175

181}

182

183

189}

190

191

192

194 if (TopIdx <= NextTop)

195 return;

198}

199

200

202 if (TopPos != PrevTop)

203 return;

206}

207

208

211 return;

214}

215

216

219 return;

222}

223

226 unsigned NumRegUnits = TRI.getNumRegs();

227 unsigned NumVirtRegs = MRI.getNumVirtRegs();

228 Regs.setUniverse(NumRegUnits + NumVirtRegs);

229 this->NumRegUnits = NumRegUnits;

230}

231

234}

235

240}

241

243 MBB = nullptr;

244 LIS = nullptr;

245

246 CurrSetPressure.clear();

247 LiveThruPressure.clear();

249

250 if (RequireIntervals)

252 else

254

255 LiveRegs.clear();

256 UntiedDefs.clear();

257}

258

259

260

261

267 bool TrackLaneMasks, bool TrackUntiedDefs) {

269

270 MF = mf;

272 RCI = rci;

274 MBB = mbb;

275 this->TrackUntiedDefs = TrackUntiedDefs;

276 this->TrackLaneMasks = TrackLaneMasks;

277

278 if (RequireIntervals) {

279 assert(lis && "IntervalPressure requires LiveIntervals");

280 LIS = lis;

281 }

282

283 CurrPos = pos;

285

287

288 LiveRegs.init(*MRI);

289 if (TrackUntiedDefs)

291}

292

293

295 if (RequireIntervals)

299}

300

301

303 if (RequireIntervals)

304 return static_cast<IntervalPressure&>(P).BottomIdx.isValid();

307}

308

312 if (IdxPos == MBB->end())

315}

316

317

319 if (RequireIntervals)

321 else

323

324 assert(P.LiveInRegs.empty() && "inconsistent max pressure result");

327}

328

329

331 if (RequireIntervals)

333 else

335

336 assert(P.LiveOutRegs.empty() && "inconsistent max pressure result");

339}

340

341

344 assert(LiveRegs.size() == 0 && "no region boundary");

345 return;

346 }

351

352}

353

354

355

356

357

366 }

367}

368

372 return Other.RegUnit == RegUnit;

373 });

374 if (I == RegUnits.end())

376 return I->LaneMask;

377}

378

384 return Other.RegUnit == RegUnit;

385 });

386 if (I == RegUnits.end()) {

388 } else {

390 }

391}

392

396 return Other.RegUnit == RegUnit;

397 });

398 if (I == RegUnits.end()) {

400 } else {

402 }

403}

404

410 return Other.RegUnit == RegUnit;

411 });

412 if (I != RegUnits.end()) {

413 I->LaneMask &= ~Pair.LaneMask;

414 if (I->LaneMask.none())

416 }

417}

418

429 if (Property(SR, Pos))

430 Result |= SR.LaneMask;

431 }

432 } else if (Property(LI, Pos)) {

433 Result = TrackLaneMasks ? MRI.getMaxLaneMaskForVReg(RegUnit)

435 }

436

437 return Result;

438 } else {

440

441

442 if (LR == nullptr)

443 return SafeDefault;

445 }

446}

447

450 bool TrackLaneMasks, Register RegUnit,

455 return LR.liveAt(Pos);

456 });

457}

458

459namespace {

460

461

462

463

464

465class RegisterOperandsCollector {

467

471 bool IgnoreDead;

472

476 : RegOpers(RegOpers), TRI(TRI), MRI(MRI), IgnoreDead(IgnoreDead) {}

477

480 collectOperand(*OperI);

481

482

485 }

486

487 void collectInstrLanes(const MachineInstr &MI) const {

489 collectOperandLanes(*OperI);

490

491

494 }

495

496

497 void collectOperand(const MachineOperand &MO) const {

499 return;

501 if (MO.isUse()) {

503 pushReg(Reg, RegOpers.Uses);

504 } else {

506

508 pushReg(Reg, RegOpers.Uses);

509

511 if (!IgnoreDead)

513 } else

514 pushReg(Reg, RegOpers.Defs);

515 }

516 }

517

520 if (Reg.isVirtual()) {

522 } else if (MRI.isAllocatable(Reg)) {

525 }

526 }

527

528 void collectOperandLanes(const MachineOperand &MO) const {

530 return;

532 unsigned SubRegIdx = MO.getSubReg();

533 if (MO.isUse()) {

535 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses);

536 } else {

538

540 SubRegIdx = 0;

541

543 if (!IgnoreDead)

544 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs);

545 } else

546 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);

547 }

548 }

549

550 void pushRegLanes(Register Reg, unsigned SubRegIdx,

552 if (Reg.isVirtual()) {

554 ? TRI.getSubRegIndexLaneMask(SubRegIdx)

555 : MRI.getMaxLaneMaskForVReg(Reg);

557 } else if (MRI.isAllocatable(Reg)) {

560 }

561 }

562};

563

564}

565

569 bool TrackLaneMasks, bool IgnoreDead) {

570 RegisterOperandsCollector Collector(*this, TRI, MRI, IgnoreDead);

571 if (TrackLaneMasks)

573 else

575}

576

580 for (auto *RI = Defs.begin(); RI != Defs.end(); ) {

583 if (LR != nullptr) {

586

587

589 RI = Defs.erase(RI);

590 continue;

591 }

592 }

593 ++RI;

594 }

595}

596

601 for (auto *I = Defs.begin(); I != Defs.end();) {

604

605

607 if (RegUnit.isVirtual() && AddFlagsMI != nullptr &&

608 (LiveAfter & ~I->LaneMask).none())

610

611 LaneBitmask ActualDef = I->LaneMask & LiveAfter;

612 if (ActualDef.none()) {

614 } else {

615 I->LaneMask = ActualDef;

616 ++I;

617 }

618 }

619

620

621 for (auto &[RegUnit, LaneMask] : Uses)

623

624 if (AddFlagsMI != nullptr) {

628 continue;

631 if (LiveAfter.none())

633 }

634 }

635}

636

637

640 if (N <= Max) {

642 return;

643 }

645 free(PDiffArray);

647}

648

656

659}

660

661

666 for (; PSetI.isValid(); ++PSetI) {

667

669 for (; I != E && I->isValid(); ++I) {

670 if (I->getPSet() >= *PSetI)

671 break;

672 }

673

674 if (I == E)

675 break;

676

677 if (->isValid() || I->getPSet() != *PSetI) {

681 }

682

683 unsigned NewUnitInc = I->getUnitInc() + Weight;

684 if (NewUnitInc != 0) {

685 I->setUnitInc(NewUnitInc);

686 } else {

687

689 for (J = std::next(I); J != E && J->isValid(); ++J, ++I)

690 *I = *J;

692 }

693 }

694}

695

696

702 }

703}

704

708

711 return Other.RegUnit == RegUnit;

712 });

715 if (I == LiveInOrOut.end()) {

719 } else {

720 PrevMask = I->LaneMask;

721 NewMask = PrevMask | Pair.LaneMask;

722 I->LaneMask = NewMask;

723 }

725}

726

729}

730

733}

734

739 LaneBitmask BumpedMask = LiveMask | P.LaneMask;

741 }

745 LaneBitmask BumpedMask = LiveMask | P.LaneMask;

747 }

748}

749

750

751

752

753

754

757 assert(!CurrPos->isDebugOrPseudoInstr());

758

759

761

762

763

766

768 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;

769

770 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;

771 if (LiveOut.any()) {

773

775 LiveOut);

776 PreviousMask = LiveOut;

777 }

778

779 if (NewMask.none()) {

780

781

782 if (TrackLaneMasks && LiveUses != nullptr)

784 }

785

787 }

788

790 if (RequireIntervals)

792

793

799 if (NewMask == PreviousMask)

800 continue;

801

802

803 if (PreviousMask.none()) {

804 if (LiveUses != nullptr) {

805 if (!TrackLaneMasks) {

807 } else {

808 auto I =

811 });

812 bool IsRedef = I != LiveUses->end();

813 if (IsRedef) {

814

815 assert(I->LaneMask.none());

817 } else {

819 }

820 }

821 }

822

823

824 if (RequireIntervals) {

826 if (LiveOut.any())

828 }

829 }

830

832 }

833 if (TrackUntiedDefs) {

835 Register RegUnit = Def.RegUnit;

837 (LiveRegs.contains(RegUnit) & Def.LaneMask).none())

838 UntiedDefs.insert(RegUnit);

839 }

840 }

841}

842

847

848

851

852

854

856 if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())

858

859

862}

863

866 if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {

867

868

870 return;

871 }

872

875 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);

876 if (TrackLaneMasks) {

879 } else if (RequireIntervals) {

881 }

882

883 recede(RegOpers, LiveUses);

884}

885

886

888 assert(!TrackUntiedDefs && "unsupported mode");

892

894 if (RequireIntervals)

896

897

899 if (RequireIntervals)

901 else

903 }

904

909 if (LiveIn.any()) {

913 }

914

915 if (RequireIntervals) {

917 if (LastUseMask.any()) {

920 }

921 }

922 }

923

924

927 LaneBitmask NewMask = PreviousMask | Def.LaneMask;

929 }

930

931

933

934

936}

937

942 if (TrackLaneMasks) {

945 }

947}

948

949

956 for (unsigned i = 0, e = OldPressureVec.size(); i < e; ++i) {

957 unsigned POld = OldPressureVec[i];

958 unsigned PNew = NewPressureVec[i];

959 int PDiff = (int)PNew - (int)POld;

960 if (!PDiff)

961 continue;

962

964 if (!LiveThruPressureVec.empty())

965 Limit += LiveThruPressureVec[i];

966

967 if (Limit > POld) {

968 if (Limit > PNew)

969 PDiff = 0;

970 else

971 PDiff = PNew - Limit;

972 } else if (Limit > PNew)

973 PDiff = Limit - POld;

974

975 if (PDiff) {

978 break;

979 }

980 }

981}

982

983

984

985

986

987

988

996

997 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();

998 for (unsigned i = 0, e = OldMaxPressureVec.size(); i < e; ++i) {

999 unsigned POld = OldMaxPressureVec[i];

1000 unsigned PNew = NewMaxPressureVec[i];

1001 if (PNew == POld)

1002 continue;

1003

1005 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < i)

1006 ++CritIdx;

1007

1008 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == i) {

1009 int PDiff = (int)PNew - (int)CriticalPSets[CritIdx].getUnitInc();

1010 if (PDiff > 0) {

1013 }

1014 }

1015 }

1016

1017

1018 if (!Delta.CurrentMax.isValid() && PNew > MaxPressureLimit[i]) {

1022 break;

1023 }

1024 }

1025}

1026

1027

1028

1029

1030

1031

1032

1034 assert(->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");

1035

1037 if (RequireIntervals)

1039

1040

1042 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, true);

1044 if (TrackLaneMasks)

1046 else if (RequireIntervals)

1048

1049

1050

1052

1053

1059 LaneBitmask LiveBefore = (LiveAfter & ~DefLanes) | UseLanes;

1060

1061

1062

1064 }

1065

1069 LaneBitmask LiveBefore = LiveAfter | P.LaneMask;

1071 }

1072}

1073

1074

1075

1076

1077

1078

1079

1080

1081

1082

1083

1084

1085

1086

1092

1093

1094

1095 std::vector SavedPressure = CurrSetPressure;

1096 std::vector SavedMaxPressure = P.MaxSetPressure;

1097

1099

1101 LiveThruPressure);

1103 MaxPressureLimit, Delta);

1106

1107

1108 P.MaxSetPressure.swap(SavedMaxPressure);

1109 CurrSetPressure.swap(SavedPressure);

1110

1111#ifndef NDEBUG

1112 if (!PDiff)

1113 return;

1114

1115

1118 if (Delta != Delta2) {

1119 dbgs() << "PDiff: ";

1121 dbgs() << "DELTA: " << *MI;

1141 }

1142#endif

1143}

1144

1145

1146

1147

1148

1149

1150

1151

1152

1153

1154

1160 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();

1162 PDiffI = PDiff.begin(), PDiffE = PDiff.end();

1163 PDiffI != PDiffE && PDiffI->isValid(); ++PDiffI) {

1164

1165 unsigned PSetID = PDiffI->getPSet();

1167 if (!LiveThruPressure.empty())

1168 Limit += LiveThruPressure[PSetID];

1169

1170 unsigned POld = CurrSetPressure[PSetID];

1171 unsigned MOld = P.MaxSetPressure[PSetID];

1172 unsigned MNew = MOld;

1173

1174 unsigned PNew = POld + PDiffI->getUnitInc();

1175 assert((PDiffI->getUnitInc() >= 0) == (PNew >= POld)

1176 && "PSet overflow/underflow");

1177 if (PNew > MOld)

1178 MNew = PNew;

1179

1181 unsigned ExcessInc = 0;

1182 if (PNew > Limit)

1183 ExcessInc = POld > Limit ? PNew - POld : PNew - Limit;

1184 else if (POld > Limit)

1185 ExcessInc = Limit - POld;

1186 if (ExcessInc) {

1189 }

1190 }

1191

1192 if (MNew == MOld)

1193 continue;

1195 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < PSetID)

1196 ++CritIdx;

1197

1198 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {

1199 int CritInc = (int)MNew - (int)CriticalPSets[CritIdx].getUnitInc();

1200 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {

1203 }

1204 }

1205 }

1206

1207 if (!Delta.CurrentMax.isValid() && MNew > MaxPressureLimit[PSetID]) {

1210 }

1211 }

1212}

1213

1214

1215

1216

1224 continue;

1227 if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {

1228 unsigned SubRegIdx = MO.getSubReg();

1229 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);

1230 LastUseMask &= ~UseMask;

1231 if (LastUseMask.none())

1233 }

1234 }

1235 return LastUseMask;

1236}

1237

1240 assert(RequireIntervals);

1244 return LR.liveAt(Pos);

1245 });

1246}

1247

1250 assert(RequireIntervals);

1254 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);

1255 return S != nullptr && S->end == Pos.getRegSlot();

1256 });

1257}

1258

1261 assert(RequireIntervals);

1266 return S != nullptr && S->start < Pos.getRegSlot(true) &&

1268 });

1269}

1270

1271

1272

1273

1274

1275

1276

1278 assert(->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");

1279

1281 if (RequireIntervals)

1283

1284

1286 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, false);

1287 if (TrackLaneMasks)

1289

1290 if (RequireIntervals) {

1294 if (LastUseMask.none())

1295 continue;

1296

1297

1298

1299

1300

1302 LastUseMask

1304 if (LastUseMask.none())

1305 continue;

1306

1308 LaneBitmask NewMask = LiveMask & ~LastUseMask;

1310 }

1311 }

1312

1313

1317 LaneBitmask NewMask = LiveMask | Def.LaneMask;

1319 }

1320

1321

1323}

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1335

1340

1341 std::vector SavedPressure = CurrSetPressure;

1342 std::vector SavedMaxPressure = P.MaxSetPressure;

1343

1345

1347 LiveThruPressure);

1349 MaxPressureLimit, Delta);

1352

1353

1354 P.MaxSetPressure.swap(SavedMaxPressure);

1355 CurrSetPressure.swap(SavedPressure);

1356}

1357

1358

1361 std::vector &PressureResult,

1362 std::vector &MaxPressureResult) {

1363

1364 PressureResult = CurrSetPressure;

1365 MaxPressureResult = P.MaxSetPressure;

1366

1368

1369

1370 P.MaxSetPressure.swap(MaxPressureResult);

1371 CurrSetPressure.swap(PressureResult);

1372}

1373

1374

1377 std::vector &PressureResult,

1378 std::vector &MaxPressureResult) {

1379

1380 PressureResult = CurrSetPressure;

1381 MaxPressureResult = P.MaxSetPressure;

1382

1384

1385

1386 P.MaxSetPressure.swap(MaxPressureResult);

1387 CurrSetPressure.swap(PressureResult);

1388}

unsigned const MachineRegisterInfo * MRI

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

A common definition of LaneBitmask for use in TableGen and CodeGen.

unsigned const TargetRegisterInfo * TRI

static void computeExcessPressureDelta(ArrayRef< unsigned > OldPressureVec, ArrayRef< unsigned > NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef< unsigned > LiveThruPressureVec)

Find the max change in excess pressure across all sets.

static void removeRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)

static void increaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask)

Increase pressure for each pressure set provided by TargetRegisterInfo.

static void decreaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask)

Decrease pressure for each pressure set provided by TargetRegisterInfo.

static void computeMaxPressureDelta(ArrayRef< unsigned > OldMaxPressureVec, ArrayRef< unsigned > NewMaxPressureVec, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit, RegPressureDelta &Delta)

Find the max change in max pressure that either surpasses a critical PSet limit or exceeds the curren...

static const LiveRange * getLiveRange(const LiveIntervals &LIS, unsigned Reg)

static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos)

static void addRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)

static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo &MRI, const LiveIntervals *LIS)

Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).

static void setRegZero(SmallVectorImpl< RegisterMaskPair > &RegUnits, Register RegUnit)

static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, LaneBitmask SafeDefault, bool(*Property)(const LiveRange &LR, SlotIndex Pos))

static LaneBitmask getRegLanes(ArrayRef< RegisterMaskPair > RegUnits, Register RegUnit)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const

Return the last index in the given basic block.

LiveRange * getCachedRegUnit(unsigned Unit)

Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...

LiveInterval & getInterval(Register Reg)

Result of a LiveRange query.

bool isDeadDef() const

Return true if this instruction has a dead def.

This class represents the liveness of a register, stack slot, etc.

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

bool liveAt(SlotIndex index) const

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

LaneBitmask contains(Register Reg) const

void init(const MachineRegisterInfo &MRI)

LaneBitmask insert(RegisterMaskPair Pair)

Mark the Pair.LaneMask lanes of Pair.Reg as live.

LaneBitmask erase(RegisterMaskPair Pair)

Clears the Pair.LaneMask lanes of Pair.Reg (mark them as dead).

void appendTo(ContainerT &To) const

bool isValid() const

isValid - Returns true until all the operands have been visited.

MachineInstrBundleIterator< const MachineInstr > const_iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Representation of each machine instruction.

void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)

Mark all subregister defs of register Reg with the undef flag.

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

getReg - Returns the register number.

bool isInternalRead() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

PSetIterator getPressureSets(Register RegUnit) const

Get an iterator over the pressure sets affected by the given physical or virtual register.

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

Iterate over the pressure sets affected by the given physical or virtual register.

unsigned getWeight() const

Capture a change in pressure for a single pressure set.

unsigned getPSetOrMax() const

List of PressureChanges in order of increasing, unique PSetID.

void dump(const TargetRegisterInfo &TRI) const

void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI)

Add a change in pressure to the pressure diff of a given instruction.

const_iterator end() const

const_iterator begin() const

void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)

Record pressure difference induced by the given operand list to node with index Idx.

void init(unsigned N)

Initialize an array of N PressureDiffs.

Track the current register pressure at some position in the instruction stream, and remember the high...

void closeRegion()

Finalize the region boundaries and recored live ins and live outs.

void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)

Recede across the previous instruction.

void closeBottom()

Set the boundary for the bottom of the region and summarize live outs.

void bumpDownwardPressure(const MachineInstr *MI)

Record the downward impact of a single instruction on current register pressure.

void recedeSkipDebugValues()

Recede until we find an instruction which is not a DebugValue.

void getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)

Consider the pressure increase caused by traversing this instruction bottom-up.

void initLiveThru(const RegPressureTracker &RPTracker)

Initialize the LiveThru pressure set based on the untied defs found in RPTracker.

void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl< RegisterMaskPair > &LiveInOrOut)

void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)

Setup the RegPressureTracker.

void discoverLiveOut(RegisterMaskPair Pair)

Add Reg to the live out set and increase max pressure.

bool isBottomClosed() const

Does this pressure result have a valid bottom position and live outs.

bool hasUntiedDef(Register VirtReg) const

void discoverLiveIn(RegisterMaskPair Pair)

Add Reg to the live in set and increase max pressure.

void closeTop()

Set the boundary for the top of the region and summarize live ins.

LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const

void getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)

Consider the pressure increase caused by traversing this instruction top-down.

void advance()

Advance across the current instruction.

bool isTopClosed() const

Does this pressure result have a valid top position and live ins.

void bumpUpwardPressure(const MachineInstr *MI)

Record the upward impact of a single instruction on current register pressure.

void bumpDeadDefs(ArrayRef< RegisterMaskPair > DeadDefs)

void getDownwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)

Get the pressure of each PSet after traversing this instruction top-down.

SlotIndex getCurrSlot() const

Get the SlotIndex for the first nondebug instruction including or after the current position.

LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const

void getUpwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)

Get the pressure of each PSet after traversing this instruction bottom-up.

LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const

void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)

void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)

void addLiveRegs(ArrayRef< RegisterMaskPair > Regs)

Force liveness of virtual registers or physical register units.

void getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit) const

This is the fast version of querying register pressure that does not directly depend on current liven...

unsigned getRegPressureSetLimit(unsigned Idx) const

Get the register unit limit for the given pressure set index.

List of registers defined and used by a machine instruction.

void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)

Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...

void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)

Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...

SmallVector< RegisterMaskPair, 8 > DeadDefs

List of virtual registers and register units defined by the instruction but dead.

void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS)

Use liveness information to find dead defs not marked with a dead flag and move them to the DeadDefs ...

SmallVector< RegisterMaskPair, 8 > Uses

List of virtual registers and register units read by the instruction.

SmallVector< RegisterMaskPair, 8 > Defs

List of virtual registers and register units defined by the instruction which are not dead.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

static constexpr bool isVirtualRegister(unsigned Reg)

Return true if the specified register number is in the virtual register namespace.

SlotIndex - An opaque wrapper around machine indexes.

SlotIndex getDeadSlot() const

Returns the dead def kill slot for the current instruction.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

iterator erase(const_iterator CI)

void push_back(const T &Elt)

void clear()

clear - Clears the set.

void setUniverse(unsigned U)

setUniverse - Set the universe size which determines the largest key the set can hold.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual unsigned getNumRegPressureSets() const =0

Get the number of dimensions of register pressure.

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

A Use represents the edge between a Value definition and its users.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It, then continue incrementing it while it points to a debug instruction.

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)

IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It until it points to a non-debug instruction or to End and return the resulting iterator.

Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)

Create Printable object to print virtual registers and physical registers on a raw_ostream.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

void dumpRegSetPressure(ArrayRef< unsigned > SetPressure, const TargetRegisterInfo *TRI)

IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)

Decrement It, then continue decrementing it while it points to a debug instruction.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.

void reset()

Clear the result so it can be used for another round of pressure tracking.

void openBottom(SlotIndex PrevBottom)

If the current bottom is not greater than the previous index, open it.

SlotIndex TopIdx

Record the boundary of the region being tracked.

void openTop(SlotIndex NextTop)

If the current top is not less than or equal to the next index, open it.

static constexpr LaneBitmask getAll()

constexpr bool none() const

constexpr bool any() const

static constexpr LaneBitmask getNone()

This represents a simple continuous liveness interval for a value.

Store the effects of a change in pressure on things that MI scheduler cares about.

PressureChange CriticalMax

PressureChange CurrentMax

RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.

MachineBasicBlock::const_iterator TopPos

Record the boundary of the region being tracked.

MachineBasicBlock::const_iterator BottomPos

void openTop(MachineBasicBlock::const_iterator PrevTop)

If the current top is the previous instruction (before receding), open it.

void reset()

Clear the result so it can be used for another round of pressure tracking.

void openBottom(MachineBasicBlock::const_iterator PrevBottom)

If the current bottom is the previous instr (before advancing), open it.

Virtual register or register unit.

SmallVector< RegisterMaskPair, 8 > LiveInRegs

List of live in virtual registers or physical register units.

void dump(const TargetRegisterInfo *TRI) const

std::vector< unsigned > MaxSetPressure

Map of max reg pressure indexed by pressure set ID, not class ID.

SmallVector< RegisterMaskPair, 8 > LiveOutRegs