LLVM: lib/MCA/HardwareUnits/RetireControlUnit.cpp Source File (original) (raw)

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17#define DEBUG_TYPE "llvm-mca"

18

19namespace llvm {

20namespace mca {

21

23 : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),

24 AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),

25 MaxRetirePerCycle(0) {

27 "RetireControlUnit is not available for in-order processors");

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36 }

37 NumROBEntries = AvailableEntries;

38 assert(NumROBEntries && "Invalid reorder buffer size!");

39 Queue.resize(2 * NumROBEntries);

40}

41

42

45 unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());

46 assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");

47

48 unsigned TokenID = NextAvailableSlotIdx;

49 Queue[NextAvailableSlotIdx] = {IR, Entries, false};

50 NextAvailableSlotIdx += std::max(1U, Entries);

51 NextAvailableSlotIdx %= Queue.size();

53

54 AvailableEntries -= Entries;

55 return TokenID;

56}

57

60#ifndef NDEBUG

62 assert(Inst && "Invalid RUToken in the RCU queue.");

63#endif

64 return Current;

65}

66

67unsigned RetireControlUnit::computeNextSlotIdx() const {

69 unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.NumSlots);

70 return NextSlotIdx % Queue.size();

71}

72

74 return Queue[computeNextSlotIdx()];

75}

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82 CurrentInstructionSlotIdx += std::max(1U, Current.NumSlots);

83 CurrentInstructionSlotIdx %= Queue.size();

84 AvailableEntries += Current.NumSlots;

85 Current = { InstRef(), 0U, false };

86}

87

89 assert(Queue.size() > TokenID);

90 assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");

91 assert(Queue[TokenID].Executed == false && "Instruction already executed!");

92 Queue[TokenID].Executed = true;

93}

94

95#ifndef NDEBUG

97 dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries

98 << ", Available ROB entries=" << AvailableEntries << " }\n";

99}

100#endif

101

102}

103}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Legalize the Machine IR a function s Machine IR

This file simulates the hardware responsible for retiring instructions.

An InstRef contains both a SourceMgr index and Instruction pair.

Instruction * getInstruction()

unsigned getNumMicroOps() const

An instruction propagated through the simulated instruction pipeline.

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Machine model for scheduling, bundling, and heuristics.

bool isOutOfOrder() const

Return true if machine supports out of order execution.

bool hasExtraProcessorInfo() const

const MCExtraProcessorInfo & getExtraProcessorInfo() const

static const unsigned UnhandledTokenID

RetireControlUnit(const MCSchedModel &SM)

Definition RetireControlUnit.cpp:22

void onInstructionExecuted(unsigned TokenID)

Definition RetireControlUnit.cpp:88

void dump() const

Definition RetireControlUnit.cpp:96

const RUToken & getCurrentToken() const

Definition RetireControlUnit.cpp:58

unsigned dispatch(const InstRef &IS)

Definition RetireControlUnit.cpp:43

const RUToken & peekNextToken() const

Definition RetireControlUnit.cpp:73

void consumeCurrentToken()

Definition RetireControlUnit.cpp:77