LLVM: include/llvm/MCA/HardwareUnits/RetireControlUnit.h Source File (original) (raw)
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14#ifndef LLVM_MCA_HARDWAREUNITS_RETIRECONTROLUNIT_H
15#define LLVM_MCA_HARDWAREUNITS_RETIRECONTROLUNIT_H
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20#include
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22namespace llvm {
23namespace mca {
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57private:
58 unsigned NextAvailableSlotIdx;
59 unsigned CurrentInstructionSlotIdx;
60 unsigned NumROBEntries;
61 unsigned AvailableEntries;
62 unsigned MaxRetirePerCycle;
63 std::vector Queue;
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65 unsigned normalizeQuantity(unsigned Quantity) const {
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69 Quantity = std::min(Quantity, NumROBEntries);
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74 return std::max(Quantity, 1U);
75 }
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77 unsigned computeNextSlotIdx() const;
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79public:
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82 bool isEmpty() const { return AvailableEntries == NumROBEntries; }
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85 return AvailableEntries >= normalizeQuantity(Quantity);
86 }
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104#ifndef NDEBUG
105 void dump() const;
106#endif
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110};
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112}
113}
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115#endif
This file defines a base class for describing a simulated hardware unit.
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
An InstRef contains both a SourceMgr index and Instruction pair.
This is an optimization pass for GlobalISel generic memory operations.
Machine model for scheduling, bundling, and heuristics.
Definition RetireControlUnit.h:51
InstRef IR
Definition RetireControlUnit.h:52
unsigned NumSlots
Definition RetireControlUnit.h:53
bool Executed
Definition RetireControlUnit.h:54
bool isAvailable(unsigned Quantity=1) const
Definition RetireControlUnit.h:84
unsigned getMaxRetirePerCycle() const
Definition RetireControlUnit.h:88
static const unsigned UnhandledTokenID
Definition RetireControlUnit.h:109
bool isEmpty() const
Definition RetireControlUnit.h:82
RetireControlUnit(const MCSchedModel &SM)
void onInstructionExecuted(unsigned TokenID)
const RUToken & getCurrentToken() const
unsigned dispatch(const InstRef &IS)
const RUToken & peekNextToken() const
void consumeCurrentToken()