LLVM: include/llvm/MCA/Stages/RetireStage.h Source File (original) (raw)

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16#ifndef LLVM_MCA_STAGES_RETIRESTAGE_H

17#define LLVM_MCA_STAGES_RETIRESTAGE_H

18

24

25namespace llvm {

26namespace mca {

27

28class RetireStage final : public Stage {

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34 RetireStage(const RetireStage &Other) = delete;

35 RetireStage &operator=(const RetireStage &Other) = delete;

36

37public:

39 : RCU(R), PRF(F), LSU(LS) {}

40

46};

47

48}

49}

50

51#endif

A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...

Legalize the Machine IR a function s Machine IR

This file defines a register mapping file class.

This file simulates the hardware responsible for retiring instructions.

This file defines the SmallVector class.

This file defines a stage.

Lightweight error class with error context and mandatory checking.

An InstRef contains both a SourceMgr index and Instruction pair.

Abstract base interface for LS (load/store) units in llvm-mca.

Manages hardware register files, and tracks register definitions for register renaming purposes.

Error cycleEnd() override

Called once at the end of each cycle.

void notifyInstructionRetired(const InstRef &IR) const

Error cycleStart() override

Called once at the start of each cycle.

Error execute(InstRef &IR) override

The primary action that this stage performs on instruction IR.

bool hasWorkToComplete() const override

Returns true if some instructions are still executing this stage.

Definition RetireStage.h:41

RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)

Definition RetireStage.h:38

This is an optimization pass for GlobalISel generic memory operations.

This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...