LLVM: lib/Target/AMDGPU/SIDefines.h File Reference (original) (raw)

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Namespaces
namespace llvm
This is an optimization pass for GlobalISel generic memory operations.
namespace llvm::SIEncodingFamily
namespace llvm::SIInstrFlags
namespace llvm::AMDGPU
namespace llvm::SISrcMods
namespace llvm::SIOutMods
namespace llvm::AMDGPU::VGPRIndexMode
namespace llvm::AMDGPUAsmVariants
namespace llvm::AMDGPU::EncValues
namespace llvm::AMDGPU::HWEncoding
namespace llvm::AMDGPU::CPol
namespace llvm::AMDGPU::SendMsg
namespace llvm::AMDGPU::Hwreg
namespace llvm::AMDGPU::MTBUFFormat
namespace llvm::AMDGPU::UfmtGFX10
namespace llvm::AMDGPU::UfmtGFX11
namespace llvm::AMDGPU::Swizzle
namespace llvm::AMDGPU::SDWA
namespace llvm::AMDGPU::DPP
namespace llvm::AMDGPU::Exp
namespace llvm::AMDGPU::WMMA
namespace llvm::AMDGPU::VOP3PEncoding
namespace llvm::AMDGPU::ImplicitArg
namespace llvm::AMDGPU::MFMAScaleFormats
namespace llvm::AMDGPU::VirtRegFlag
namespace llvm::AMDGPU::Barrier
Macros
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
#define S_00B028_VGPRS(x)
#define S_00B028_SGPRS(x)
#define S_00B028_MEM_ORDERED(x)
#define G_00B028_MEM_ORDERED(x)
#define C_00B028_MEM_ORDERED 0xFDFFFFFF
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
#define S_00B02C_EXTRA_LDS_SIZE(x)
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
#define S_00B128_MEM_ORDERED(x)
#define G_00B128_MEM_ORDERED(x)
#define C_00B128_MEM_ORDERED 0xF7FFFFFF
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
#define S_00B228_WGP_MODE(x)
#define G_00B228_WGP_MODE(x)
#define C_00B228_WGP_MODE 0xF7FFFFFF
#define S_00B228_MEM_ORDERED(x)
#define G_00B228_MEM_ORDERED(x)
#define C_00B228_MEM_ORDERED 0xFDFFFFFF
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
#define S_00B428_WGP_MODE(x)
#define G_00B428_WGP_MODE(x)
#define C_00B428_WGP_MODE 0xFBFFFFFF
#define S_00B428_MEM_ORDERED(x)
#define G_00B428_MEM_ORDERED(x)
#define C_00B428_MEM_ORDERED 0xFEFFFFFF
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
#define S_00B84C_SCRATCH_EN(x)
#define G_00B84C_SCRATCH_EN(x)
#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
#define S_00B84C_USER_SGPR(x)
#define G_00B84C_USER_SGPR(x)
#define C_00B84C_USER_SGPR 0xFFFFFFC1
#define S_00B84C_TRAP_HANDLER(x)
#define G_00B84C_TRAP_HANDLER(x)
#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
#define S_00B84C_TGID_X_EN(x)
#define G_00B84C_TGID_X_EN(x)
#define C_00B84C_TGID_X_EN 0xFFFFFF7F
#define S_00B84C_TGID_Y_EN(x)
#define G_00B84C_TGID_Y_EN(x)
#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
#define S_00B84C_TGID_Z_EN(x)
#define G_00B84C_TGID_Z_EN(x)
#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
#define S_00B84C_TG_SIZE_EN(x)
#define G_00B84C_TG_SIZE_EN(x)
#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
#define S_00B84C_TIDIG_COMP_CNT(x)
#define G_00B84C_TIDIG_COMP_CNT(x)
#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
#define S_00B84C_EXCP_EN_MSB(x)
#define G_00B84C_EXCP_EN_MSB(x)
#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
#define S_00B84C_LDS_SIZE(x)
#define G_00B84C_LDS_SIZE(x)
#define C_00B84C_LDS_SIZE 0xFF007FFF
#define S_00B84C_EXCP_EN(x)
#define G_00B84C_EXCP_EN(x)
#define C_00B84C_EXCP_EN 0x80FFFFFF
#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
#define S_00B848_VGPRS(x)
#define G_00B848_VGPRS(x)
#define C_00B848_VGPRS 0xFFFFFFC0
#define S_00B848_SGPRS(x)
#define G_00B848_SGPRS(x)
#define C_00B848_SGPRS 0xFFFFFC3F
#define S_00B848_PRIORITY(x)
#define G_00B848_PRIORITY(x)
#define C_00B848_PRIORITY 0xFFFFF3FF
#define S_00B848_FLOAT_MODE(x)
#define G_00B848_FLOAT_MODE(x)
#define C_00B848_FLOAT_MODE 0xFFF00FFF
#define S_00B848_PRIV(x)
#define G_00B848_PRIV(x)
#define C_00B848_PRIV 0xFFEFFFFF
#define S_00B848_DX10_CLAMP(x)
#define G_00B848_DX10_CLAMP(x)
#define C_00B848_DX10_CLAMP 0xFFDFFFFF
#define S_00B848_RR_WG_MODE(x)
#define G_00B848_RR_WG_MODE(x)
#define C_00B848_RR_WG_MODE 0xFFDFFFFF
#define S_00B848_DEBUG_MODE(x)
#define G_00B848_DEBUG_MODE(x)
#define C_00B848_DEBUG_MODE 0xFFBFFFFF
#define S_00B848_IEEE_MODE(x)
#define G_00B848_IEEE_MODE(x)
#define C_00B848_IEEE_MODE 0xFF7FFFFF
#define S_00B848_WGP_MODE(x)
#define G_00B848_WGP_MODE(x)
#define C_00B848_WGP_MODE 0xDFFFFFFF
#define S_00B848_MEM_ORDERED(x)
#define G_00B848_MEM_ORDERED(x)
#define C_00B848_MEM_ORDERED 0xBFFFFFFF
#define S_00B848_FWD_PROGRESS(x)
#define G_00B848_FWD_PROGRESS(x)
#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
#define FP_ROUND_ROUND_TO_NEAREST 0
#define FP_ROUND_ROUND_TO_INF 1
#define FP_ROUND_ROUND_TO_NEGINF 2
#define FP_ROUND_ROUND_TO_ZERO 3
#define FP_ROUND_MODE_SP(x)
#define FP_ROUND_MODE_DP(x)
#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
#define FP_DENORM_FLUSH_OUT 1
#define FP_DENORM_FLUSH_IN 2
#define FP_DENORM_FLUSH_NONE 3
#define FP_DENORM_MODE_SP(x)
#define FP_DENORM_MODE_DP(x)
#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
#define S_00B860_WAVESIZE_PreGFX11(x)
#define S_00B860_WAVESIZE_GFX11(x)
#define S_00B860_WAVESIZE_GFX12Plus(x)
#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
#define S_0286E8_WAVESIZE_PreGFX11(x)
#define S_0286E8_WAVESIZE_GFX11(x)
#define S_0286E8_WAVESIZE_GFX12Plus(x)
#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
#define S_028B54_HS_W32_EN(x)
#define S_028B54_GS_W32_EN(x)
#define S_028B54_VS_W32_EN(x)
#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
#define S_0286D8_PS_W32_EN(x)
#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
#define S_00B800_CS_W32_EN(x)
#define R_SPILLED_SGPRS 0x4
#define R_SPILLED_VGPRS 0x8
Enumerations
enum llvm::SIRCFlags : uint8_t { llvm::RegTupleAlignUnitsWidth = 2 , llvm::HasVGPRBit = RegTupleAlignUnitsWidth , llvm::HasAGPRBit, llvm::HasSGPRbit, llvm::HasVGPR = 1 << HasVGPRBit , llvm::HasAGPR = 1 << HasAGPRBit , llvm::HasSGPR = 1 << HasSGPRbit , llvm::RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1 , llvm::RegKindMask = (HasVGPR | HasAGPR HasSGPR) }
enum { llvm::SIEncodingFamily::SI = 0 , llvm::SIEncodingFamily::VI = 1 , llvm::SIEncodingFamily::SDWA = 2 , llvm::SIEncodingFamily::SDWA9 = 3 , llvm::SIEncodingFamily::GFX80 = 4 , llvm::SIEncodingFamily::GFX9 = 5 , llvm::SIEncodingFamily::GFX10 = 6 , llvm::SIEncodingFamily::SDWA10 = 7 , llvm::SIEncodingFamily::GFX90A = 8 , llvm::SIEncodingFamily::GFX940 = 9 , llvm::SIEncodingFamily::GFX11 = 10 , llvm::SIEncodingFamily::GFX12 = 11 , llvm::SIEncodingFamily::GFX1250 = 12 }
enum : uint64_t { llvm::SIInstrFlags::SALU = 1 << 0 , llvm::SIInstrFlags::VALU = 1 << 1 , llvm::SIInstrFlags::SOP1 = 1 << 2 , llvm::SIInstrFlags::SOP2 = 1 << 3 , llvm::SIInstrFlags::SOPC = 1 << 4 , llvm::SIInstrFlags::SOPK = 1 << 5 , llvm::SIInstrFlags::SOPP = 1 << 6 , llvm::SIInstrFlags::VOP1 = 1 << 7 , llvm::SIInstrFlags::VOP2 = 1 << 8 , llvm::SIInstrFlags::VOPC = 1 << 9 , llvm::SIInstrFlags::VOP3 = 1 << 10 , llvm::SIInstrFlags::VOP3P = 1 << 12 , llvm::SIInstrFlags::VINTRP = 1 << 13 , llvm::SIInstrFlags::SDWA = 1 << 14 , llvm::SIInstrFlags::DPP = 1 << 15 , llvm::SIInstrFlags::TRANS = 1 << 16 , llvm::SIInstrFlags::MUBUF = 1 << 17 , llvm::SIInstrFlags::MTBUF = 1 << 18 , llvm::SIInstrFlags::SMRD = 1 << 19 , llvm::SIInstrFlags::MIMG = 1 << 20 , llvm::SIInstrFlags::VIMAGE = 1 << 21 , llvm::SIInstrFlags::VSAMPLE = 1 << 22 , llvm::SIInstrFlags::EXP = 1 << 23 , llvm::SIInstrFlags::FLAT = 1 << 24 , llvm::SIInstrFlags::DS = 1 << 25 , llvm::SIInstrFlags::Spill = 1 << 26 , llvm::SIInstrFlags::LDSDIR = 1 << 28 , llvm::SIInstrFlags::VINTERP = 1 << 29 , llvm::SIInstrFlags::VOPD3 = 1 << 30 , llvm::SIInstrFlags::VM_CNT = UINT64_C(1) << 32 , llvm::SIInstrFlags::EXP_CNT = UINT64_C(1) << 33 , llvm::SIInstrFlags::LGKM_CNT = UINT64_C(1) << 34 , llvm::SIInstrFlags::WQM = UINT64_C(1) << 35 , llvm::SIInstrFlags::DisableWQM = UINT64_C(1) << 36 , llvm::SIInstrFlags::Gather4 = UINT64_C(1) << 37 , llvm::SIInstrFlags::TENSOR_CNT = UINT64_C(1) << 38 , llvm::SIInstrFlags::SCALAR_STORE = UINT64_C(1) << 39 , llvm::SIInstrFlags::FIXED_SIZE = UINT64_C(1) << 40 , llvm::SIInstrFlags::ASYNC_CNT = UINT64_C(1) << 41 , llvm::SIInstrFlags::VOP3_OPSEL = UINT64_C(1) << 42 , llvm::SIInstrFlags::maybeAtomic = UINT64_C(1) << 43 , llvm::SIInstrFlags::renamedInGFX9 = UINT64_C(1) << 44 , llvm::SIInstrFlags::FPClamp = UINT64_C(1) << 45 , llvm::SIInstrFlags::IntClamp = UINT64_C(1) << 46 , llvm::SIInstrFlags::ClampLo = UINT64_C(1) << 47 , llvm::SIInstrFlags::ClampHi = UINT64_C(1) << 48 , llvm::SIInstrFlags::IsPacked = UINT64_C(1) << 49 , llvm::SIInstrFlags::D16Buf = UINT64_C(1) << 50 , llvm::SIInstrFlags::FlatGlobal = UINT64_C(1) << 51 , llvm::SIInstrFlags::FPDPRounding = UINT64_C(1) << 52 , llvm::SIInstrFlags::FPAtomic = UINT64_C(1) << 53 , llvm::SIInstrFlags::IsMAI = UINT64_C(1) << 54 , llvm::SIInstrFlags::IsDOT = UINT64_C(1) << 55 , llvm::SIInstrFlags::FlatScratch = UINT64_C(1) << 56 , llvm::SIInstrFlags::IsAtomicNoRet = UINT64_C(1) << 57 , llvm::SIInstrFlags::IsAtomicRet = UINT64_C(1) << 58 , llvm::SIInstrFlags::IsWMMA = UINT64_C(1) << 59 , llvm::SIInstrFlags::TiedSourceNotRead = UINT64_C(1) << 60 , llvm::SIInstrFlags::IsNeverUniform = UINT64_C(1) << 61 , llvm::SIInstrFlags::GWS = UINT64_C(1) << 62 , llvm::SIInstrFlags::IsSWMMAC = UINT64_C(1) << 63 }
enum llvm::SIInstrFlags::ClassFlags : unsigned { llvm::SIInstrFlags::S_NAN = 1 << 0 , llvm::SIInstrFlags::Q_NAN = 1 << 1 , llvm::SIInstrFlags::N_INFINITY = 1 << 2 , llvm::SIInstrFlags::N_NORMAL = 1 << 3 , llvm::SIInstrFlags::N_SUBNORMAL = 1 << 4 , llvm::SIInstrFlags::N_ZERO = 1 << 5 , llvm::SIInstrFlags::P_ZERO = 1 << 6 , llvm::SIInstrFlags::P_SUBNORMAL = 1 << 7 , llvm::SIInstrFlags::P_NORMAL = 1 << 8 , llvm::SIInstrFlags::P_INFINITY = 1 << 9 }
enum llvm::AMDGPU::OperandType : unsigned { llvm::AMDGPU::OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET , llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_SDWA_VOPC_DST, llvm::AMDGPU::OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32 , llvm::AMDGPU::OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32 , llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16 , llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64 , llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32 , llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO , llvm::AMDGPU::OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32 , llvm::AMDGPU::OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST , llvm::AMDGPU::OPERAND_KIMM_FIRST = OPERAND_KIMM32 , llvm::AMDGPU::OPERAND_KIMM_LAST = OPERAND_KIMM64 }
enum : unsigned { llvm::SISrcMods::NONE = 0 , llvm::SISrcMods::NEG = 1 << 0 , llvm::SISrcMods::ABS = 1 << 1 , llvm::SISrcMods::SEXT = 1 << 4 , llvm::SISrcMods::NEG_HI = ABS , llvm::SISrcMods::OP_SEL_0 = 1 << 2 , llvm::SISrcMods::OP_SEL_1 = 1 << 3 , llvm::SISrcMods::DST_OP_SEL = 1 << 3 }
enum : unsigned { llvm::SIOutMods::NONE = 0 , llvm::SIOutMods::MUL2 = 1 , llvm::SIOutMods::MUL4 = 2 , llvm::SIOutMods::DIV2 = 3 }
enum llvm::AMDGPU::VGPRIndexMode::Id : unsigned { llvm::AMDGPU::VGPRIndexMode::ID_SRC0 = 0 , llvm::AMDGPU::VGPRIndexMode::ID_SRC1, llvm::AMDGPU::VGPRIndexMode::ID_SRC2, llvm::AMDGPU::VGPRIndexMode::ID_DST, llvm::AMDGPU::VGPRIndexMode::ID_MIN = ID_SRC0 , llvm::AMDGPU::VGPRIndexMode::ID_MAX = ID_DST }
enum llvm::AMDGPU::VGPRIndexMode::EncBits : unsigned { llvm::AMDGPU::VGPRIndexMode::OFF = 0 , llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE = 1 << ID_SRC0 , llvm::AMDGPU::VGPRIndexMode::SRC1_ENABLE = 1 << ID_SRC1 , llvm::AMDGPU::VGPRIndexMode::SRC2_ENABLE = 1 << ID_SRC2 , llvm::AMDGPU::VGPRIndexMode::DST_ENABLE = 1 << ID_DST , llvm::AMDGPU::VGPRIndexMode::ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE SRC2_ENABLE DST_ENABLE , llvm::AMDGPU::VGPRIndexMode::UNDEF = 0xFFFF }
enum : unsigned { llvm::AMDGPUAsmVariants::DEFAULT = 0 , llvm::AMDGPUAsmVariants::VOP3 = 1 , llvm::AMDGPUAsmVariants::SDWA = 2 , llvm::AMDGPUAsmVariants::SDWA9 = 3 , llvm::AMDGPUAsmVariants::DPP = 4 , llvm::AMDGPUAsmVariants::VOP3_DPP = 5 }
enum : unsigned { llvm::AMDGPU::EncValues::SGPR_MIN = 0 , llvm::AMDGPU::EncValues::SGPR_MAX_SI = 101 , llvm::AMDGPU::EncValues::SGPR_MAX_GFX10 = 105 , llvm::AMDGPU::EncValues::TTMP_VI_MIN = 112 , llvm::AMDGPU::EncValues::TTMP_VI_MAX = 123 , llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN = 108 , llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX = 123 , llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN = 128 , llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX = 192 , llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX = 208 , llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN = 240 , llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX = 248 , llvm::AMDGPU::EncValues::LITERAL64_CONST = 254 , llvm::AMDGPU::EncValues::LITERAL_CONST = 255 , llvm::AMDGPU::EncValues::VGPR_MIN = 256 , llvm::AMDGPU::EncValues::VGPR_MAX = 511 , llvm::AMDGPU::EncValues::IS_VGPR = 256 }
enum : unsigned { llvm::AMDGPU::HWEncoding::REG_IDX_MASK = 0x3ff , llvm::AMDGPU::HWEncoding::LO256_REG_IDX_MASK = 0xff , llvm::AMDGPU::HWEncoding::IS_VGPR = 1 << 10 , llvm::AMDGPU::HWEncoding::IS_AGPR = 1 << 11 , llvm::AMDGPU::HWEncoding::IS_HI16 = 1 << 12 }
enum llvm::AMDGPU::CPol::CPol { llvm::AMDGPU::CPol::GLC = 1 , llvm::AMDGPU::CPol::SLC = 2 , llvm::AMDGPU::CPol::DLC = 4 , llvm::AMDGPU::CPol::SCC = 16 , llvm::AMDGPU::CPol::SC0 = GLC , llvm::AMDGPU::CPol::SC1 = SCC , llvm::AMDGPU::CPol::NT = SLC , llvm::AMDGPU::CPol::ALL_pregfx12 = GLC | SLC DLC SCC , llvm::AMDGPU::CPol::SWZ_pregfx12 = 8 , llvm::AMDGPU::CPol::TH = 0x7 , llvm::AMDGPU::CPol::TH_RT = 0 , llvm::AMDGPU::CPol::TH_NT = 1 , llvm::AMDGPU::CPol::TH_HT = 2 , llvm::AMDGPU::CPol::TH_LU = 3 , llvm::AMDGPU::CPol::TH_WB = 3 , llvm::AMDGPU::CPol::TH_NT_RT = 4 , llvm::AMDGPU::CPol::TH_RT_NT = 5 , llvm::AMDGPU::CPol::TH_NT_HT = 6 , llvm::AMDGPU::CPol::TH_NT_WB = 7 , llvm::AMDGPU::CPol::TH_BYPASS = 3 , llvm::AMDGPU::CPol::TH_RESERVED = 7 , llvm::AMDGPU::CPol::TH_ATOMIC_RETURN = GLC , llvm::AMDGPU::CPol::TH_ATOMIC_NT = SLC , llvm::AMDGPU::CPol::TH_ATOMIC_CASCADE = 4 , llvm::AMDGPU::CPol::SCOPE_SHIFT = 3 , llvm::AMDGPU::CPol::SCOPE_MASK = 0x3 , llvm::AMDGPU::CPol::SCOPE = SCOPE_MASK << SCOPE_SHIFT , llvm::AMDGPU::CPol::SCOPE_CU = 0 << SCOPE_SHIFT , llvm::AMDGPU::CPol::SCOPE_SE = 1 << SCOPE_SHIFT , llvm::AMDGPU::CPol::SCOPE_DEV = 2 << SCOPE_SHIFT , llvm::AMDGPU::CPol::SCOPE_SYS = 3 << SCOPE_SHIFT , llvm::AMDGPU::CPol::NV = 1 << 5 , llvm::AMDGPU::CPol::SWZ = 1 << 6 , llvm::AMDGPU::CPol::SCAL = 1 << 11 , llvm::AMDGPU::CPol::ALL = TH SCOPE NV , llvm::AMDGPU::CPol::TH_TYPE_LOAD = 1 << 7 , llvm::AMDGPU::CPol::TH_TYPE_STORE = 1 << 8 , llvm::AMDGPU::CPol::TH_TYPE_ATOMIC = 1 << 9 , llvm::AMDGPU::CPol::TH_REAL_BYPASS = 1 << 10 , llvm::AMDGPU::CPol::VOLATILE = 1 << 31 , llvm::AMDGPU::CPol::VIRTUAL_BITS = VOLATILE }
enum llvm::AMDGPU::SendMsg::Id { llvm::AMDGPU::SendMsg::ID_INTERRUPT = 1 , llvm::AMDGPU::SendMsg::ID_GS_PreGFX11 = 2 , llvm::AMDGPU::SendMsg::ID_GS_DONE_PreGFX11 = 3 , llvm::AMDGPU::SendMsg::ID_HS_TESSFACTOR_GFX11Plus = 2 , llvm::AMDGPU::SendMsg::ID_DEALLOC_VGPRS_GFX11Plus = 3 , llvm::AMDGPU::SendMsg::ID_SAVEWAVE = 4 , llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN = 5 , llvm::AMDGPU::SendMsg::ID_HALT_WAVES = 6 , llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE = 7 , llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC = 8 , llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ = 9 , llvm::AMDGPU::SendMsg::ID_GET_DOORBELL = 10 , llvm::AMDGPU::SendMsg::ID_SAVEWAVE_HAS_TDM = 10 , llvm::AMDGPU::SendMsg::ID_GET_DDID = 11 , llvm::AMDGPU::SendMsg::ID_SYSMSG = 15 , llvm::AMDGPU::SendMsg::ID_RTN_GET_DOORBELL = 128 , llvm::AMDGPU::SendMsg::ID_RTN_GET_DDID = 129 , llvm::AMDGPU::SendMsg::ID_RTN_GET_TMA = 130 , llvm::AMDGPU::SendMsg::ID_RTN_GET_REALTIME = 131 , llvm::AMDGPU::SendMsg::ID_RTN_SAVE_WAVE = 132 , llvm::AMDGPU::SendMsg::ID_RTN_GET_TBA = 133 , llvm::AMDGPU::SendMsg::ID_RTN_GET_TBA_TO_PC = 134 , llvm::AMDGPU::SendMsg::ID_RTN_GET_SE_AID_ID = 135 , llvm::AMDGPU::SendMsg::ID_RTN_GET_CLUSTER_BARRIER_STATE = 136 , llvm::AMDGPU::SendMsg::ID_MASK_PreGFX11_ = 0xF , llvm::AMDGPU::SendMsg::ID_MASK_GFX11Plus_ = 0xFF }
enum llvm::AMDGPU::SendMsg::Op { llvm::AMDGPU::SendMsg::OP_SHIFT_ = 4 , llvm::AMDGPU::SendMsg::OP_NONE_ = 0 , llvm::AMDGPU::SendMsg::OP_WIDTH_ = 3 , llvm::AMDGPU::SendMsg::OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_) , llvm::AMDGPU::SendMsg::OP_GS_NOP = 0 , llvm::AMDGPU::SendMsg::OP_GS_CUT = 1 , llvm::AMDGPU::SendMsg::OP_GS_EMIT = 2 , llvm::AMDGPU::SendMsg::OP_GS_EMIT_CUT = 3 , llvm::AMDGPU::SendMsg::OP_GS_FIRST_ = OP_GS_NOP , llvm::AMDGPU::SendMsg::OP_SYS_ECC_ERR_INTERRUPT = 1 , llvm::AMDGPU::SendMsg::OP_SYS_REG_RD = 2 , llvm::AMDGPU::SendMsg::OP_SYS_HOST_TRAP_ACK = 3 , llvm::AMDGPU::SendMsg::OP_SYS_TTRACE_PC = 4 , llvm::AMDGPU::SendMsg::OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT }
enum llvm::AMDGPU::SendMsg::StreamId : unsigned { llvm::AMDGPU::SendMsg::STREAM_ID_NONE_ = 0 , llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_ = 0 , llvm::AMDGPU::SendMsg::STREAM_ID_LAST_ = 4 , llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_ , llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_ = 8 , llvm::AMDGPU::SendMsg::STREAM_ID_WIDTH_ = 2 , llvm::AMDGPU::SendMsg::STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) }
enum llvm::AMDGPU::Hwreg::Id { llvm::AMDGPU::Hwreg::ID_MODE = 1 , llvm::AMDGPU::Hwreg::ID_STATUS = 2 , llvm::AMDGPU::Hwreg::ID_TRAPSTS = 3 , llvm::AMDGPU::Hwreg::ID_HW_ID = 4 , llvm::AMDGPU::Hwreg::ID_GPR_ALLOC = 5 , llvm::AMDGPU::Hwreg::ID_LDS_ALLOC = 6 , llvm::AMDGPU::Hwreg::ID_IB_STS = 7 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_DATA_gfx12 = 10 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12 , llvm::AMDGPU::Hwreg::ID_MEM_BASES = 15 , llvm::AMDGPU::Hwreg::ID_TBA_LO = 16 , llvm::AMDGPU::Hwreg::ID_TBA_HI = 17 , llvm::AMDGPU::Hwreg::ID_TMA_LO = 18 , llvm::AMDGPU::Hwreg::ID_TMA_HI = 19 , llvm::AMDGPU::Hwreg::ID_FLAT_SCR_LO = 20 , llvm::AMDGPU::Hwreg::ID_FLAT_SCR_HI = 21 , llvm::AMDGPU::Hwreg::ID_XNACK_MASK = 22 , llvm::AMDGPU::Hwreg::ID_HW_ID1 = 23 , llvm::AMDGPU::Hwreg::ID_HW_ID2 = 24 , llvm::AMDGPU::Hwreg::ID_POPS_PACKER = 25 , llvm::AMDGPU::Hwreg::ID_SCHED_MODE = 26 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_DATA_gfx11 = 27 , llvm::AMDGPU::Hwreg::ID_IB_STS2 = 28 , llvm::AMDGPU::Hwreg::ID_SHADER_CYCLES = 29 , llvm::AMDGPU::Hwreg::ID_SHADER_CYCLES_HI = 30 , llvm::AMDGPU::Hwreg::ID_DVGPR_ALLOC_LO = 31 , llvm::AMDGPU::Hwreg::ID_DVGPR_ALLOC_HI = 32 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19 , llvm::AMDGPU::Hwreg::ID_STATE_PRIV = 4 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_DATA1 = 15 , llvm::AMDGPU::Hwreg::ID_PERF_SNAPSHOT_DATA2 = 16 , llvm::AMDGPU::Hwreg::ID_EXCP_FLAG_PRIV = 17 , llvm::AMDGPU::Hwreg::ID_EXCP_FLAG_USER = 18 , llvm::AMDGPU::Hwreg::ID_TRAP_CTRL = 19 , llvm::AMDGPU::Hwreg::ID_XCC_ID = 20 , llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_DATA = 21 , llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_DATA1 = 22 , llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_PC_LO = 23 , llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_PC_HI = 24 , llvm::AMDGPU::Hwreg::ID_XNACK_STATE_PRIV = 33 , llvm::AMDGPU::Hwreg::ID_XNACK_MASK_gfx1250 = 34 }
enum llvm::AMDGPU::Hwreg::Offset : unsigned { llvm::AMDGPU::Hwreg::OFFSET_MEM_VIOL = 8 , llvm::AMDGPU::Hwreg::OFFSET_ME_ID = 8 }
enum llvm::AMDGPU::Hwreg::ModeRegisterMasks : uint32_t { llvm::AMDGPU::Hwreg::FP_ROUND_MASK = 0xf << 0 , llvm::AMDGPU::Hwreg::FP_DENORM_MASK = 0xf << 4 , llvm::AMDGPU::Hwreg::DX10_CLAMP_MASK = 1 << 8 , llvm::AMDGPU::Hwreg::IEEE_MODE_MASK = 1 << 9 , llvm::AMDGPU::Hwreg::LOD_CLAMP_MASK = 1 << 10 , llvm::AMDGPU::Hwreg::DEBUG_MASK = 1 << 11 , llvm::AMDGPU::Hwreg::EXCP_EN_INVALID_MASK = 1 << 12 , llvm::AMDGPU::Hwreg::EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13 , llvm::AMDGPU::Hwreg::EXCP_EN_FLOAT_DIV0_MASK = 1 << 14 , llvm::AMDGPU::Hwreg::EXCP_EN_OVERFLOW_MASK = 1 << 15 , llvm::AMDGPU::Hwreg::EXCP_EN_UNDERFLOW_MASK = 1 << 16 , llvm::AMDGPU::Hwreg::EXCP_EN_INEXACT_MASK = 1 << 17 , llvm::AMDGPU::Hwreg::EXCP_EN_INT_DIV0_MASK = 1 << 18 , llvm::AMDGPU::Hwreg::GPR_IDX_EN_MASK = 1 << 27 , llvm::AMDGPU::Hwreg::VSKIP_MASK = 1 << 28 , llvm::AMDGPU::Hwreg::CSP_MASK = 0x7u << 29 , llvm::AMDGPU::Hwreg::DST_VGPR_MSB = 1 << 12 , llvm::AMDGPU::Hwreg::SRC0_VGPR_MSB = 1 << 13 , llvm::AMDGPU::Hwreg::SRC1_VGPR_MSB = 1 << 14 , llvm::AMDGPU::Hwreg::SRC2_VGPR_MSB = 1 << 15 , llvm::AMDGPU::Hwreg::VGPR_MSB_MASK = 0xf << 12 , llvm::AMDGPU::Hwreg::REPLAY_MODE = 1 << 25 , llvm::AMDGPU::Hwreg::FLAT_SCRATCH_IS_NV = 1 << 26 }
enum llvm::AMDGPU::MTBUFFormat::DataFormat : int64_t { llvm::AMDGPU::MTBUFFormat::DFMT_INVALID = 0 , llvm::AMDGPU::MTBUFFormat::DFMT_8, llvm::AMDGPU::MTBUFFormat::DFMT_16, llvm::AMDGPU::MTBUFFormat::DFMT_8_8, llvm::AMDGPU::MTBUFFormat::DFMT_32, llvm::AMDGPU::MTBUFFormat::DFMT_16_16, llvm::AMDGPU::MTBUFFormat::DFMT_10_11_11, llvm::AMDGPU::MTBUFFormat::DFMT_11_11_10, llvm::AMDGPU::MTBUFFormat::DFMT_10_10_10_2, llvm::AMDGPU::MTBUFFormat::DFMT_2_10_10_10, llvm::AMDGPU::MTBUFFormat::DFMT_8_8_8_8, llvm::AMDGPU::MTBUFFormat::DFMT_32_32, llvm::AMDGPU::MTBUFFormat::DFMT_16_16_16_16, llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32, llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32_32, llvm::AMDGPU::MTBUFFormat::DFMT_RESERVED_15, llvm::AMDGPU::MTBUFFormat::DFMT_MIN = DFMT_INVALID , llvm::AMDGPU::MTBUFFormat::DFMT_MAX = DFMT_RESERVED_15 , llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF = -1 , llvm::AMDGPU::MTBUFFormat::DFMT_DEFAULT = DFMT_8 , llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT = 0 , llvm::AMDGPU::MTBUFFormat::DFMT_MASK = 0xF }
enum llvm::AMDGPU::MTBUFFormat::NumFormat : int64_t { llvm::AMDGPU::MTBUFFormat::NFMT_UNORM = 0 , llvm::AMDGPU::MTBUFFormat::NFMT_SNORM, llvm::AMDGPU::MTBUFFormat::NFMT_USCALED, llvm::AMDGPU::MTBUFFormat::NFMT_SSCALED, llvm::AMDGPU::MTBUFFormat::NFMT_UINT, llvm::AMDGPU::MTBUFFormat::NFMT_SINT, llvm::AMDGPU::MTBUFFormat::NFMT_RESERVED_6, llvm::AMDGPU::MTBUFFormat::NFMT_SNORM_OGL = NFMT_RESERVED_6 , llvm::AMDGPU::MTBUFFormat::NFMT_FLOAT, llvm::AMDGPU::MTBUFFormat::NFMT_MIN = NFMT_UNORM , llvm::AMDGPU::MTBUFFormat::NFMT_MAX = NFMT_FLOAT , llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF = -1 , llvm::AMDGPU::MTBUFFormat::NFMT_DEFAULT = NFMT_UNORM , llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT = 4 , llvm::AMDGPU::MTBUFFormat::NFMT_MASK = 7 }
enum llvm::AMDGPU::MTBUFFormat::MergedFormat : int64_t { llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_UNDEF = -1 , llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT, llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT) , llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX = DFMT_NFMT_MASK }
enum llvm::AMDGPU::MTBUFFormat::UnifiedFormatCommon : int64_t { llvm::AMDGPU::MTBUFFormat::UFMT_MAX = 127 , llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF = -1 , llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT = 1 }
enum llvm::AMDGPU::UfmtGFX10::UnifiedFormat : int64_t { llvm::AMDGPU::UfmtGFX10::UFMT_INVALID = 0 , llvm::AMDGPU::UfmtGFX10::UFMT_8_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_8_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_8_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_8_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_8_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_8_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_16_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_16_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_16_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_16_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_UNORM, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_SNORM, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_USCALED, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_SSCALED, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_32_UINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_32_SINT, llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_32_FLOAT, llvm::AMDGPU::UfmtGFX10::UFMT_FIRST = UFMT_INVALID , llvm::AMDGPU::UfmtGFX10::UFMT_LAST = UFMT_32_32_32_32_FLOAT }
enum llvm::AMDGPU::UfmtGFX11::UnifiedFormat : int64_t { llvm::AMDGPU::UfmtGFX11::UFMT_INVALID = 0 , llvm::AMDGPU::UfmtGFX11::UFMT_8_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_8_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_8_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_8_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_8_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_8_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_16_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_16_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_16_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_16_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_10_11_11_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_11_11_10_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_UNORM, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_SNORM, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_USCALED, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_SSCALED, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_32_UINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_32_SINT, llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_FIRST = UFMT_INVALID , llvm::AMDGPU::UfmtGFX11::UFMT_LAST = UFMT_32_32_32_32_FLOAT }
enum llvm::AMDGPU::Swizzle::Id : unsigned { llvm::AMDGPU::Swizzle::ID_QUAD_PERM = 0 , llvm::AMDGPU::Swizzle::ID_BITMASK_PERM, llvm::AMDGPU::Swizzle::ID_SWAP, llvm::AMDGPU::Swizzle::ID_REVERSE, llvm::AMDGPU::Swizzle::ID_BROADCAST, llvm::AMDGPU::Swizzle::ID_FFT, llvm::AMDGPU::Swizzle::ID_ROTATE }
enum llvm::AMDGPU::Swizzle::EncBits : unsigned { llvm::AMDGPU::Swizzle::QUAD_PERM_ENC = 0x8000 , llvm::AMDGPU::Swizzle::QUAD_PERM_ENC_MASK = 0xFF00 , llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC = 0x0000 , llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC_MASK = 0x8000 , llvm::AMDGPU::Swizzle::FFT_MODE_ENC = 0xE000 , llvm::AMDGPU::Swizzle::ROTATE_MODE_ENC = 0xC000 , llvm::AMDGPU::Swizzle::FFT_ROTATE_MODE_MASK = 0xF000 , llvm::AMDGPU::Swizzle::ROTATE_MODE_LO = 0xC000 , llvm::AMDGPU::Swizzle::FFT_MODE_LO = 0xE000 , llvm::AMDGPU::Swizzle::LANE_MASK = 0x3 , llvm::AMDGPU::Swizzle::LANE_MAX = LANE_MASK , llvm::AMDGPU::Swizzle::LANE_SHIFT = 2 , llvm::AMDGPU::Swizzle::LANE_NUM = 4 , llvm::AMDGPU::Swizzle::BITMASK_MASK = 0x1F , llvm::AMDGPU::Swizzle::BITMASK_MAX = BITMASK_MASK , llvm::AMDGPU::Swizzle::BITMASK_WIDTH = 5 , llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT = 0 , llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT = 5 , llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT = 10 , llvm::AMDGPU::Swizzle::FFT_SWIZZLE_MASK = 0x1F , llvm::AMDGPU::Swizzle::FFT_SWIZZLE_MAX = 0x1F , llvm::AMDGPU::Swizzle::ROTATE_MAX_SIZE = 0x1F , llvm::AMDGPU::Swizzle::ROTATE_DIR_SHIFT = 10 , llvm::AMDGPU::Swizzle::ROTATE_DIR_MASK = 0x1 , llvm::AMDGPU::Swizzle::ROTATE_SIZE_SHIFT = 5 , llvm::AMDGPU::Swizzle::ROTATE_SIZE_MASK = ROTATE_MAX_SIZE }
enum llvm::AMDGPU::SDWA::SdwaSel : unsigned { llvm::AMDGPU::SDWA::BYTE_0 = 0 , llvm::AMDGPU::SDWA::BYTE_1 = 1 , llvm::AMDGPU::SDWA::BYTE_2 = 2 , llvm::AMDGPU::SDWA::BYTE_3 = 3 , llvm::AMDGPU::SDWA::WORD_0 = 4 , llvm::AMDGPU::SDWA::WORD_1 = 5 , llvm::AMDGPU::SDWA::DWORD = 6 }
enum llvm::AMDGPU::SDWA::DstUnused : unsigned { llvm::AMDGPU::SDWA::UNUSED_PAD = 0 , llvm::AMDGPU::SDWA::UNUSED_SEXT = 1 , llvm::AMDGPU::SDWA::UNUSED_PRESERVE = 2 }
enum llvm::AMDGPU::SDWA::SDWA9EncValues : unsigned { llvm::AMDGPU::SDWA::SRC_SGPR_MASK = 0x100 , llvm::AMDGPU::SDWA::SRC_VGPR_MASK = 0xFF , llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK = 0x80 , llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK = 0x7F , llvm::AMDGPU::SDWA::SRC_VGPR_MIN = 0 , llvm::AMDGPU::SDWA::SRC_VGPR_MAX = 255 , llvm::AMDGPU::SDWA::SRC_SGPR_MIN = 256 , llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI = 357 , llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10 = 361 , llvm::AMDGPU::SDWA::SRC_TTMP_MIN = 364 , llvm::AMDGPU::SDWA::SRC_TTMP_MAX = 379 }
enum llvm::AMDGPU::DPP::DppCtrl : unsigned { llvm::AMDGPU::DPP::QUAD_PERM_FIRST = 0 , llvm::AMDGPU::DPP::QUAD_PERM_ID = 0xE4 , llvm::AMDGPU::DPP::QUAD_PERM_LAST = 0xFF , llvm::AMDGPU::DPP::DPP_UNUSED1 = 0x100 , llvm::AMDGPU::DPP::ROW_SHL0 = 0x100 , llvm::AMDGPU::DPP::ROW_SHL_FIRST = 0x101 , llvm::AMDGPU::DPP::ROW_SHL_LAST = 0x10F , llvm::AMDGPU::DPP::DPP_UNUSED2 = 0x110 , llvm::AMDGPU::DPP::ROW_SHR0 = 0x110 , llvm::AMDGPU::DPP::ROW_SHR_FIRST = 0x111 , llvm::AMDGPU::DPP::ROW_SHR_LAST = 0x11F , llvm::AMDGPU::DPP::DPP_UNUSED3 = 0x120 , llvm::AMDGPU::DPP::ROW_ROR0 = 0x120 , llvm::AMDGPU::DPP::ROW_ROR_FIRST = 0x121 , llvm::AMDGPU::DPP::ROW_ROR_LAST = 0x12F , llvm::AMDGPU::DPP::WAVE_SHL1 = 0x130 , llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST = 0x131 , llvm::AMDGPU::DPP::DPP_UNUSED4_LAST = 0x133 , llvm::AMDGPU::DPP::WAVE_ROL1 = 0x134 , llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST = 0x135 , llvm::AMDGPU::DPP::DPP_UNUSED5_LAST = 0x137 , llvm::AMDGPU::DPP::WAVE_SHR1 = 0x138 , llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST = 0x139 , llvm::AMDGPU::DPP::DPP_UNUSED6_LAST = 0x13B , llvm::AMDGPU::DPP::WAVE_ROR1 = 0x13C , llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST = 0x13D , llvm::AMDGPU::DPP::DPP_UNUSED7_LAST = 0x13F , llvm::AMDGPU::DPP::ROW_MIRROR = 0x140 , llvm::AMDGPU::DPP::ROW_HALF_MIRROR = 0x141 , llvm::AMDGPU::DPP::BCAST15 = 0x142 , llvm::AMDGPU::DPP::BCAST31 = 0x143 , llvm::AMDGPU::DPP::DPP_UNUSED8_FIRST = 0x144 , llvm::AMDGPU::DPP::DPP_UNUSED8_LAST = 0x14F , llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST = 0x150 , llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST = 0x15F , llvm::AMDGPU::DPP::ROW_SHARE0 = 0x150 , llvm::AMDGPU::DPP::ROW_SHARE_FIRST = 0x150 , llvm::AMDGPU::DPP::ROW_SHARE_LAST = 0x15F , llvm::AMDGPU::DPP::ROW_XMASK0 = 0x160 , llvm::AMDGPU::DPP::ROW_XMASK_FIRST = 0x160 , llvm::AMDGPU::DPP::ROW_XMASK_LAST = 0x16F , llvm::AMDGPU::DPP::DPP_LAST = ROW_XMASK_LAST }
enum llvm::AMDGPU::DPP::DppFiMode { llvm::AMDGPU::DPP::DPP_FI_0 = 0 , llvm::AMDGPU::DPP::DPP_FI_1 = 1 , llvm::AMDGPU::DPP::DPP8_FI_0 = 0xE9 , llvm::AMDGPU::DPP::DPP8_FI_1 = 0xEA }
enum llvm::AMDGPU::Exp::Target : unsigned { llvm::AMDGPU::Exp::ET_MRT0 = 0 , llvm::AMDGPU::Exp::ET_MRT7 = 7 , llvm::AMDGPU::Exp::ET_MRTZ = 8 , llvm::AMDGPU::Exp::ET_NULL = 9 , llvm::AMDGPU::Exp::ET_POS0 = 12 , llvm::AMDGPU::Exp::ET_POS3 = 15 , llvm::AMDGPU::Exp::ET_POS4 = 16 , llvm::AMDGPU::Exp::ET_POS_LAST = ET_POS4 , llvm::AMDGPU::Exp::ET_PRIM = 20 , llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0 = 21 , llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1 = 22 , llvm::AMDGPU::Exp::ET_PARAM0 = 32 , llvm::AMDGPU::Exp::ET_PARAM31 = 63 , llvm::AMDGPU::Exp::ET_NULL_MAX_IDX = 0 , llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX = 0 , llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX = 0 , llvm::AMDGPU::Exp::ET_MRT_MAX_IDX = 7 , llvm::AMDGPU::Exp::ET_POS_MAX_IDX = 4 , llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND_MAX_IDX = 1 , llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX = 31 , llvm::AMDGPU::Exp::ET_INVALID = 255 }
enum llvm::AMDGPU::WMMA::MatrixFMT : unsigned { llvm::AMDGPU::WMMA::MATRIX_FMT_FP8 = 0 , llvm::AMDGPU::WMMA::MATRIX_FMT_BF8 = 1 , llvm::AMDGPU::WMMA::MATRIX_FMT_FP6 = 2 , llvm::AMDGPU::WMMA::MATRIX_FMT_BF6 = 3 , llvm::AMDGPU::WMMA::MATRIX_FMT_FP4 = 4 }
enum llvm::AMDGPU::WMMA::MatrixScale : unsigned { llvm::AMDGPU::WMMA::MATRIX_SCALE_ROW0 = 0 , llvm::AMDGPU::WMMA::MATRIX_SCALE_ROW1 = 1 }
enum llvm::AMDGPU::WMMA::MatrixScaleFmt : unsigned { llvm::AMDGPU::WMMA::MATRIX_SCALE_FMT_E8 = 0 , llvm::AMDGPU::WMMA::MATRIX_SCALE_FMT_E5M3 = 1 , llvm::AMDGPU::WMMA::MATRIX_SCALE_FMT_E4M3 = 2 }
enum llvm::AMDGPU::VOP3PEncoding::OpSel : uint64_t { llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_0 = UINT64_C(1) << 59 , llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_1 = UINT64_C(1) << 60 , llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_2 = UINT64_C(1) << 14 }
enum llvm::AMDGPU::ImplicitArg::Offset_COV5 : unsigned { llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET = 80 , llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET = 88 , llvm::AMDGPU::ImplicitArg::HEAP_PTR_OFFSET = 96 , llvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET = 104 , llvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET = 112 , llvm::AMDGPU::ImplicitArg::PRIVATE_BASE_OFFSET = 192 , llvm::AMDGPU::ImplicitArg::SHARED_BASE_OFFSET = 196 , llvm::AMDGPU::ImplicitArg::QUEUE_PTR_OFFSET = 200 }
enum llvm::AMDGPU::MFMAScaleFormats::MFMAScaleFormats { llvm::AMDGPU::MFMAScaleFormats::FP8_E4M3 = 0 , llvm::AMDGPU::MFMAScaleFormats::FP8_E5M2 = 1 , llvm::AMDGPU::MFMAScaleFormats::FP6_E2M3 = 2 , llvm::AMDGPU::MFMAScaleFormats::FP6_E3M2 = 3 , llvm::AMDGPU::MFMAScaleFormats::FP4_E2M1 = 4 }
enum llvm::AMDGPU::VirtRegFlag::Register_Flag : uint8_t { llvm::AMDGPU::VirtRegFlag::WWM_REG = 1 << 0 }
enum llvm::AMDGPU::Barrier::Type { llvm::AMDGPU::Barrier::CLUSTER_TRAP = -4 , llvm::AMDGPU::Barrier::CLUSTER = -3 , llvm::AMDGPU::Barrier::TRAP = -2 , llvm::AMDGPU::Barrier::WORKGROUP = -1 , llvm::AMDGPU::Barrier::NAMED_BARRIER_FIRST = 1 , llvm::AMDGPU::Barrier::NAMED_BARRIER_LAST = 16 }
enum { llvm::AMDGPU::Barrier::BARRIER_SCOPE_WORKGROUP = 0 }

◆ C_00B028_MEM_ORDERED

#define C_00B028_MEM_ORDERED 0xFDFFFFFF

◆ C_00B128_MEM_ORDERED

#define C_00B128_MEM_ORDERED 0xF7FFFFFF

◆ C_00B228_MEM_ORDERED

#define C_00B228_MEM_ORDERED 0xFDFFFFFF

◆ C_00B228_WGP_MODE

#define C_00B228_WGP_MODE 0xF7FFFFFF

◆ C_00B428_MEM_ORDERED

#define C_00B428_MEM_ORDERED 0xFEFFFFFF

◆ C_00B428_WGP_MODE

#define C_00B428_WGP_MODE 0xFBFFFFFF

◆ C_00B848_DEBUG_MODE

#define C_00B848_DEBUG_MODE 0xFFBFFFFF

◆ C_00B848_DX10_CLAMP

#define C_00B848_DX10_CLAMP 0xFFDFFFFF

◆ C_00B848_FLOAT_MODE

#define C_00B848_FLOAT_MODE 0xFFF00FFF

◆ C_00B848_FWD_PROGRESS

#define C_00B848_FWD_PROGRESS 0x7FFFFFFF

◆ C_00B848_IEEE_MODE

#define C_00B848_IEEE_MODE 0xFF7FFFFF

◆ C_00B848_MEM_ORDERED

#define C_00B848_MEM_ORDERED 0xBFFFFFFF

◆ C_00B848_PRIORITY

#define C_00B848_PRIORITY 0xFFFFF3FF

◆ C_00B848_PRIV

#define C_00B848_PRIV 0xFFEFFFFF

◆ C_00B848_RR_WG_MODE

#define C_00B848_RR_WG_MODE 0xFFDFFFFF

◆ C_00B848_SGPRS

#define C_00B848_SGPRS 0xFFFFFC3F

◆ C_00B848_VGPRS

#define C_00B848_VGPRS 0xFFFFFFC0

◆ C_00B848_WGP_MODE

#define C_00B848_WGP_MODE 0xDFFFFFFF

◆ C_00B84C_EXCP_EN

#define C_00B84C_EXCP_EN 0x80FFFFFF

◆ C_00B84C_EXCP_EN_MSB

#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF

◆ C_00B84C_LDS_SIZE

#define C_00B84C_LDS_SIZE 0xFF007FFF

◆ C_00B84C_SCRATCH_EN

#define C_00B84C_SCRATCH_EN 0xFFFFFFFE

◆ C_00B84C_TG_SIZE_EN

#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF

◆ C_00B84C_TGID_X_EN

#define C_00B84C_TGID_X_EN 0xFFFFFF7F

◆ C_00B84C_TGID_Y_EN

#define C_00B84C_TGID_Y_EN 0xFFFFFEFF

◆ C_00B84C_TGID_Z_EN

#define C_00B84C_TGID_Z_EN 0xFFFFFDFF

◆ C_00B84C_TIDIG_COMP_CNT

#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF

◆ C_00B84C_TRAP_HANDLER

#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF

◆ C_00B84C_USER_SGPR

#define C_00B84C_USER_SGPR 0xFFFFFFC1

◆ FP_DENORM_FLUSH_IN

#define FP_DENORM_FLUSH_IN 2

◆ FP_DENORM_FLUSH_IN_FLUSH_OUT

#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0

◆ FP_DENORM_FLUSH_NONE

#define FP_DENORM_FLUSH_NONE 3

◆ FP_DENORM_FLUSH_OUT

#define FP_DENORM_FLUSH_OUT 1

◆ FP_DENORM_MODE_DP

#define FP_DENORM_MODE_DP ( x )

◆ FP_DENORM_MODE_SP

#define FP_DENORM_MODE_SP ( x )

◆ FP_ROUND_MODE_DP

#define FP_ROUND_MODE_DP ( x )

◆ FP_ROUND_MODE_SP

#define FP_ROUND_MODE_SP ( x )

◆ FP_ROUND_ROUND_TO_INF

#define FP_ROUND_ROUND_TO_INF 1

◆ FP_ROUND_ROUND_TO_NEAREST

#define FP_ROUND_ROUND_TO_NEAREST 0

◆ FP_ROUND_ROUND_TO_NEGINF

#define FP_ROUND_ROUND_TO_NEGINF 2

◆ FP_ROUND_ROUND_TO_ZERO

#define FP_ROUND_ROUND_TO_ZERO 3

◆ G_00B028_MEM_ORDERED

#define G_00B028_MEM_ORDERED ( x )

◆ G_00B128_MEM_ORDERED

#define G_00B128_MEM_ORDERED ( x )

◆ G_00B228_MEM_ORDERED

#define G_00B228_MEM_ORDERED ( x )

◆ G_00B228_WGP_MODE

#define G_00B228_WGP_MODE ( x )

◆ G_00B428_MEM_ORDERED

#define G_00B428_MEM_ORDERED ( x )

◆ G_00B428_WGP_MODE

#define G_00B428_WGP_MODE ( x )

◆ G_00B848_DEBUG_MODE

#define G_00B848_DEBUG_MODE ( x )

◆ G_00B848_DX10_CLAMP

#define G_00B848_DX10_CLAMP ( x )

◆ G_00B848_FLOAT_MODE

#define G_00B848_FLOAT_MODE ( x )

◆ G_00B848_FWD_PROGRESS

#define G_00B848_FWD_PROGRESS ( x )

◆ G_00B848_IEEE_MODE

#define G_00B848_IEEE_MODE ( x )

◆ G_00B848_MEM_ORDERED

#define G_00B848_MEM_ORDERED ( x )

◆ G_00B848_PRIORITY

#define G_00B848_PRIORITY ( x )

◆ G_00B848_PRIV

#define G_00B848_PRIV ( x )

◆ G_00B848_RR_WG_MODE

#define G_00B848_RR_WG_MODE ( x )

◆ G_00B848_SGPRS

#define G_00B848_SGPRS ( x )

◆ G_00B848_VGPRS

#define G_00B848_VGPRS ( x )

◆ G_00B848_WGP_MODE

#define G_00B848_WGP_MODE ( x )

◆ G_00B84C_EXCP_EN

#define G_00B84C_EXCP_EN ( x )

◆ G_00B84C_EXCP_EN_MSB

#define G_00B84C_EXCP_EN_MSB ( x )

◆ G_00B84C_LDS_SIZE

#define G_00B84C_LDS_SIZE ( x )

◆ G_00B84C_SCRATCH_EN

#define G_00B84C_SCRATCH_EN ( x )

◆ G_00B84C_TG_SIZE_EN

#define G_00B84C_TG_SIZE_EN ( x )

◆ G_00B84C_TGID_X_EN

#define G_00B84C_TGID_X_EN ( x )

◆ G_00B84C_TGID_Y_EN

#define G_00B84C_TGID_Y_EN ( x )

◆ G_00B84C_TGID_Z_EN

#define G_00B84C_TGID_Z_EN ( x )

◆ G_00B84C_TIDIG_COMP_CNT

#define G_00B84C_TIDIG_COMP_CNT ( x )

◆ G_00B84C_TRAP_HANDLER

#define G_00B84C_TRAP_HANDLER ( x )

◆ G_00B84C_USER_SGPR

#define G_00B84C_USER_SGPR ( x )

◆ R_00B028_SPI_SHADER_PGM_RSRC1_PS

#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028

◆ R_00B02C_SPI_SHADER_PGM_RSRC2_PS

#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C

◆ R_00B128_SPI_SHADER_PGM_RSRC1_VS

#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128

◆ R_00B228_SPI_SHADER_PGM_RSRC1_GS

#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228

◆ R_00B328_SPI_SHADER_PGM_RSRC1_ES

#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328

◆ R_00B428_SPI_SHADER_PGM_RSRC1_HS

#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428

◆ R_00B528_SPI_SHADER_PGM_RSRC1_LS

#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528

◆ R_00B800_COMPUTE_DISPATCH_INITIATOR

#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800

◆ R_00B848_COMPUTE_PGM_RSRC1

#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848

◆ R_00B84C_COMPUTE_PGM_RSRC2

#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C

◆ R_00B860_COMPUTE_TMPRING_SIZE

#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860

◆ R_0286CC_SPI_PS_INPUT_ENA

#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC

◆ R_0286D0_SPI_PS_INPUT_ADDR

#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0

◆ R_0286D8_SPI_PS_IN_CONTROL

#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8

◆ R_0286E8_SPI_TMPRING_SIZE

#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8

◆ R_028B54_VGT_SHADER_STAGES_EN

#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54

◆ R_SPILLED_SGPRS

#define R_SPILLED_SGPRS 0x4

◆ R_SPILLED_VGPRS

#define R_SPILLED_VGPRS 0x8

◆ S_00B028_MEM_ORDERED

#define S_00B028_MEM_ORDERED ( x )

◆ S_00B028_SGPRS

#define S_00B028_SGPRS ( x )

◆ S_00B028_VGPRS

#define S_00B028_VGPRS ( x )

◆ S_00B02C_EXTRA_LDS_SIZE

#define S_00B02C_EXTRA_LDS_SIZE ( x )

◆ S_00B128_MEM_ORDERED

#define S_00B128_MEM_ORDERED ( x )

◆ S_00B228_MEM_ORDERED

#define S_00B228_MEM_ORDERED ( x )

◆ S_00B228_WGP_MODE

#define S_00B228_WGP_MODE ( x )

◆ S_00B428_MEM_ORDERED

#define S_00B428_MEM_ORDERED ( x )

◆ S_00B428_WGP_MODE

#define S_00B428_WGP_MODE ( x )

◆ S_00B800_CS_W32_EN

#define S_00B800_CS_W32_EN ( x )

◆ S_00B848_DEBUG_MODE

#define S_00B848_DEBUG_MODE ( x )

◆ S_00B848_DX10_CLAMP

#define S_00B848_DX10_CLAMP ( x )

◆ S_00B848_FLOAT_MODE

#define S_00B848_FLOAT_MODE ( x )

◆ S_00B848_FWD_PROGRESS

#define S_00B848_FWD_PROGRESS ( x )

◆ S_00B848_IEEE_MODE

#define S_00B848_IEEE_MODE ( x )

◆ S_00B848_MEM_ORDERED

#define S_00B848_MEM_ORDERED ( x )

◆ S_00B848_PRIORITY

#define S_00B848_PRIORITY ( x )

◆ S_00B848_PRIV

#define S_00B848_PRIV ( x )

◆ S_00B848_RR_WG_MODE

#define S_00B848_RR_WG_MODE ( x )

◆ S_00B848_SGPRS

#define S_00B848_SGPRS ( x )

◆ S_00B848_VGPRS

#define S_00B848_VGPRS ( x )

◆ S_00B848_WGP_MODE

#define S_00B848_WGP_MODE ( x )

◆ S_00B84C_EXCP_EN

#define S_00B84C_EXCP_EN ( x )

◆ S_00B84C_EXCP_EN_MSB

#define S_00B84C_EXCP_EN_MSB ( x )

◆ S_00B84C_LDS_SIZE

#define S_00B84C_LDS_SIZE ( x )

◆ S_00B84C_SCRATCH_EN

#define S_00B84C_SCRATCH_EN ( x )

◆ S_00B84C_TG_SIZE_EN

#define S_00B84C_TG_SIZE_EN ( x )

◆ S_00B84C_TGID_X_EN

#define S_00B84C_TGID_X_EN ( x )

◆ S_00B84C_TGID_Y_EN

#define S_00B84C_TGID_Y_EN ( x )

◆ S_00B84C_TGID_Z_EN

#define S_00B84C_TGID_Z_EN ( x )

◆ S_00B84C_TIDIG_COMP_CNT

#define S_00B84C_TIDIG_COMP_CNT ( x )

◆ S_00B84C_TRAP_HANDLER

#define S_00B84C_TRAP_HANDLER ( x )

◆ S_00B84C_USER_SGPR

#define S_00B84C_USER_SGPR ( x )

◆ S_00B860_WAVESIZE_GFX11

#define S_00B860_WAVESIZE_GFX11 ( x )

◆ S_00B860_WAVESIZE_GFX12Plus

#define S_00B860_WAVESIZE_GFX12Plus ( x )

◆ S_00B860_WAVESIZE_PreGFX11

#define S_00B860_WAVESIZE_PreGFX11 ( x )

◆ S_0286D8_PS_W32_EN

#define S_0286D8_PS_W32_EN ( x )

◆ S_0286E8_WAVESIZE_GFX11

#define S_0286E8_WAVESIZE_GFX11 ( x )

◆ S_0286E8_WAVESIZE_GFX12Plus

#define S_0286E8_WAVESIZE_GFX12Plus ( x )

◆ S_0286E8_WAVESIZE_PreGFX11

#define S_0286E8_WAVESIZE_PreGFX11 ( x )

◆ S_028B54_GS_W32_EN

#define S_028B54_GS_W32_EN ( x )

◆ S_028B54_HS_W32_EN

#define S_028B54_HS_W32_EN ( x )

◆ S_028B54_VS_W32_EN

#define S_028B54_VS_W32_EN ( x )