LLVM: lib/Target/AMDGPU/SIFixSGPRCopies.cpp File Reference (original) (raw)

Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this: More...

Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this:

Register Class is the union of and

BB0: %0 = SCALAR_INST %1 = COPY %0 ... BRANCH cond BB1, BB2 BB1: %2 = VECTOR_INST %3 = COPY %2 BB2: %4 = PHI %1 , <bb.0>, %3 , <bb.1> %5 = VECTOR_INST %4

The coalescer will begin at BB0 and eliminate its copy, then the resulting code will look like this:

BB0: %0 = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: %2 = VECTOR_INST %3 = COPY %2 BB2: %4 = PHI %0 , <bb.0>, %3 , <bb.1> %5 = VECTOR_INST %4

Now that the result of the PHI instruction is an SGPR, the register allocator is now forced to constrain the register class of %3 to so we end up with final code like this:

BB0: %0 = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: %2 = VECTOR_INST %3 = COPY %2 BB2: %4 = PHI %0 , <bb.0>, %3 , <bb.1> %5 = VECTOR_INST %4

Now this code contains an illegal copy from a VGPR to an SGPR.

In order to avoid this problem, this pass searches for PHI instructions which define a register and constrains its definition class to if the user of the PHI's definition register is a vector instruction. If the PHI's definition class is constrained to then the coalescer will be unable to perform the COPY removal from the above example which ultimately led to the creation of an illegal COPY.

Definition in file SIFixSGPRCopies.cpp.