SILowerWWMCopies.cpp Source File (original) (raw)

28using namespace llvm;

30#define DEBUG_TYPE "si-lower-wwm-copies"

32namespace {

34class SILowerWWMCopies {

35public:

37 : LIS(LIS), Indexes(SI), VRM(VRM) {}

40private:

50};

53public:

54 static char ID;

58 }

62 StringRef getPassName() const override { return "SI Lower WWM Copies"; }

64 void getAnalysisUsage(AnalysisUsage &AU) const override {

70 }

71};

73}

76 false, false)

82char SILowerWWMCopiesLegacy::ID = 0;

89 if (!LIS)

90 return true;

94 SlotIndex Idx = LIS->getInstructionIndex(MI);

95 return LR.liveAt(Idx);

96}

101 if (Reg.isPhysical())

102 return;

103

104

106 assert(PhysReg && "should have allocated a physical register");

107

109}

110

111bool SILowerWWMCopiesLegacy::runOnMachineFunction(MachineFunction &MF) {

112 auto *LISWrapper = getAnalysisIfAvailable();

113 auto *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;

114

115 auto *SIWrapper = getAnalysisIfAvailable();

116 auto *Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;

117

118 auto *VRMWrapper = getAnalysisIfAvailable();

119 auto *VRM = VRMWrapper ? &VRMWrapper->getVRM() : nullptr;

120

121 SILowerWWMCopies Impl(LIS, Indexes, VRM);

122 return Impl.run(MF);

123}

124

125PreservedAnalyses

131

132 SILowerWWMCopies Impl(LIS, Indexes, VRM);

133 Impl.run(MF);

135}

136

140

142 TRI = ST.getRegisterInfo();

144

146 return false;

147

151 if (MI.getOpcode() != AMDGPU::WWM_COPY)

152 continue;

153

154

156

157

158

162 TII->insertScratchExecCopy(MF, MBB, InsertPt, DL, RegForExecCopy,

163 isSCCLiveAtMI(MI), Indexes);

164 TII->restoreExec(MF, MBB, ++InsertPt, DL, RegForExecCopy, Indexes);

165 addToWWMSpills(MF, MI.getOperand(0).getReg());

167

168

169 MI.setDesc(TII->get(AMDGPU::COPY));

171 }

172 }

173

175}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

Provides AMDGPU specific target descriptions.

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

AMD GCN specific subclass of TargetSubtarget.

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

PassT::Result * getCachedResult(IRUnitT &IR) const

Get the cached result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

AnalysisUsage & addUsedIfAvailable()

Add the specified Pass class to the set of analyses used by this pass.

void setPreservesAll()

Set by analyses that do not transform their input at all.

This class represents the liveness of a register, stack slot, etc.

bool liveAt(SlotIndex index) const

Wrapper class representing physical registers. Should be passed by value.

static MCRegister from(unsigned Val)

Check the provided unsigned value is a valid MCRegister.

MachineInstrBundleIterator< MachineInstr > iterator

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition SILowerWWMCopies.cpp:126

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...

void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))

SlotIndex - An opaque wrapper around machine indexes.

StringRef - Represent a constant reference to a string, i.e.

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

void initializeSILowerWWMCopiesLegacyPass(PassRegistry &)

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

char & SILowerWWMCopiesLegacyID

Definition SILowerWWMCopies.cpp:84