SIMachineFunctionInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H

14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H

28#include

30namespace llvm {

39public:

45protected:

49public:

53 return false;

54 }

63};

66public:

85 OS << "GWSResource";

86 }

87};

89namespace yaml {

93 union {

96 };

97 std::optional Mask;

110

111

113 if (Other.IsRegister)

115 else

117 }

121 else

124 return *this;

125 }

130

131

137

138private:

139

141};

142

146 if (A.IsRegister)

148 else

150 } else {

151 auto Keys = YamlIO.keys();

157 else

158 YamlIO.setError("missing required key 'reg' or 'offset'");

159 }

161 }

162 static const bool flow = true;

163};

164

189

200

206 YamlIO.mapOptional("privateSegmentWaveByteOffset",

208

211

215 }

216};

217

218

250

255 YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);

256 YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);

257 YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);

258 YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);

259 }

260};

261

278

279

281

284

288

291

292 std::optional ArgInfo;

293

297

303

306

309

311

316

319};

320

372

373}

374

375

376

377

378

379

380

381

387

390 union {

393 };

394

395public:

402};

403

407 assert(AMDGPU::VReg_1024RegClass.contains(Reg) && "Expecting a VGPR block");

408

409 const MCRegister FirstVGPRBlock = AMDGPU::VReg_1024RegClass.getRegister(0);

410 return Reg - FirstVGPRBlock;

411 }

412};

413

414

415

419

420

422

423

424

425 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;

426

427

428

429 Register FrameOffsetReg = AMDGPU::FP_REG;

430

431

432

433

434 Register StackPtrOffsetReg = AMDGPU::SP_REG;

435

436

437

438

439 Register LongBranchReservedReg;

440

442

443

444 unsigned PSInputAddr = 0;

445 unsigned PSInputEnable = 0;

446

447

448

449

450

451

452

453

454

455

456 unsigned BytesInStackArgArea = 0;

457

458 bool ReturnsVoid = true;

459

460

461

462 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};

463

464

465

466 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};

467

468 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;

469

470

471 SmallVector MaxNumWorkGroups = {0, 0, 0};

472

473

474 AMDGPU::ClusterDimsAttr ClusterDims;

475

476private:

477 unsigned NumUserSGPRs = 0;

478 unsigned NumSystemSGPRs = 0;

479

480 unsigned NumWaveDispatchSGPRs = 0;

481 unsigned NumWaveDispatchVGPRs = 0;

482

483 bool HasSpilledSGPRs = false;

484 bool HasSpilledVGPRs = false;

485 bool HasNonSpillStackObjects = false;

486 bool IsStackRealigned = false;

487

488 unsigned NumSpilledSGPRs = 0;

489 unsigned NumSpilledVGPRs = 0;

490

491 unsigned DynamicVGPRBlockSize = 0;

492

493

494

495 unsigned ScratchReservedForDynamicVGPRs = 0;

496

497

498

499 GCNUserSGPRUsageInfo UserSGPRInfo;

500

501

502 bool WorkGroupIDX : 1;

503 bool WorkGroupIDY : 1;

504 bool WorkGroupIDZ : 1;

505 bool WorkGroupInfo : 1;

506 bool LDSKernelId : 1;

507 bool PrivateSegmentWaveByteOffset : 1;

508

509 bool WorkItemIDX : 1;

510 bool WorkItemIDY : 1;

511 bool WorkItemIDZ : 1;

512

513

514

515 bool ImplicitArgPtr : 1;

516

517

518

519 unsigned MinNumAGPRs = ~0u;

520

521

522

523

524 unsigned GITPtrHigh;

525

526 unsigned HighBitsOf32BitAddress;

527

528

529 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;

530

531

532 unsigned Occupancy;

533

534

535

537

538 MCPhysReg getNextUserSGPR() const;

539

540 MCPhysReg getNextSystemSGPR() const;

541

542

543 void MRI_NoteNewVirtualRegister(Register Reg) override;

544 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;

545

546public:

548

554

555private:

556

557

559 SGPRSpillsToVirtualVGPRLanes;

560

561

563 SGPRSpillsToPhysicalVGPRLanes;

564 unsigned NumVirtualVGPRSpillLanes = 0;

565 unsigned NumPhysicalVGPRSpillLanes = 0;

569

570

571

572

573

574

575 WWMSpillsMap WWMSpills;

576

577

578

579

581

583

584

585

586

587 ReservedRegSet WWMReservedRegs;

588

589 bool IsWholeWaveFunction = false;

590

591 using PrologEpilogSGPRSpill =

592 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;

593

594

595

596

598

599

601

603

604

606

607

609

610

611

612 std::optional ScavengeFI;

613

614

615

616

618

619private:

621

622 bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI,

623 unsigned LaneIndex);

624 bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI,

625 unsigned LaneIndex,

626 bool IsPrologEpilog);

627

628public:

630 return VGPRForAGPRCopy;

631 }

632

634 VGPRForAGPRCopy = NewVGPRForAGPRCopy;

635 }

636

638

640 MaskForVGPRBlockOps.grow(RegisterBlock);

641 MaskForVGPRBlockOps[RegisterBlock] = Mask;

642 }

643

645 return MaskForVGPRBlockOps[RegisterBlock];

646 }

647

649 return MaskForVGPRBlockOps.inBounds(RegisterBlock);

650 }

651

652public:

655

659 const override;

660

665

669 : WWMReservedRegs.contains(Reg);

670 }

671

675

677

680 auto I = SGPRSpillsToVirtualVGPRLanes.find(FrameIndex);

681 return (I == SGPRSpillsToVirtualVGPRLanes.end())

684 }

685

688

689 const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }

691

693 return WWMReservedRegs.contains(Reg);

694 }

695

697

700 return PrologEpilogSGPRSpills;

701 }

702

704

706

710

711

712

713 PrologEpilogSGPRSpills.insert(

715 PrologEpilogSGPRSpills, Reg,

716 [](const auto &LHS, const auto &RHS) { return LHS < RHS.first; }),

717 std::make_pair(Reg, SI));

718 }

719

720

721

723 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {

724 return Spill.first == Reg;

725 });

726 return I != PrologEpilogSGPRSpills.end();

727 }

728

729

731 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {

732 return Spill.first == Reg;

733 });

734 if (I != PrologEpilogSGPRSpills.end() &&

736 return I->second.getReg();

737

738 return AMDGPU::NoRegister;

739 }

740

741

743 for (const auto &SI : PrologEpilogSGPRSpills) {

746 }

747 }

748

749

751 return find_if(PrologEpilogSGPRSpills,

752 [FI](const std::pair<Register,

754 return SI.second.getKind() ==

756 SI.second.getIndex() == FI;

757 }) != PrologEpilogSGPRSpills.end();

758 }

759

762 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {

763 return Spill.first == Reg;

764 });

765 assert(I != PrologEpilogSGPRSpills.end());

766

767 return I->second;

768 }

769

772 auto I = SGPRSpillsToPhysicalVGPRLanes.find(FrameIndex);

773 return (I == SGPRSpillsToPhysicalVGPRLanes.end())

776 }

777

780 if (VRegFlags.inBounds(Reg))

781 VRegFlags[Reg] |= Flag;

782 }

783

785 if (Reg.isPhysical())

786 return false;

787

788 return VRegFlags.inBounds(Reg) && VRegFlags[Reg] & Flag;

789 }

790

792

795

798 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,

799 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;

800

802 return SpillAGPR;

803 }

804

806

808

810 return SpillVGPR;

811 }

812

814 auto I = VGPRToAGPRSpills.find(FrameIndex);

815 return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister

816 : I->second.Lanes[Lane];

817 }

818

820 auto I = VGPRToAGPRSpills.find(FrameIndex);

821 if (I != VGPRToAGPRSpills.end())

822 I->second.IsDead = true;

823 }

824

825

826

830

832 bool SpillToPhysVGPRLane = false,

833 bool IsPrologEpilog = false);

835

836

837

839 bool ResetSGPRSpillStackIDs);

840

843

845 return BytesInStackArgArea;

846 }

847

849 BytesInStackArgArea = Bytes;

850 }

851

854

855

857 return ScratchReservedForDynamicVGPRs;

858 }

859

861 ScratchReservedForDynamicVGPRs = SizeInBytes;

862 }

863

864

876 unsigned AllocSizeDWord, int KernArgIdx,

877 int PaddingSGPRs);

878

879

882 ++NumUserSGPRs;

884 }

885

886

889 NumSystemSGPRs += 1;

890 return ArgInfo.WorkGroupIDX.getRegister();

891 }

892

895 NumSystemSGPRs += 1;

896 return ArgInfo.WorkGroupIDY.getRegister();

897 }

898

901 NumSystemSGPRs += 1;

902 return ArgInfo.WorkGroupIDZ.getRegister();

903 }

904

907 NumSystemSGPRs += 1;

908 return ArgInfo.WorkGroupInfo.getRegister();

909 }

910

912

913

915 ArgInfo.WorkItemIDX = Arg;

916 }

917

919 ArgInfo.WorkItemIDY = Arg;

920 }

921

923 ArgInfo.WorkItemIDZ = Arg;

924 }

925

927 ArgInfo.PrivateSegmentWaveByteOffset

929 NumSystemSGPRs += 1;

930 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();

931 }

932

936

938 return WorkGroupIDX;

939 }

940

942 return WorkGroupIDY;

943 }

944

946 return WorkGroupIDZ;

947 }

948

950 return WorkGroupInfo;

951 }

952

954 return PrivateSegmentWaveByteOffset;

955 }

956

958 return WorkItemIDX;

959 }

960

962 return WorkItemIDY;

963 }

964

966 return WorkItemIDZ;

967 }

968

970 return ImplicitArgPtr;

971 }

972

974 return ArgInfo;

975 }

976

978 return ArgInfo;

979 }

980

981 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>

983 return ArgInfo.getPreloadedValue(Value);

984 }

985

987 const auto *Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));

988 return Arg ? Arg->getRegister() : MCRegister();

989 }

990

992 return GITPtrHigh;

993 }

994

996

998 return HighBitsOf32BitAddress;

999 }

1000

1002 return NumUserSGPRs;

1003 }

1004

1006 return NumUserSGPRs + NumSystemSGPRs;

1007 }

1008

1010 return UserSGPRInfo.getNumKernargPreloadSGPRs();

1011 }

1012

1014

1016

1018

1020

1022 if (ArgInfo.PrivateSegmentWaveByteOffset)

1023 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();

1025 }

1026

1027

1028

1030 return ScratchRSrcReg;

1031 }

1032

1034 assert(Reg != 0 && "Should never be unset");

1035 ScratchRSrcReg = Reg;

1036 }

1037

1039 return FrameOffsetReg;

1040 }

1041

1043 assert(Reg != 0 && "Should never be unset");

1044 FrameOffsetReg = Reg;

1045 }

1046

1048 assert(Reg != 0 && "Should never be unset");

1049 StackPtrOffsetReg = Reg;

1050 }

1051

1053

1054

1055

1056

1057

1059 return StackPtrOffsetReg;

1060 }

1061

1063

1065 return ArgInfo.QueuePtr.getRegister();

1066 }

1067

1069 return ArgInfo.ImplicitBufferPtr.getRegister();

1070 }

1071

1073 return HasSpilledSGPRs;

1074 }

1075

1077 HasSpilledSGPRs = Spill;

1078 }

1079

1081 return HasSpilledVGPRs;

1082 }

1083

1085 HasSpilledVGPRs = Spill;

1086 }

1087

1089 return HasNonSpillStackObjects;

1090 }

1091

1093 HasNonSpillStackObjects = StackObject;

1094 }

1095

1097 return IsStackRealigned;

1098 }

1099

1101 IsStackRealigned = Realigned;

1102 }

1103

1105 return NumSpilledSGPRs;

1106 }

1107

1109 return NumSpilledVGPRs;

1110 }

1111

1113 NumSpilledSGPRs += num;

1114 }

1115

1117 NumSpilledVGPRs += num;

1118 }

1119

1121 return PSInputAddr;

1122 }

1123

1125 return PSInputEnable;

1126 }

1127

1129 return PSInputAddr & (1 << Index);

1130 }

1131

1133 PSInputAddr |= 1 << Index;

1134 }

1135

1137 PSInputEnable |= 1 << Index;

1138 }

1139

1141 return ReturnsVoid;

1142 }

1143

1145 ReturnsVoid = Value;

1146 }

1147

1148

1149

1151 return FlatWorkGroupSizes;

1152 }

1153

1154

1156 return FlatWorkGroupSizes.first;

1157 }

1158

1159

1161 return FlatWorkGroupSizes.second;

1162 }

1163

1164

1165

1167 return WavesPerEU;

1168 }

1169

1170

1172 return WavesPerEU.first;

1173 }

1174

1175

1177 return WavesPerEU.second;

1178 }

1179

1182 return &GWSResourcePSV;

1183 }

1184

1186 return Occupancy;

1187 }

1188

1191 return Occupancy;

1192 return (Occupancy < 4) ? Occupancy : 4;

1193 }

1194

1196

1198 if (Occupancy > Limit)

1199 Occupancy = Limit;

1200 }

1201

1203 if (Occupancy < Limit)

1204 Occupancy = Limit;

1206 }

1207

1209

1211

1212

1213

1217

1218

1219

1221

1222

1224

1228

1230};

1231

1232}

1233

1234#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Provides AMDGPU specific target descriptions.

The AMDGPU TargetMachine interface definition for hw codegen targets.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

AMD GCN specific subclass of TargetSubtarget.

static bool IsRegister(const MCParsedAsmOperand &op)

Promote Memory to Register

static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))

Interface definition for SIInstrInfo.

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file implements a set that has insertion order iteration characteristics.

This file defines the SmallVector class.

void printCustom(raw_ostream &OS) const override

Implement printing for PseudoSourceValue.

Definition SIMachineFunctionInfo.h:84

static bool classof(const PseudoSourceValue *V)

Definition SIMachineFunctionInfo.h:70

AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)

Definition SIMachineFunctionInfo.h:67

bool mayAlias(const MachineFrameInfo *) const override

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

Definition SIMachineFunctionInfo.h:80

bool isAliased(const MachineFrameInfo *) const override

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...

Definition SIMachineFunctionInfo.h:75

AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST)

bool isMemoryBound() const

bool needsWaveLimiter() const

bool isConstant(const MachineFrameInfo *) const override

Test whether the memory pointed to by this PseudoSourceValue has a constant value.

Definition SIMachineFunctionInfo.h:50

AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)

Definition SIMachineFunctionInfo.h:46

bool mayAlias(const MachineFrameInfo *) const override

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

Definition SIMachineFunctionInfo.h:60

bool isAliased(const MachineFrameInfo *) const override

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...

Definition SIMachineFunctionInfo.h:56

AMDGPUPSVKind

Definition SIMachineFunctionInfo.h:40

@ PSVImage

Definition SIMachineFunctionInfo.h:41

@ GWSResource

Definition SIMachineFunctionInfo.h:42

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Lightweight error class with error context and mandatory checking.

Wrapper class representing physical registers. Should be passed by value.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

This class implements a map that also provides access to all stored values in a deterministic order.

int Index

Definition SIMachineFunctionInfo.h:391

PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)

Definition SIMachineFunctionInfo.h:397

PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)

Definition SIMachineFunctionInfo.h:396

int getIndex() const

Definition SIMachineFunctionInfo.h:400

SGPRSaveKind getKind() const

Definition SIMachineFunctionInfo.h:401

Definition SIMachineFunctionInfo.h:392

Definition SIMachineFunctionInfo.h:399

Special value supplied for machine level alias analysis.

PseudoSourceValue(unsigned Kind, const TargetMachine &TM)

Wrapper class representing virtual and physical registers.

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...

Definition SIMachineFunctionInfo.h:417

unsigned getNumWaveDispatchVGPRs() const

Definition SIMachineFunctionInfo.h:1017

bool hasNonSpillStackObjects() const

Definition SIMachineFunctionInfo.h:1088

ArrayRef< PrologEpilogSGPRSpill > getPrologEpilogSGPRSpills() const

Definition SIMachineFunctionInfo.h:698

const WWMSpillsMap & getWWMSpills() const

Definition SIMachineFunctionInfo.h:689

bool isPSInputAllocated(unsigned Index) const

Definition SIMachineFunctionInfo.h:1128

void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const

Definition SIMachineFunctionInfo.h:742

unsigned getMinNumAGPRs() const

Definition SIMachineFunctionInfo.h:1210

ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const

Definition SIMachineFunctionInfo.h:801

void setSGPRForEXECCopy(Register Reg)

Definition SIMachineFunctionInfo.h:807

bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)

unsigned getOccupancy() const

Definition SIMachineFunctionInfo.h:1185

unsigned getNumPreloadedSGPRs() const

Definition SIMachineFunctionInfo.h:1005

void shiftWwmVGPRsToLowestRange(MachineFunction &MF, SmallVectorImpl< Register > &WWMVGPRs, BitVector &SavedVGPRs)

void setWorkItemIDY(ArgDescriptor Arg)

Definition SIMachineFunctionInfo.h:918

unsigned getNumSpilledVGPRs() const

Definition SIMachineFunctionInfo.h:1108

bool hasLDSKernelId() const

Definition SIMachineFunctionInfo.h:911

void increaseOccupancy(const MachineFunction &MF, unsigned Limit)

Definition SIMachineFunctionInfo.h:1202

unsigned getNumWaveDispatchSGPRs() const

Definition SIMachineFunctionInfo.h:1013

void setWorkItemIDZ(ArgDescriptor Arg)

Definition SIMachineFunctionInfo.h:922

std::pair< unsigned, unsigned > getWavesPerEU() const

Definition SIMachineFunctionInfo.h:1166

void setMaskForVGPRBlockOps(Register RegisterBlock, uint32_t Mask)

Definition SIMachineFunctionInfo.h:639

unsigned getMaxNumWorkGroupsZ() const

Definition SIMachineFunctionInfo.h:1227

MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const

Definition SIMachineFunctionInfo.h:813

unsigned getNumSpilledSGPRs() const

Definition SIMachineFunctionInfo.h:1104

GCNUserSGPRUsageInfo & getUserSGPRInfo()

Definition SIMachineFunctionInfo.h:703

void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))

Definition SIMachineFunctionInfo.h:1062

unsigned getDynamicVGPRBlockSize() const

Definition SIMachineFunctionInfo.h:853

bool hasSpilledVGPRs() const

Definition SIMachineFunctionInfo.h:1080

void setFlag(Register Reg, uint8_t Flag)

Definition SIMachineFunctionInfo.h:778

void setVGPRToAGPRSpillDead(int FrameIndex)

Definition SIMachineFunctionInfo.h:819

unsigned getMaxFlatWorkGroupSize() const

Definition SIMachineFunctionInfo.h:1160

bool isWholeWaveFunction() const

Definition SIMachineFunctionInfo.h:696

std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const

Definition SIMachineFunctionInfo.h:1150

Definition SIMachineFunctionInfo.h:1058

bool isStackRealigned() const

Definition SIMachineFunctionInfo.h:1096

Returns the physical register reserved for use as the resource descriptor for scratch accesses.

Definition SIMachineFunctionInfo.h:1029

bool returnsVoid() const

Definition SIMachineFunctionInfo.h:1140

unsigned getMaxWavesPerEU() const

Definition SIMachineFunctionInfo.h:1176

void setStackPtrOffsetReg(Register Reg)

Definition SIMachineFunctionInfo.h:1047

Increment user SGPRs used for padding the argument list only.

Definition SIMachineFunctionInfo.h:880

ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const

Definition SIMachineFunctionInfo.h:809

ArrayRef< Register > getSGPRSpillPhysVGPRs() const

Definition SIMachineFunctionInfo.h:687

int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)

bool hasWorkGroupIDZ() const

Definition SIMachineFunctionInfo.h:945

Definition SIMachineFunctionInfo.h:1064

ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const

Definition SIMachineFunctionInfo.h:679

uint32_t getMaskForVGPRBlockOps(Register RegisterBlock) const

Definition SIMachineFunctionInfo.h:644

unsigned getMaxMemoryClusterDWords() const

Definition SIMachineFunctionInfo.h:1208

SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default

bool hasMaskForVGPRBlockOps(Register RegisterBlock) const

Definition SIMachineFunctionInfo.h:648

AMDGPU::ClusterDimsAttr getClusterDims() const

Definition SIMachineFunctionInfo.h:1229

SmallVector< unsigned > getMaxNumWorkGroups() const

Definition SIMachineFunctionInfo.h:1223

void clearNonWWMRegAllocMask()

Definition SIMachineFunctionInfo.h:674

bool hasPrologEpilogSGPRSpillEntry(Register Reg) const

Definition SIMachineFunctionInfo.h:722

bool hasWorkGroupIDY() const

Definition SIMachineFunctionInfo.h:941

void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)

Definition SIMachineFunctionInfo.h:633

bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)

Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.

Definition SIMachineFunctionInfo.h:893

void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const

void setBytesInStackArgArea(unsigned Bytes)

Definition SIMachineFunctionInfo.h:848

void setNumWaveDispatchSGPRs(unsigned Count)

Definition SIMachineFunctionInfo.h:1015

SIModeRegisterDefaults getMode() const

Definition SIMachineFunctionInfo.h:676

Definition SIMachineFunctionInfo.h:805

void setFrameOffsetReg(Register Reg)

Definition SIMachineFunctionInfo.h:1042

static bool MFMAVGPRForm

Definition SIMachineFunctionInfo.h:547

bool isWWMReservedRegister(Register Reg) const

Definition SIMachineFunctionInfo.h:692

ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const

Definition SIMachineFunctionInfo.h:771

Definition SIMachineFunctionInfo.h:926

std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const

Definition SIMachineFunctionInfo.h:982

bool hasWorkGroupInfo() const

Definition SIMachineFunctionInfo.h:949

bool mayUseAGPRs(const Function &F) const

bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const

friend class GCNTargetMachine

Definition SIMachineFunctionInfo.h:418

bool hasWorkItemIDY() const

Definition SIMachineFunctionInfo.h:961

unsigned getMinFlatWorkGroupSize() const

Definition SIMachineFunctionInfo.h:1155

Definition SIMachineFunctionInfo.h:629

const GCNUserSGPRUsageInfo & getUserSGPRInfo() const

Definition SIMachineFunctionInfo.h:705

bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)

void setPrivateSegmentWaveByteOffset(Register Reg)

Definition SIMachineFunctionInfo.h:933

unsigned getMinWavesPerEU() const

Definition SIMachineFunctionInfo.h:1171

Definition SIMachineFunctionInfo.h:1038

void setLongBranchReservedReg(Register Reg)

Definition SIMachineFunctionInfo.h:1052

bool hasWorkGroupIDX() const

Definition SIMachineFunctionInfo.h:937

const AMDGPUFunctionArgInfo & getArgInfo() const

Definition SIMachineFunctionInfo.h:977

unsigned getMaxNumWorkGroupsX() const

Definition SIMachineFunctionInfo.h:1225

unsigned getBytesInStackArgArea() const

Definition SIMachineFunctionInfo.h:844

void setHasSpilledVGPRs(bool Spill=true)

Definition SIMachineFunctionInfo.h:1084

void setIfReturnsVoid(bool Value)

Definition SIMachineFunctionInfo.h:1144

void limitOccupancy(unsigned Limit)

Definition SIMachineFunctionInfo.h:1197

bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)

If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.

void setScratchReservedForDynamicVGPRs(unsigned SizeInBytes)

Definition SIMachineFunctionInfo.h:860

BitVector getNonWWMRegMask() const

Definition SIMachineFunctionInfo.h:673

void markPSInputAllocated(unsigned Index)

Definition SIMachineFunctionInfo.h:1132

void setWorkItemIDX(ArgDescriptor Arg)

Definition SIMachineFunctionInfo.h:914

bool isWWMReg(Register Reg) const

Definition SIMachineFunctionInfo.h:667

MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override

Make a functionally equivalent copy of this MachineFunctionInfo in MF.

bool hasVRegFlags()

Definition SIMachineFunctionInfo.h:791

bool checkFlag(Register Reg, uint8_t Flag) const

Definition SIMachineFunctionInfo.h:784

void setNumWaveDispatchVGPRs(unsigned Count)

Definition SIMachineFunctionInfo.h:1019

void markPSInputEnabled(unsigned Index)

Definition SIMachineFunctionInfo.h:1136

void addToSpilledVGPRs(unsigned num)

Definition SIMachineFunctionInfo.h:1116

MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const

Definition SIMachineFunctionInfo.h:986

uint32_t get32BitAddressHighBits() const

Definition SIMachineFunctionInfo.h:997

unsigned getMinAllowedOccupancy() const

Definition SIMachineFunctionInfo.h:1189

void setHasSpilledSGPRs(bool Spill=true)

Definition SIMachineFunctionInfo.h:1076

bool checkIndexInPrologEpilogSGPRSpills(int FI) const

Definition SIMachineFunctionInfo.h:750

void updateNonWWMRegMask(BitVector &RegMask)

Definition SIMachineFunctionInfo.h:672

bool selectAGPRFormMFMA(unsigned NumRegs) const

Return true if an MFMA that requires at least NumRegs should select to the AGPR form,...

Definition SIMachineFunctionInfo.h:1214

unsigned getNumKernargPreloadedSGPRs() const

Definition SIMachineFunctionInfo.h:1009

bool hasWorkItemIDX() const

Definition SIMachineFunctionInfo.h:957

unsigned getNumUserSGPRs() const

Definition SIMachineFunctionInfo.h:1001

unsigned getScratchReservedForDynamicVGPRs() const

Definition SIMachineFunctionInfo.h:856

const ReservedRegSet & getWWMReservedRegs() const

Definition SIMachineFunctionInfo.h:690

Definition SIMachineFunctionInfo.h:1068

std::optional< int > getOptionalScavengeFI() const

Definition SIMachineFunctionInfo.h:842

AMDGPUFunctionArgInfo & getArgInfo()

Definition SIMachineFunctionInfo.h:973

const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const

Definition SIMachineFunctionInfo.h:761

bool isDynamicVGPREnabled() const

Definition SIMachineFunctionInfo.h:852

void setHasNonSpillStackObjects(bool StackObject=true)

Definition SIMachineFunctionInfo.h:1092

void setIsStackRealigned(bool Realigned=true)

Definition SIMachineFunctionInfo.h:1100

unsigned getGITPtrHigh() const

Definition SIMachineFunctionInfo.h:991

void limitOccupancy(const MachineFunction &MF)

bool hasSpilledSGPRs() const

Definition SIMachineFunctionInfo.h:1072

ArrayRef< Register > getSGPRSpillVGPRs() const

Definition SIMachineFunctionInfo.h:686

unsigned getPSInputAddr() const

Definition SIMachineFunctionInfo.h:1120

SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)

void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)

Definition SIMachineFunctionInfo.h:707

Definition SIMachineFunctionInfo.h:730

Definition SIMachineFunctionInfo.h:1021

bool hasImplicitArgPtr() const

Definition SIMachineFunctionInfo.h:969

Definition SIMachineFunctionInfo.h:899

Definition SIMachineFunctionInfo.h:905

bool hasWorkItemIDZ() const

Definition SIMachineFunctionInfo.h:965

unsigned getMaxNumWorkGroupsY() const

Definition SIMachineFunctionInfo.h:1226

unsigned getPSInputEnable() const

Definition SIMachineFunctionInfo.h:1124

void setScratchRSrcReg(Register Reg)

Definition SIMachineFunctionInfo.h:1033

void addToSpilledSGPRs(unsigned num)

Definition SIMachineFunctionInfo.h:1112

const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)

Definition SIMachineFunctionInfo.h:1181

void reserveWWMRegister(Register Reg)

Definition SIMachineFunctionInfo.h:666

bool hasPrivateSegmentWaveByteOffset() const

Definition SIMachineFunctionInfo.h:953

Definition SIMachineFunctionInfo.h:887

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

A SetVector that performs no allocations if smaller than a certain size.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

virtual bool outputting() const =0

void mapOptional(StringRef Key, T &Val)

virtual void setError(const Twine &)=0

void mapRequired(StringRef Key, T &Val)

virtual std::vector< StringRef > keys()=0

This is an optimization pass for GlobalISel generic memory operations.

SGPRSaveKind

Definition SIMachineFunctionInfo.h:382

@ SPILL_TO_MEM

Definition SIMachineFunctionInfo.h:385

@ SPILL_TO_VGPR_LANE

Definition SIMachineFunctionInfo.h:384

@ COPY_TO_SCRATCH_SGPR

Definition SIMachineFunctionInfo.h:383

auto upper_bound(R &&Range, T &&Value)

Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...

FunctionAddr VTableAddr Count

bool is_sorted(R &&Range, Compare C)

Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

FunctionAddr VTableAddr Next

ArrayRef(const T &OneElt) -> ArrayRef< T >

constexpr unsigned DefaultMemoryClusterDWordsLimit

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

This struct is a compact representation of a valid (non-zero power of two) alignment.

static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)

@ PreserveSign

The sign of a flushed-to-zero number is preserved in the sign of 0.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

bool IsDead

Definition SIMachineFunctionInfo.h:552

bool FullyAllocated

Definition SIMachineFunctionInfo.h:551

SmallVector< MCPhysReg, 32 > Lanes

Definition SIMachineFunctionInfo.h:550

Definition SIMachineFunctionInfo.h:405

unsigned operator()(Register Reg) const

Definition SIMachineFunctionInfo.h:406

Function object to check whether the first component of a container supported by std::get (like std::...

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.

static void mapping(IO &YamlIO, SIArgumentInfo &AI)

Definition SIMachineFunctionInfo.h:191

static const bool flow

Definition SIMachineFunctionInfo.h:162

static void mapping(IO &YamlIO, SIArgument &A)

Definition SIMachineFunctionInfo.h:144

static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)

Definition SIMachineFunctionInfo.h:322

static void mapping(IO &YamlIO, SIMode &Mode)

Definition SIMachineFunctionInfo.h:252

This class should be specialized by any type that needs to be converted to/from a YAML mapping.

std::optional< SIArgument > PrivateSegmentWaveByteOffset

Definition SIMachineFunctionInfo.h:180

std::optional< SIArgument > WorkGroupIDY

Definition SIMachineFunctionInfo.h:176

std::optional< SIArgument > FlatScratchInit

Definition SIMachineFunctionInfo.h:171

std::optional< SIArgument > DispatchPtr

Definition SIMachineFunctionInfo.h:167

std::optional< SIArgument > DispatchID

Definition SIMachineFunctionInfo.h:170

std::optional< SIArgument > WorkItemIDY

Definition SIMachineFunctionInfo.h:186

std::optional< SIArgument > WorkGroupIDX

Definition SIMachineFunctionInfo.h:175

std::optional< SIArgument > ImplicitArgPtr

Definition SIMachineFunctionInfo.h:182

std::optional< SIArgument > QueuePtr

Definition SIMachineFunctionInfo.h:168

std::optional< SIArgument > WorkGroupInfo

Definition SIMachineFunctionInfo.h:178

std::optional< SIArgument > LDSKernelId

Definition SIMachineFunctionInfo.h:179

std::optional< SIArgument > ImplicitBufferPtr

Definition SIMachineFunctionInfo.h:183

std::optional< SIArgument > WorkItemIDX

Definition SIMachineFunctionInfo.h:185

std::optional< SIArgument > KernargSegmentPtr

Definition SIMachineFunctionInfo.h:169

std::optional< SIArgument > WorkItemIDZ

Definition SIMachineFunctionInfo.h:187

std::optional< SIArgument > PrivateSegmentSize

Definition SIMachineFunctionInfo.h:172

std::optional< SIArgument > PrivateSegmentBuffer

Definition SIMachineFunctionInfo.h:166

std::optional< SIArgument > FirstKernArgPreloadReg

Definition SIMachineFunctionInfo.h:173

std::optional< SIArgument > WorkGroupIDZ

Definition SIMachineFunctionInfo.h:177

unsigned StackOffset

Definition SIMachineFunctionInfo.h:95

std::optional< unsigned > Mask

Definition SIMachineFunctionInfo.h:97

~SIArgument()

Definition SIMachineFunctionInfo.h:126

SIArgument()

Definition SIMachineFunctionInfo.h:100

SIArgument(const SIArgument &Other)

Definition SIMachineFunctionInfo.h:101

StringValue RegisterName

Definition SIMachineFunctionInfo.h:94

SIArgument & operator=(const SIArgument &Other)

Definition SIMachineFunctionInfo.h:109

static SIArgument createArgument(bool IsReg)

Definition SIMachineFunctionInfo.h:132

bool IsRegister

Definition SIMachineFunctionInfo.h:92

~SIMachineFunctionInfo() override=default

unsigned MaxMemoryClusterDWords

Definition SIMachineFunctionInfo.h:296

bool HasSpilledVGPRs

Definition SIMachineFunctionInfo.h:274

StringValue SGPRForEXECCopy

Definition SIMachineFunctionInfo.h:301

bool HasSpilledSGPRs

Definition SIMachineFunctionInfo.h:273

bool ReturnsVoid

Definition SIMachineFunctionInfo.h:290

Align DynLDSAlign

Definition SIMachineFunctionInfo.h:267

SmallVector< StringValue > WWMReservedRegs

Definition SIMachineFunctionInfo.h:283

uint32_t HighBitsOf32BitAddress

Definition SIMachineFunctionInfo.h:277

uint32_t GDSSize

Definition SIMachineFunctionInfo.h:266

bool MemoryBound

Definition SIMachineFunctionInfo.h:271

unsigned Occupancy

Definition SIMachineFunctionInfo.h:280

unsigned PSInputEnable

Definition SIMachineFunctionInfo.h:295

Align MaxKernArgAlign

Definition SIMachineFunctionInfo.h:264

SIMachineFunctionInfo()=default

StringValue FrameOffsetReg

Definition SIMachineFunctionInfo.h:286

StringValue LongBranchReservedReg

Definition SIMachineFunctionInfo.h:302

unsigned NumKernargPreloadSGPRs

Definition SIMachineFunctionInfo.h:310

uint64_t ExplicitKernArgSize

Definition SIMachineFunctionInfo.h:263

uint32_t LDSSize

Definition SIMachineFunctionInfo.h:265

bool WaveLimiter

Definition SIMachineFunctionInfo.h:272

unsigned PSInputAddr

Definition SIMachineFunctionInfo.h:294

bool IsWholeWaveFunction

Definition SIMachineFunctionInfo.h:305

uint16_t NumWaveDispatchSGPRs

Definition SIMachineFunctionInfo.h:275

void mappingImpl(yaml::IO &YamlIO) override

bool NoSignedZerosFPMath

Definition SIMachineFunctionInfo.h:270

bool IsEntryFunction

Definition SIMachineFunctionInfo.h:268

unsigned DynamicVGPRBlockSize

Definition SIMachineFunctionInfo.h:307

StringValue VGPRForAGPRCopy

Definition SIMachineFunctionInfo.h:300

SIMode Mode

Definition SIMachineFunctionInfo.h:298

bool IsChainFunction

Definition SIMachineFunctionInfo.h:269

bool HasInitWholeWave

Definition SIMachineFunctionInfo.h:304

std::optional< SIArgumentInfo > ArgInfo

Definition SIMachineFunctionInfo.h:292

SmallVector< StringValue, 2 > SpillPhysVGPRS

Definition SIMachineFunctionInfo.h:282

std::optional< FrameIndex > ScavengeFI

Definition SIMachineFunctionInfo.h:299

uint16_t NumWaveDispatchVGPRs

Definition SIMachineFunctionInfo.h:276

unsigned BytesInStackArgArea

Definition SIMachineFunctionInfo.h:289

unsigned ScratchReservedForDynamicVGPRs

Definition SIMachineFunctionInfo.h:308

StringValue ScratchRSrcReg

Definition SIMachineFunctionInfo.h:285

StringValue StackPtrOffsetReg

Definition SIMachineFunctionInfo.h:287

bool IEEE

Definition SIMachineFunctionInfo.h:220

SIMode(const SIModeRegisterDefaults &Mode)

Definition SIMachineFunctionInfo.h:229

bool DX10Clamp

Definition SIMachineFunctionInfo.h:221

bool FP64FP16OutputDenormals

Definition SIMachineFunctionInfo.h:225

bool operator==(const SIMode Other) const

Definition SIMachineFunctionInfo.h:241

bool FP64FP16InputDenormals

Definition SIMachineFunctionInfo.h:224

bool FP32OutputDenormals

Definition SIMachineFunctionInfo.h:223

bool FP32InputDenormals

Definition SIMachineFunctionInfo.h:222

A wrapper around std::string which contains a source range that's being set during parsing.