SIMachineFunctionInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H

14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H

28#include

30namespace llvm {

32class MachineFrameInfo;

33class MachineFunction;

34class SIMachineFunctionInfo;

35class SIRegisterInfo;

36class TargetRegisterClass;

39public:

45protected:

49public:

53 return false;

54 }

57 return true;

58 }

61 return true;

62 }

63};

66public:

72 }

76 return false;

77 }

81 return false;

82 }

85 OS << "GWSResource";

86 }

87};

89namespace yaml {

93 union {

96 };

97 std::optional Mask;

105 else

108 }

110

111

113 if (Other.IsRegister)

115 else

117 }

121 else

124 return *this;

125 }

129 }

130

131

133 if (IsReg)

136 }

137

138private:

139

141};

142

145 if (YamlIO.outputting()) {

146 if (A.IsRegister)

147 YamlIO.mapRequired("reg", A.RegisterName);

148 else

149 YamlIO.mapRequired("offset", A.StackOffset);

150 } else {

151 auto Keys = YamlIO.keys();

154 YamlIO.mapRequired("reg", A.RegisterName);

156 YamlIO.mapRequired("offset", A.StackOffset);

157 else

158 YamlIO.setError("missing required key 'reg' or 'offset'");

159 }

160 YamlIO.mapOptional("mask", A.Mask);

161 }

162 static const bool flow = true;

163};

164

173

180

183

187};

188

198

204 YamlIO.mapOptional("privateSegmentWaveByteOffset",

206

209

213 }

214};

215

216

224

226

237 }

238

246 }

247};

248

251 YamlIO.mapOptional("ieee", Mode.IEEE, true);

252 YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);

253 YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);

254 YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);

255 YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);

256 YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);

257 }

258};

259

274

275

277

280

284

287

288 std::optional ArgInfo;

289

293

299

301

306

309};

310

314 UINT64_C(0));

340 YamlIO.mapOptional("highBitsOf32BitAddress",

347 StringValue());

349 StringValue());

353 }

354};

355

356}

357

358

359

360

361

362

363

364

369};

370

373 union {

376 };

377

378public:

381 : Kind(K), Reg(R) {}

385};

386

387

388

392

393

395

396

397

398 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;

399

400

401

402 Register FrameOffsetReg = AMDGPU::FP_REG;

403

404

405

406

407 Register StackPtrOffsetReg = AMDGPU::SP_REG;

408

409

410

411

412 Register LongBranchReservedReg;

413

415

416

417 unsigned PSInputAddr = 0;

418 unsigned PSInputEnable = 0;

419

420

421

422

423

424

425

426

427

428

429 unsigned BytesInStackArgArea = 0;

430

431 bool ReturnsVoid = true;

432

433

434

435 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};

436

437

438

439 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};

440

441 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;

442

443

444 SmallVector MaxNumWorkGroups = {0, 0, 0};

445

446private:

447 unsigned NumUserSGPRs = 0;

448 unsigned NumSystemSGPRs = 0;

449

450 bool HasSpilledSGPRs = false;

451 bool HasSpilledVGPRs = false;

452 bool HasNonSpillStackObjects = false;

453 bool IsStackRealigned = false;

454

455 unsigned NumSpilledSGPRs = 0;

456 unsigned NumSpilledVGPRs = 0;

457

458

459

460 GCNUserSGPRUsageInfo UserSGPRInfo;

461

462

463 bool WorkGroupIDX : 1;

464 bool WorkGroupIDY : 1;

465 bool WorkGroupIDZ : 1;

466 bool WorkGroupInfo : 1;

467 bool LDSKernelId : 1;

468 bool PrivateSegmentWaveByteOffset : 1;

469

470 bool WorkItemIDX : 1;

471 bool WorkItemIDY : 1;

472 bool WorkItemIDZ : 1;

473

474

475

476 bool ImplicitArgPtr : 1;

477

478 bool MayNeedAGPRs : 1;

479

480

481

482

483 unsigned GITPtrHigh;

484

485 unsigned HighBitsOf32BitAddress;

486

487

488 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;

489

490

491 unsigned Occupancy;

492

493

494

496

497 mutable std::optional UsesAGPRs;

498

499 MCPhysReg getNextUserSGPR() const;

500

501 MCPhysReg getNextSystemSGPR() const;

502

503

504 void MRI_NoteNewVirtualRegister(Register Reg) override;

505 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;

506

507public:

512 };

513

514private:

515

516

518 SGPRSpillsToVirtualVGPRLanes;

519

520

522 SGPRSpillsToPhysicalVGPRLanes;

523 unsigned NumVirtualVGPRSpillLanes = 0;

524 unsigned NumPhysicalVGPRSpillLanes = 0;

528

529

530

531

532

533

535

536

537

538

540

542

543

544

545

547

548 using PrologEpilogSGPRSpill =

549 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;

550

551

552

553

555

556

558

560

561

563

564

566

567

568

569 std::optional ScavengeFI;

570

571private:

573

574 bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI,

575 unsigned LaneIndex);

576 bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI,

577 unsigned LaneIndex,

578 bool IsPrologEpilog);

579

580public:

582 return VGPRForAGPRCopy;

583 }

584

586 VGPRForAGPRCopy = NewVGPRForAGPRCopy;

587 }

588

590

591public:

594

598 const override;

599

604

609 }

610

614

616

619 auto I = SGPRSpillsToVirtualVGPRLanes.find(FrameIndex);

620 return (I == SGPRSpillsToVirtualVGPRLanes.end())

623 }

624

627

630

633 return PrologEpilogSGPRSpills;

634 }

635

637

639

643

644

645

646 PrologEpilogSGPRSpills.insert(

648 PrologEpilogSGPRSpills, Reg,

649 [](const auto &LHS, const auto &RHS) { return LHS < RHS.first; }),

650 std::make_pair(Reg, SI));

651 }

652

653

654

656 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {

657 return Spill.first == Reg;

658 });

659 return I != PrologEpilogSGPRSpills.end();

660 }

661

662

664 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {

665 return Spill.first == Reg;

666 });

667 if (I != PrologEpilogSGPRSpills.end() &&

669 return I->second.getReg();

670

671 return AMDGPU::NoRegister;

672 }

673

674

676 for (const auto &SI : PrologEpilogSGPRSpills) {

678 Regs.push_back(SI.second.getReg());

679 }

680 }

681

682

684 return find_if(PrologEpilogSGPRSpills,

685 [FI](const std::pair<Register,

687 return SI.second.getKind() ==

689 SI.second.getIndex() == FI;

690 }) != PrologEpilogSGPRSpills.end();

691 }

692

695 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {

696 return Spill.first == Reg;

697 });

698 assert(I != PrologEpilogSGPRSpills.end());

699

700 return I->second;

701 }

702

705 auto I = SGPRSpillsToPhysicalVGPRLanes.find(FrameIndex);

706 return (I == SGPRSpillsToPhysicalVGPRLanes.end())

709 }

710

713 if (VRegFlags.inBounds(Reg))

714 VRegFlags[Reg] |= Flag;

715 }

716

718 if (Reg.isPhysical())

719 return false;

720

721 return VRegFlags.inBounds(Reg) && VRegFlags[Reg] & Flag;

722 }

723

725

728

731 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,

732 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;

733

735 return SpillAGPR;

736 }

737

739

741

743 return SpillVGPR;

744 }

745

747 auto I = VGPRToAGPRSpills.find(FrameIndex);

748 return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister

749 : I->second.Lanes[Lane];

750 }

751

753 auto I = VGPRToAGPRSpills.find(FrameIndex);

754 if (I != VGPRToAGPRSpills.end())

755 I->second.IsDead = true;

756 }

757

758

759

763

765 bool SpillToPhysVGPRLane = false,

766 bool IsPrologEpilog = false);

768

769

770

772 bool ResetSGPRSpillStackIDs);

773

776

778 return BytesInStackArgArea;

779 }

780

782 BytesInStackArgArea = Bytes;

783 }

784

785

797 unsigned AllocSizeDWord, int KernArgIdx,

798 int PaddingSGPRs);

799

800

802 Register Next = getNextUserSGPR();

803 ++NumUserSGPRs;

804 return Next;

805 }

806

807

810 NumSystemSGPRs += 1;

811 return ArgInfo.WorkGroupIDX.getRegister();

812 }

813

816 NumSystemSGPRs += 1;

817 return ArgInfo.WorkGroupIDY.getRegister();

818 }

819

822 NumSystemSGPRs += 1;

823 return ArgInfo.WorkGroupIDZ.getRegister();

824 }

825

828 NumSystemSGPRs += 1;

829 return ArgInfo.WorkGroupInfo.getRegister();

830 }

831

833

834

836 ArgInfo.WorkItemIDX = Arg;

837 }

838

840 ArgInfo.WorkItemIDY = Arg;

841 }

842

844 ArgInfo.WorkItemIDZ = Arg;

845 }

846

848 ArgInfo.PrivateSegmentWaveByteOffset

850 NumSystemSGPRs += 1;

851 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();

852 }

853

856 }

857

859 return WorkGroupIDX;

860 }

861

863 return WorkGroupIDY;

864 }

865

867 return WorkGroupIDZ;

868 }

869

871 return WorkGroupInfo;

872 }

873

875 return PrivateSegmentWaveByteOffset;

876 }

877

879 return WorkItemIDX;

880 }

881

883 return WorkItemIDY;

884 }

885

887 return WorkItemIDZ;

888 }

889

891 return ImplicitArgPtr;

892 }

893

896 }

897

900 }

901

902 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>

905 }

906

908 const auto *Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));

909 return Arg ? Arg->getRegister() : MCRegister();

910 }

911

913 return GITPtrHigh;

914 }

915

917

919 return HighBitsOf32BitAddress;

920 }

921

923 return NumUserSGPRs;

924 }

925

927 return NumUserSGPRs + NumSystemSGPRs;

928 }

929

931 return UserSGPRInfo.getNumKernargPreloadSGPRs();

932 }

933

935 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();

936 }

937

938

939

941 return ScratchRSrcReg;

942 }

943

945 assert(Reg != 0 && "Should never be unset");

946 ScratchRSrcReg = Reg;

947 }

948

950 return FrameOffsetReg;

951 }

952

954 assert(Reg != 0 && "Should never be unset");

955 FrameOffsetReg = Reg;

956 }

957

959 assert(Reg != 0 && "Should never be unset");

960 StackPtrOffsetReg = Reg;

961 }

962

964

965

966

967

968

970 return StackPtrOffsetReg;

971 }

972

974

976 return ArgInfo.QueuePtr.getRegister();

977 }

978

980 return ArgInfo.ImplicitBufferPtr.getRegister();

981 }

982

984 return HasSpilledSGPRs;

985 }

986

988 HasSpilledSGPRs = Spill;

989 }

990

992 return HasSpilledVGPRs;

993 }

994

996 HasSpilledVGPRs = Spill;

997 }

998

1000 return HasNonSpillStackObjects;

1001 }

1002

1004 HasNonSpillStackObjects = StackObject;

1005 }

1006

1008 return IsStackRealigned;

1009 }

1010

1012 IsStackRealigned = Realigned;

1013 }

1014

1016 return NumSpilledSGPRs;

1017 }

1018

1020 return NumSpilledVGPRs;

1021 }

1022

1024 NumSpilledSGPRs += num;

1025 }

1026

1028 NumSpilledVGPRs += num;

1029 }

1030

1032 return PSInputAddr;

1033 }

1034

1036 return PSInputEnable;

1037 }

1038

1040 return PSInputAddr & (1 << Index);

1041 }

1042

1044 PSInputAddr |= 1 << Index;

1045 }

1046

1048 PSInputEnable |= 1 << Index;

1049 }

1050

1052 return ReturnsVoid;

1053 }

1054

1056 ReturnsVoid = Value;

1057 }

1058

1059

1060

1062 return FlatWorkGroupSizes;

1063 }

1064

1065

1067 return FlatWorkGroupSizes.first;

1068 }

1069

1070

1072 return FlatWorkGroupSizes.second;

1073 }

1074

1075

1076

1078 return WavesPerEU;

1079 }

1080

1081

1083 return WavesPerEU.first;

1084 }

1085

1086

1088 return WavesPerEU.second;

1089 }

1090

1093 return &GWSResourcePSV;

1094 }

1095

1097 return Occupancy;

1098 }

1099

1102 return Occupancy;

1103 return (Occupancy < 4) ? Occupancy : 4;

1104 }

1105

1107

1109 if (Occupancy > Limit)

1110 Occupancy = Limit;

1111 }

1112

1114 if (Occupancy < Limit)

1115 Occupancy = Limit;

1117 }

1118

1120

1122 return MayNeedAGPRs;

1123 }

1124

1125

1126

1128

1129

1131

1132

1134

1138};

1139

1140}

1141

1142#endif

Provides AMDGPU specific target descriptions.

The AMDGPU TargetMachine interface definition for hw codegen targets.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

AMD GCN specific subclass of TargetSubtarget.

unsigned const TargetRegisterInfo * TRI

Promote Memory to Register

static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))

Interface definition for SIInstrInfo.

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file implements a set that has insertion order iteration characteristics.

This file defines the SmallVector class.

void printCustom(raw_ostream &OS) const override

Implement printing for PseudoSourceValue.

static bool classof(const PseudoSourceValue *V)

AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)

bool mayAlias(const MachineFrameInfo *) const override

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

bool isAliased(const MachineFrameInfo *) const override

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...

bool isMemoryBound() const

bool needsWaveLimiter() const

bool isConstant(const MachineFrameInfo *) const override

Test whether the memory pointed to by this PseudoSourceValue has a constant value.

AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)

bool mayAlias(const MachineFrameInfo *) const override

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

bool isAliased(const MachineFrameInfo *) const override

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

void clear()

clear - Removes all bits from the bitvector.

Allocate memory in an ever growing pool, as if by bump-pointer.

iterator find(const_arg_type_t< KeyT > Val)

Lightweight error class with error context and mandatory checking.

Wrapper class representing physical registers. Should be passed by value.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)

PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)

SGPRSaveKind getKind() const

Special value supplied for machine level alias analysis.

Wrapper class representing virtual and physical registers.

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...

bool hasNonSpillStackObjects() const

ArrayRef< PrologEpilogSGPRSpill > getPrologEpilogSGPRSpills() const

const WWMSpillsMap & getWWMSpills() const

bool usesAGPRs(const MachineFunction &MF) const

bool isPSInputAllocated(unsigned Index) const

void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const

ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const

void setSGPRForEXECCopy(Register Reg)

bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)

unsigned getOccupancy() const

unsigned getNumPreloadedSGPRs() const

void shiftWwmVGPRsToLowestRange(MachineFunction &MF, SmallVectorImpl< Register > &WWMVGPRs, BitVector &SavedVGPRs)

void setWorkItemIDY(ArgDescriptor Arg)

unsigned getNumSpilledVGPRs() const

bool hasLDSKernelId() const

void increaseOccupancy(const MachineFunction &MF, unsigned Limit)

void setWorkItemIDZ(ArgDescriptor Arg)

std::pair< unsigned, unsigned > getWavesPerEU() const

unsigned getMaxNumWorkGroupsZ() const

MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const

unsigned getNumSpilledSGPRs() const

GCNUserSGPRUsageInfo & getUserSGPRInfo()

void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))

bool hasSpilledVGPRs() const

void setFlag(Register Reg, uint8_t Flag)

void setVGPRToAGPRSpillDead(int FrameIndex)

unsigned getMaxFlatWorkGroupSize() const

std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const

bool isStackRealigned() const

Returns the physical register reserved for use as the resource descriptor for scratch accesses.

unsigned getMaxWavesPerEU() const

void setStackPtrOffsetReg(Register Reg)

Increment user SGPRs used for padding the argument list only.

ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const

ArrayRef< Register > getSGPRSpillPhysVGPRs() const

int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)

bool hasWorkGroupIDZ() const

ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const

unsigned getMaxMemoryClusterDWords() const

SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default

SmallVector< unsigned > getMaxNumWorkGroups() const

void clearNonWWMRegAllocMask()

bool hasPrologEpilogSGPRSpillEntry(Register Reg) const

bool hasWorkGroupIDY() const

void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)

bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)

Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.

void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const

void setBytesInStackArgArea(unsigned Bytes)

SIModeRegisterDefaults getMode() const

void setFrameOffsetReg(Register Reg)

ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const

std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const

bool hasWorkGroupInfo() const

bool mayUseAGPRs(const Function &F) const

bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const

bool hasWorkItemIDY() const

unsigned getMinFlatWorkGroupSize() const

const GCNUserSGPRUsageInfo & getUserSGPRInfo() const

bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)

void setPrivateSegmentWaveByteOffset(Register Reg)

unsigned getMinWavesPerEU() const

void setLongBranchReservedReg(Register Reg)

bool hasWorkGroupIDX() const

const AMDGPUFunctionArgInfo & getArgInfo() const

unsigned getMaxNumWorkGroupsX() const

unsigned getBytesInStackArgArea() const

void setHasSpilledVGPRs(bool Spill=true)

void setIfReturnsVoid(bool Value)

void limitOccupancy(unsigned Limit)

bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)

If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.

BitVector getNonWWMRegMask() const

void markPSInputAllocated(unsigned Index)

void setWorkItemIDX(ArgDescriptor Arg)

bool isWWMReg(Register Reg) const

MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override

Make a functionally equivalent copy of this MachineFunctionInfo in MF.

bool checkFlag(Register Reg, uint8_t Flag) const

void markPSInputEnabled(unsigned Index)

void addToSpilledVGPRs(unsigned num)

MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const

uint32_t get32BitAddressHighBits() const

unsigned getMinAllowedOccupancy() const

void setHasSpilledSGPRs(bool Spill=true)

bool checkIndexInPrologEpilogSGPRSpills(int FI) const

void updateNonWWMRegMask(BitVector &RegMask)

unsigned getNumKernargPreloadedSGPRs() const

bool hasWorkItemIDX() const

unsigned getNumUserSGPRs() const

const ReservedRegSet & getWWMReservedRegs() const

std::optional< int > getOptionalScavengeFI() const

AMDGPUFunctionArgInfo & getArgInfo()

const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const

void setHasNonSpillStackObjects(bool StackObject=true)

void setIsStackRealigned(bool Realigned=true)

unsigned getGITPtrHigh() const

void limitOccupancy(const MachineFunction &MF)

bool hasSpilledSGPRs() const

ArrayRef< Register > getSGPRSpillVGPRs() const

unsigned getPSInputAddr() const

SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)

void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)

bool hasImplicitArgPtr() const

bool mayNeedAGPRs() const

bool hasWorkItemIDZ() const

unsigned getMaxNumWorkGroupsY() const

unsigned getPSInputEnable() const

void setScratchRSrcReg(Register Reg)

void addToSpilledSGPRs(unsigned num)

const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)

void reserveWWMRegister(Register Reg)

bool hasPrivateSegmentWaveByteOffset() const

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

bool insert(const value_type &X)

Insert a new element into the SetVector.

bool contains(const key_type &key) const

Check if the SetVector contains the given key.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

iterator insert(iterator I, T &&Elt)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StackOffset holds a fixed and a scalable offset in bytes.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

This is an optimization pass for GlobalISel generic memory operations.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

auto upper_bound(R &&Range, T &&Value)

Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...

bool is_sorted(R &&Range, Compare C)

Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...

constexpr unsigned DefaultMemoryClusterDWordsLimit

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

This struct is a compact representation of a valid (non-zero power of two) alignment.

static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)

Helper struct shared between Function Specialization and SCCP Solver.

@ PreserveSign

The sign of a flushed-to-zero number is preserved in the sign of 0.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

SmallVector< MCPhysReg, 32 > Lanes

Function object to check whether the first component of a container supported by std::get (like std::...

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.

static void mapping(IO &YamlIO, SIArgumentInfo &AI)

static void mapping(IO &YamlIO, SIArgument &A)

static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)

static void mapping(IO &YamlIO, SIMode &Mode)

std::optional< SIArgument > PrivateSegmentWaveByteOffset

std::optional< SIArgument > WorkGroupIDY

std::optional< SIArgument > FlatScratchInit

std::optional< SIArgument > DispatchPtr

std::optional< SIArgument > DispatchID

std::optional< SIArgument > WorkItemIDY

std::optional< SIArgument > WorkGroupIDX

std::optional< SIArgument > ImplicitArgPtr

std::optional< SIArgument > QueuePtr

std::optional< SIArgument > WorkGroupInfo

std::optional< SIArgument > LDSKernelId

std::optional< SIArgument > ImplicitBufferPtr

std::optional< SIArgument > WorkItemIDX

std::optional< SIArgument > KernargSegmentPtr

std::optional< SIArgument > WorkItemIDZ

std::optional< SIArgument > PrivateSegmentSize

std::optional< SIArgument > PrivateSegmentBuffer

std::optional< SIArgument > WorkGroupIDZ

std::optional< unsigned > Mask

SIArgument(const SIArgument &Other)

SIArgument & operator=(const SIArgument &Other)

static SIArgument createArgument(bool IsReg)

unsigned MaxMemoryClusterDWords

StringValue SGPRForEXECCopy

SmallVector< StringValue > WWMReservedRegs

uint32_t HighBitsOf32BitAddress

SIMachineFunctionInfo()=default

StringValue FrameOffsetReg

StringValue LongBranchReservedReg

uint64_t ExplicitKernArgSize

void mappingImpl(yaml::IO &YamlIO) override

~SIMachineFunctionInfo()=default

StringValue VGPRForAGPRCopy

std::optional< SIArgumentInfo > ArgInfo

SmallVector< StringValue, 2 > SpillPhysVGPRS

std::optional< FrameIndex > ScavengeFI

unsigned BytesInStackArgArea

StringValue ScratchRSrcReg

StringValue StackPtrOffsetReg

SIMode(const SIModeRegisterDefaults &Mode)

bool FP64FP16OutputDenormals

bool FP64FP16InputDenormals

A wrapper around std::string which contains a source range that's being set during parsing.