SIPreAllocateWWMRegs.cpp Source File (original) (raw)

28using namespace llvm;

30#define DEBUG_TYPE "si-pre-allocate-wwm-regs"

36namespace {

38class SIPreAllocateWWMRegs {

39private:

48 std::vector RegsToRewrite;

49#ifndef NDEBUG

51#endif

55public:

59 bool run(MachineFunction &MF);

60};

63public:

64 static char ID;

66 SIPreAllocateWWMRegsLegacy() : MachineFunctionPass(ID) {}

68 bool runOnMachineFunction(MachineFunction &MF) override;

70 void getAnalysisUsage(AnalysisUsage &AU) const override {

71 AU.addRequired();

72 AU.addRequired();

73 AU.addRequired();

76 }

77};

79}

82 "SI Pre-allocate WWM Registers", false, false)

87 "SI Pre-allocate WWM Registers", false, false)

89char SIPreAllocateWWMRegsLegacy::ID = 0;

94 return new SIPreAllocateWWMRegsLegacy();

95}

97bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) {

99 if (Reg.isPhysical())

100 return false;

101

103 return false;

104

106 return false;

107

109

111 if ( MRI ->isPhysRegUsed(PhysReg, true) &&

113 Matrix->assign(LI, PhysReg);

114 assert(PhysReg != 0);

115 RegsToRewrite.push_back(Reg);

116 return true;

117 }

118 }

119

121}

122

123void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) {

124 for (MachineBasicBlock &MBB : MF) {

125 for (MachineInstr &MI : MBB) {

126 for (MachineOperand &MO : MI.operands()) {

128 continue;

129

132 continue;

133

135 continue;

136

137 if (!VRM->hasPhys(VirtReg))

138 continue;

139

143 PhysReg = TRI->getSubReg(PhysReg, SubReg);

145 }

146

149 }

150 }

151 }

152

153 SIMachineFunctionInfo *MFI = MF.getInfo();

154

155 for (unsigned Reg : RegsToRewrite) {

157

159 assert(PhysReg != 0);

160

162 }

163

164 RegsToRewrite.clear();

165

166

167 MRI->freezeReservedRegs();

168}

169

170#ifndef NDEBUG

172SIPreAllocateWWMRegs::printWWMInfo(const MachineInstr &MI) {

173

174 unsigned Opc = MI.getOpcode();

175

176 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM) {

177 dbgs() << "Entering ";

178 } else {

179 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM);

180 dbgs() << "Exiting ";

181 }

182

183 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) {

184 dbgs() << "Strict WWM ";

185 } else {

186 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM);

187 dbgs() << "Strict WQM ";

188 }

189

190 dbgs() << "region: " << MI;

191}

192

193#endif

194

195bool SIPreAllocateWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) {

196 auto *LIS = &getAnalysis().getLIS();

197 auto *Matrix = &getAnalysis().getLRM();

198 auto *VRM = &getAnalysis().getVRM();

199 return SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF);

200}

201

202bool SIPreAllocateWWMRegs::run(MachineFunction &MF) {

204

205 const GCNSubtarget &ST = MF.getSubtarget();

206

207 TII = ST.getInstrInfo();

210

212

213 bool PreallocateSGPRSpillVGPRs =

216

217 bool RegsAssigned = false;

218

219

220

221

222

223

224 ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);

225

226 for (MachineBasicBlock *MBB : RPOT) {

227 bool InWWM = false;

228 for (MachineInstr &MI : *MBB) {

229 if (MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR) {

230 if (PreallocateSGPRSpillVGPRs)

231 RegsAssigned |= processDef(MI.getOperand(0));

232 continue;

233 }

234

235 if (MI.getOpcode() == AMDGPU::ENTER_STRICT_WWM ||

236 MI.getOpcode() == AMDGPU::ENTER_STRICT_WQM) {

238 InWWM = true;

239 continue;

240 }

241

242 if (MI.getOpcode() == AMDGPU::EXIT_STRICT_WWM ||

243 MI.getOpcode() == AMDGPU::EXIT_STRICT_WQM) {

245 InWWM = false;

246 }

247

248 if (!InWWM)

249 continue;

250

252

253 for (MachineOperand &DefOpnd : MI.defs()) {

254 RegsAssigned |= processDef(DefOpnd);

255 }

256 }

257 }

258

259 if (!RegsAssigned)

260 return false;

261

262 rewriteRegs(MF);

263 return true;

264}

265

266PreservedAnalyses

272 SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF);

274}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

Provides AMDGPU specific target descriptions.

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

AMD GCN specific subclass of TargetSubtarget.

Promote Memory to Register

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.

static cl::opt< bool > EnablePreallocateSGPRSpillVGPRs("amdgpu-prealloc-sgpr-spill-vgprs", cl::init(false), cl::Hidden)

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

AnalysisUsage & addRequired()

void setPreservesAll()

Set by analyses that do not transform their input at all.

FunctionPass class - This class is used to implement most global optimizations.

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

LiveInterval - This class represents the liveness of a register, or stack slot.

LiveInterval & getInterval(Register Reg)

void removeInterval(Register Reg)

Interval removal.

@ IK_Free

No interference, go ahead and assign.

Wrapper class representing physical registers. Should be passed by value.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

LLVM_ABI void setIsRenamable(bool Val=true)

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

LLVM_ABI void runOnMachineFunction(const MachineFunction &MF, bool Rev=false)

runOnFunction - Prepare to answer questions about MF.

ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const

getOrder - Returns the preferred allocation order for RC.

Wrapper class representing virtual and physical registers.

constexpr bool isValid() const

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

void reserveWWMRegister(Register Reg)

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition SIPreAllocateWWMRegs.cpp:267

const TargetRegisterInfo & getRegisterInfo() const

LLVM_ABI VirtRegMap run(MachineFunction &MF, MachineFunctionAnalysisManager &MAM)

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

bool hasPhys(Register virtReg) const

returns true if the specified virtual register is mapped to a physical register

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

This is an optimization pass for GlobalISel generic memory operations.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionPass * createSIPreAllocateWWMRegsLegacyPass()

Definition SIPreAllocateWWMRegs.cpp:93

char & SIPreAllocateWWMRegsLegacyID

Definition SIPreAllocateWWMRegs.cpp:91