SIRegisterInfo.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H

15#define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H

19#define GET_REGINFO_HEADER

20#include "AMDGPUGenRegisterInfo.inc"

24namespace llvm {

26class GCNSubtarget;

27class LiveIntervals;

28class LiveRegUnits;

29class MachineInstrBuilder;

30class RegisterBank;

31struct SGPRSpillBuilder;

41private:

43 bool SpillSGPRToVGPR;

44 bool isWave32;

45 BitVector RegPressureIgnoredUnits;

52 static std::array<std::vector<int16_t>, 32> RegSplitParts;

57 static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;

61public:

80 return SpillSGPRToVGPR;

81 }

86 const unsigned Align,

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144 int Idx) const override;

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149 int64_t Offset) const override;

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152 int64_t Offset) const override;

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155 int64_t Offset) const override;

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169 return &AMDGPU::VReg_1024RegClass;

170 }

171

173 bool IsLoad, bool IsKill = true) const;

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179 bool OnlyToVGPR = false,

180 bool SpillToPhysVGPRLane = false) const;

181

184 bool OnlyToVGPR = false,

185 bool SpillToPhysVGPRLane = false) const;

186

190

192 unsigned FIOperandNum,

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198 bool SpillToPhysVGPRLane = false) const;

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307 unsigned SubIdx) const;

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321 bool ReserveHighestVGPR = false) const;

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347 unsigned EltSize) const;

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353 unsigned Idx) const override;

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377 return isWave32 ? &AMDGPU::SReg_32RegClass

378 : &AMDGPU::SReg_64RegClass;

379 }

380

382 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass

383 : &AMDGPU::SReg_64_XEXECRegClass;

384 }

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410 uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;

411 Mask = (Even >> 1) | Mask;

412 uint64_t Odd = Mask & 0x5555555555555555ULL;

414 }

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418 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;

419 }

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452 unsigned LoadStoreOp, int Index, Register ValueReg,

453 bool ValueIsKill, MCRegister ScratchOffsetReg,

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465 unsigned AlignNumBits) const {

466 assert(AlignNumBits != 0);

468 return RCAlign == AlignNumBits ||

469 (RCAlign > AlignNumBits && (RCAlign % AlignNumBits) == 0);

470 }

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475 unsigned SubReg) const;

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482 bool IncludeCalls = true) const;

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486 : std::optional<uint8_t>{};

487 }

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492 float

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496 return AMDGPUGenRegisterInfo::getSpillWeightScaleFactor(RC) *

497 ((RC == &AMDGPU::VGPR_32_Lo256RegClass ||

498 RC == &AMDGPU::VReg_64_Lo256_Align2RegClass)

499 ? 2.0

500 : 1.0);

501 }

502};

503

504namespace AMDGPU {

505

506unsigned getRegBitWidth(const TargetRegisterClass &RC);

507}

508

509}

510

511#endif

unsigned const MachineRegisterInfo * MRI

static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file implements the BitVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

A set of register units used to track register liveness.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

A description of a memory reference used in the backend.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Holds all the information related to register banks.

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

int64_t getScratchInstrOffset(const MachineInstr *MI) const

bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override

const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const

Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...

ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const

Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.

MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const

Returns a lowest register that is not used at any point in the function.

static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)

static unsigned getNumCoveredRegs(LaneBitmask LM)

Definition SIRegisterInfo.h:406

MCPhysReg get32BitRegister(MCPhysReg Reg) const

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override

bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override

bool shouldRealignStack(const MachineFunction &MF) const override

bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const

bool isProperlyAlignedRC(const TargetRegisterClass &RC) const

static bool hasVectorRegisters(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:280

const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const

LLVM_READONLY const TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const

bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const

float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override

Definition SIRegisterInfo.h:493

SIRegisterInfo(const GCNSubtarget &ST)

const uint32_t * getAllVGPRRegMask() const

MCRegister getReturnAddressReg(const MachineFunction &MF) const

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

bool hasBasePointer(const MachineFunction &MF) const

const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override

Returns a legal register class to copy a register in the specified class to or from.

ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const

ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const

Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.

const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override

MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const

Special case of eliminateFrameIndex.

bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const

void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr) const

const TargetRegisterClass * getRegClassForBlockOp(const MachineFunction &MF) const

Definition SIRegisterInfo.h:168

bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override

LLVM_READONLY const TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const

static bool isChainScratchRegister(Register VGPR)

bool requiresRegisterScavenging(const MachineFunction &Fn) const override

bool opCanUseInlineConstant(unsigned OpType) const

const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const

const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override

bool isVGPRPhysReg(Register Reg) const

Definition SIRegisterInfo.h:240

bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override

const uint32_t * getNoPreservedMask() const override

StringRef getRegAsmName(MCRegister Reg) const override

const uint32_t * getAllAllocatableSRegMask() const

bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const

Definition SIRegisterInfo.h:331

MCRegister getAlignedHighSGPRForRC(const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const

Return the largest available SGPR aligned to Align for the register class RC.

const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const

unsigned getHWRegIndex(MCRegister Reg) const

const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const

const uint32_t * getAllVectorRegMask() const

const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const

static LLVM_READONLY const TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)

const TargetRegisterClass * getPointerRegClass(unsigned Kind=0) const override

const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const

Definition SIRegisterInfo.h:368

bool opCanUseLiteralConstant(unsigned OpType) const

bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override

LLVM_READONLY const TargetRegisterClass * getAlignedLo256VGPRClassForBitWidth(unsigned BitWidth) const

LLVM_READONLY const TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const

const TargetRegisterClass * getEquivalentAVClass(const TargetRegisterClass *SRC) const

bool requiresFrameIndexScavenging(const MachineFunction &MF) const override

static bool hasVGPRs(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:265

static bool isVGPRClass(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:245

MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const

bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const

const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const

SmallVector< StringLiteral > getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override

unsigned getNumChannelsFromSubReg(unsigned SubReg) const

Definition SIRegisterInfo.h:422

LLVM_READONLY const TargetRegisterClass * getDefaultVectorSuperClassForBitWidth(unsigned BitWidth) const

unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override

ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.

unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override

unsigned getCSRFirstUseCost() const override

Definition SIRegisterInfo.h:110

BitVector getReservedRegs(const MachineFunction &MF) const override

bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override

const TargetRegisterClass * getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const

void addImplicitUsesForBlockCSRLoad(MachineInstrBuilder &MIB, Register BlockReg) const

bool isSGPRClassID(unsigned RCID) const

Definition SIRegisterInfo.h:231

unsigned getNumUsedPhysRegs(const MachineRegisterInfo &MRI, const TargetRegisterClass &RC, bool IncludeCalls=true) const

const uint32_t * getAllAGPRRegMask() const

const int * getRegUnitPressureSets(MCRegUnit RegUnit) const override

bool isDivergentRegClass(const TargetRegisterClass *RC) const override

Definition SIRegisterInfo.h:339

const TargetRegisterClass * getBoolRC() const

Definition SIRegisterInfo.h:376

bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const

bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override

bool isVSSuperClass(const TargetRegisterClass *RC) const

Definition SIRegisterInfo.h:260

bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const

If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.

unsigned getChannelFromSubReg(unsigned SubReg) const

Definition SIRegisterInfo.h:417

MCRegister getExec() const

bool isSGPRPhysReg(Register Reg) const

Definition SIRegisterInfo.h:236

std::optional< uint8_t > getVRegFlagValue(StringRef Name) const override

Definition SIRegisterInfo.h:484

MCRegister getVCC() const

int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override

bool isVectorSuperClass(const TargetRegisterClass *RC) const

Definition SIRegisterInfo.h:255

bool isRegClassAligned(const TargetRegisterClass *RC, unsigned AlignNumBits) const

Definition SIRegisterInfo.h:464

static bool hasAGPRs(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:270

const TargetRegisterClass * getWaveMaskRegClass() const

Definition SIRegisterInfo.h:381

unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const

static bool hasSGPRs(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:275

void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override

bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override

bool spillSGPRToVGPR() const

Definition SIRegisterInfo.h:79

const TargetRegisterClass * getVGPR64Class() const

void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const

unsigned getRegClassAlignmentNumBits(const TargetRegisterClass *RC) const

Definition SIRegisterInfo.h:459

static bool isSGPRClass(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:226

static bool isAGPRClass(const TargetRegisterClass *RC)

Definition SIRegisterInfo.h:250

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

const uint8_t TSFlags

Configurable target specific flags.

A Use represents the edge between a Value definition and its users.

Definition SIRegisterInfo.h:34

@ Size16

Definition SIRegisterInfo.h:36

@ Size32

Definition SIRegisterInfo.h:36

unsigned getRegBitWidth(const TargetRegisterClass &RC)

Get the size in bits of a register from the register class RC.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

constexpr int popcount(T Value) noexcept

Count the number of set bits in a value.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

constexpr unsigned BitWidth

This struct is a compact representation of a valid (non-zero power of two) alignment.

constexpr Type getAsInteger() const

Definition SIRegisterInfo.h:65

bool hasLane()

Definition SIRegisterInfo.h:71

int Lane

Definition SIRegisterInfo.h:66

bool hasReg()

Definition SIRegisterInfo.h:72

SpilledReg(Register R, int L)

Definition SIRegisterInfo.h:69