SPIRVGlobalRegistry.cpp Source File (original) (raw)

28#include "llvm/IR/IntrinsicsSPIRV.h"

32#include

33#include

35using namespace llvm;

39 return false;

41 return false;

43 if (LI->getType()->isAggregateType())

44 return false;

45 return true;

46}

50 return PType->getAddressSpace();

52 return PType->getAddressSpace();

55 return ExtTy->getIntParameter(0);

57}

59static bool

61 switch (SC) {

62 case SPIRV::StorageClass::Uniform:

63 case SPIRV::StorageClass::PushConstant:

64 case SPIRV::StorageClass::StorageBuffer:

65 case SPIRV::StorageClass::PhysicalStorageBufferEXT:

66 return true;

67 case SPIRV::StorageClass::UniformConstant:

68 case SPIRV::StorageClass::Input:

69 case SPIRV::StorageClass::Output:

70 case SPIRV::StorageClass::Workgroup:

71 case SPIRV::StorageClass::CrossWorkgroup:

72 case SPIRV::StorageClass::Private:

73 case SPIRV::StorageClass::Function:

74 case SPIRV::StorageClass::Generic:

75 case SPIRV::StorageClass::AtomicCounter:

76 case SPIRV::StorageClass::Image:

77 case SPIRV::StorageClass::CallableDataNV:

78 case SPIRV::StorageClass::IncomingCallableDataNV:

79 case SPIRV::StorageClass::RayPayloadNV:

80 case SPIRV::StorageClass::HitAttributeNV:

81 case SPIRV::StorageClass::IncomingRayPayloadNV:

82 case SPIRV::StorageClass::ShaderRecordBufferNV:

83 case SPIRV::StorageClass::CodeSectionINTEL:

84 case SPIRV::StorageClass::DeviceOnlyINTEL:

85 case SPIRV::StorageClass::HostOnlyINTEL:

86 return false;

87 }

89}

92 : PointerSize(PointerSize), Bound(0), CurMF(nullptr) {}

100 return SpirvType;

101}

102

109 return SpirvType;

110}

111

118 return SpirvType;

119}

120

123 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {

127 return SpirvType;

128}

129

133 VRegToTypeMap[&MF][VReg] = SpirvType;

134}

135

137 auto Res = MRI.createGenericVirtualRegister(LLT::scalar(64));

138 MRI.setRegClass(Res, &SPIRV::TYPERegClass);

139 return Res;

140}

141

145

147 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

148 return MIRBuilder.buildInstr(SPIRV::OpTypeBool)

150 });

151}

152

153unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {

154 if (Width > 64)

157 if (ST.canUseExtension(

158 SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||

159 ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4))

160 return Width;

161 if (Width <= 8)

162 Width = 8;

163 else if (Width <= 16)

164 Width = 16;

165 else if (Width <= 32)

166 Width = 32;

167 else

168 Width = 64;

169 return Width;

170}

171

172SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,

174 bool IsSigned) {

175 Width = adjustOpTypeIntWidth(Width);

176 const SPIRVSubtarget &ST =

178 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

179 if (Width == 4 && ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4)) {

180 MIRBuilder.buildInstr(SPIRV::OpExtension)

181 .addImm(SPIRV::Extension::SPV_INTEL_int4);

182 MIRBuilder.buildInstr(SPIRV::OpCapability)

183 .addImm(SPIRV::Capability::Int4TypeINTEL);

184 } else if (( $isPowerOf2\_32$ (Width) || Width < 8) &&

185 ST.canUseExtension(

186 SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers)) {

187 MIRBuilder.buildInstr(SPIRV::OpExtension)

188 .addImm(SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers);

189 MIRBuilder.buildInstr(SPIRV::OpCapability)

190 .addImm(SPIRV::Capability::ArbitraryPrecisionIntegersALTERA);

191 }

192 return MIRBuilder.buildInstr(SPIRV::OpTypeInt)

195 .addImm(IsSigned ? 1 : 0);

196 });

197}

198

199SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,

201 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

202 return MIRBuilder.buildInstr(SPIRV::OpTypeFloat)

205 });

206}

207

209SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,

211 SPIRV::FPEncoding::FPEncoding FPEncode) {

212 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

213 return MIRBuilder.buildInstr(SPIRV::OpTypeFloat)

217 });

218}

219

221 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

222 return MIRBuilder.buildInstr(SPIRV::OpTypeVoid)

224 });

225}

226

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

247 "Cannot invalidate aliasing instructions.");

248 assert(MI->getOpcode() != SPIRV::OpFunction &&

249 "Cannot invalidate OpFunction.");

250

251 if (MI->getOpcode() == SPIRV::OpFunctionCall) {

253 auto It = ForwardCalls.find(F);

254 if (It != ForwardCalls.end()) {

255 It->second.erase(MI);

256 if (It->second.empty())

257 ForwardCalls.erase(It);

258 }

259 }

260 }

261

263 auto It = LastInsertedTypeMap.find(MF);

264 if (It != LastInsertedTypeMap.end() && It->second == MI)

265 LastInsertedTypeMap.erase(MF);

266

268}

269

270SPIRVType *SPIRVGlobalRegistry::createOpType(

273 auto oldInsertPoint = MIRBuilder.getInsertPt();

276

277 auto LastInsertedType = LastInsertedTypeMap.find(CurMF);

278 if (LastInsertedType != LastInsertedTypeMap.end()) {

279 auto It = LastInsertedType->second->getIterator();

280

281

283 if (It->getParent() != NewMBB)

284 InsertAt = oldInsertPoint->getParent() == NewMBB

285 ? oldInsertPoint

287 else if (It->getNextNode())

288 InsertAt = It->getNextNode()->getIterator();

289 else

291 MIRBuilder.setInsertPt(*NewMBB, InsertAt);

292 } else {

294 auto Result = LastInsertedTypeMap.try_emplace(CurMF, nullptr);

295 assert(Result.second);

296 LastInsertedType = Result.first;

297 }

298

299 MachineInstr *Type = Op(MIRBuilder);

300

301

303 LastInsertedType->second = Type;

304

305 MIRBuilder.setInsertPt(*OldMBB, oldInsertPoint);

307}

308

309SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,

312 auto EleOpc = ElemType->getOpcode();

313 (void)EleOpc;

314 assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||

315 EleOpc == SPIRV::OpTypeBool) &&

316 "Invalid vector element type");

317

318 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

319 return MIRBuilder.buildInstr(SPIRV::OpTypeVector)

323 });

324}

325

329 bool ZeroAsNull) {

331 auto *const CF = ConstantFP::get(Ctx, Val);

333 if (MI && (MI->getOpcode() == SPIRV::OpConstantNull ||

334 MI->getOpcode() == SPIRV::OpConstantF))

335 return MI->getOperand(0).getReg();

337}

338

342 bool ZeroAsNull) {

345 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);

346 CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);

348

354

356 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)

359 } else {

360 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantF)

365 MIB);

366 }

367 const auto &ST = CurMF->getSubtarget();

369 *ST.getRegisterInfo(),

370 *ST.getRegBankInfo());

371 return MIB;

372 });

373 add(CF, NewType);

374 return Res;

375}

376

380 bool ZeroAsNull) {

382 auto *const CI = ConstantInt::get(const_cast<IntegerType *>(Ty), Val);

384 if (MI && (MI->getOpcode() == SPIRV::OpConstantNull ||

385 MI->getOpcode() == SPIRV::OpConstantI))

386 return MI->getOperand(0).getReg();

388}

389

394 bool ZeroAsNull) {

397 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);

398 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);

400

407 MIB = MIRBuilder

409 : SPIRV::OpConstantTrue)

412 } else if (!CI->isZero() || !ZeroAsNull) {

413 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)

417 } else {

418 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)

421 }

422 const auto &ST = CurMF->getSubtarget();

424 *ST.getRegisterInfo(),

425 *ST.getRegBankInfo());

426 return MIB;

427 });

428 add(CI, NewType);

429 return Res;

430}

431

435 bool ZeroAsNull) {

437 auto &MF = MIRBuilder.getMF();

439 auto *const CI = ConstantInt::get(const_cast<IntegerType *>(Ty), Val);

442 return Res;

443

447 Res = MRI.createGenericVirtualRegister(LLTy);

448 MRI.setRegClass(Res, &SPIRV::iIDRegClass);

449 assignTypeToVReg(Ty, Res, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,

450 EmitIR);

451

454 if (EmitIR)

458 if (Val || !ZeroAsNull) {

459 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)

463 } else {

464 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)

467 }

468 const auto &Subtarget = CurMF->getSubtarget();

470 *Subtarget.getRegisterInfo(),

471 *Subtarget.getRegBankInfo());

472 return MIB;

473 });

474 add(CI, NewType);

475 return Res;

476}

477

481 auto &MF = MIRBuilder.getMF();

482 LLVMContext &Ctx = MF.getFunction().getContext();

483 if (!SpvType)

485 SPIRV::AccessQualifier::ReadWrite, true);

486 auto *const CF = ConstantFP::get(Ctx, Val);

489 return Res;

490

492 Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);

493 MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);

495

499 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantF)

502 addNumImm(CF->getValueAPF().bitcastToAPInt(), MIB);

503 return MIB;

504 });

505 add(CF, NewType);

506 return Res;

507}

508

509Register SPIRVGlobalRegistry::getOrCreateBaseRegister(

513 if (SpvType->getOpcode() == SPIRV::OpTypeVector ||

514 SpvType->getOpcode() == SPIRV::OpTypeArray) {

517 }

518 if (Type->getOpcode() == SPIRV::OpTypeFloat) {

521 TII, ZeroAsNull);

522 }

523 assert(Type->getOpcode() == SPIRV::OpTypeInt);

526 SpvBaseType, TII, ZeroAsNull);

527}

528

529Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(

532 unsigned ElemCnt, bool ZeroAsNull) {

534 return R;

535

536 bool IsNull = Val->isNullValue() && ZeroAsNull;

538 if (!IsNull)

539 ElemReg =

540 getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);

541

543 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);

546

547 MachineInstr *DepMI = const_cast<MachineInstr *>(SpvType);

549 const MachineInstr *NewMI =

550 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

551 MachineInstrBuilder MIB;

552 if (!IsNull) {

553 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantComposite)

556 for (unsigned i = 0; i < ElemCnt; ++i)

558 } else {

559 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)

562 }

563 const auto &Subtarget = CurMF->getSubtarget();

565 *Subtarget.getRegisterInfo(),

566 *Subtarget.getRegBankInfo());

567 return MIB;

568 });

569 add(CA, NewMI);

570 return Res;

571}

572

577 bool ZeroAsNull) {

583 auto *ConstVal = ConstantInt::get(LLVMBaseTy, Val);

584 auto *ConstVec =

587 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW,

589 ZeroAsNull);

590}

591

596 bool ZeroAsNull) {

602 auto *ConstVal = ConstantFP::get(LLVMBaseTy, Val);

603 auto *ConstVec =

606 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW,

608 ZeroAsNull);

609}

610

618 Constant *CI = ConstantInt::get(LLVMBaseTy, Val);

621

622

623

624

625

626

627

628

631 ConstantInt::get(LLVMBaseTy, Val), ConstantInt::get(LLVMBaseTy, Num)});

632 return getOrCreateCompositeOrNull(CI, I, SpvType, TII, UniqueKey, BW,

634}

635

636Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(

640 return R;

641

643 if (Val || EmitIR) {

645 ElemReg = buildConstantInt(Val, MIRBuilder, SpvBaseType, EmitIR);

646 }

649 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);

651

654 if (EmitIR)

656

657 if (Val) {

658 auto MIB = MIRBuilder.buildInstr(SPIRV::OpConstantComposite)

661 for (unsigned i = 0; i < ElemCnt; ++i)

663 return MIB;

664 }

665

666 return MIRBuilder.buildInstr(SPIRV::OpConstantNull)

669 });

670 add(CA, NewMI);

671 return Res;

672}

673

677 SPIRVType *SpvType, bool EmitIR) {

682 const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val);

683 auto ConstVec =

686 return getOrCreateIntCompositeOrNull(Val, MIRBuilder, SpvType, EmitIR,

687 ConstVec, BW,

689}

690

702 return Res;

703

705 Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);

706 CurMF->getRegInfo().setRegClass(Res, &SPIRV::pIDRegClass);

708

711 return MIRBuilder.buildInstr(SPIRV::OpConstantNull)

714 });

715 add(CP, NewMI);

716 return Res;

717}

718

721 unsigned Param, unsigned FilerMode,

723 auto Sampler =

725 ? ResReg

729

730

731

732

733

734 MIRBuilder.buildInstr(SPIRV::OpConstantSampler)

736 .addUse(TypeSamplerReg)

740 return Sampler;

741}

742

745 const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage,

747 const std::optionalSPIRV::LinkageType::LinkageType &LinkageType,

750 if (GV) {

752 } else {

753

754

756 GVar = M->getGlobalVariable(Name);

757 if (GVar == nullptr) {

759

763 }

764 GV = GVar;

765 }

766

769 if (Reg.isValid()) {

770 if (Reg != ResVReg)

771 MIRBuilder.buildCopy(ResVReg, Reg);

772 return ResVReg;

773 }

774

775 auto MIB = MIRBuilder.buildInstr(SPIRV::OpVariable)

780 MIB.addUse(Init->getOperand(0).getReg());

781

782

783 if (IsInstSelector) {

784 const auto &Subtarget = CurMF->getSubtarget();

786 *Subtarget.getRegisterInfo(),

787 *Subtarget.getRegBankInfo());

788 }

789 add(GVar, MIB);

790

793

794

796 if (Reg != ResVReg) {

797 LLT RegLLTy =

799 MRI->setType(Reg, RegLLTy);

801 } else {

802

803

804

806 if (!DefType || DefType != BaseType)

808 }

809

810

811 if (GVar && GVar->hasName())

813

814

815

818 if (IsConst && !ST.isShader())

819 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Constant, {});

820

823 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Alignment, {Alignment});

824 }

825

826 if (LinkageType)

827 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,

828 {static_cast<uint32_t>(*LinkageType)}, Name);

829

830 SPIRV::BuiltIn::BuiltIn BuiltInId;

832 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::BuiltIn,

833 {static_cast<uint32_t>(BuiltInId)});

834

835

836

837

838 MDNode *GVarMD = nullptr;

839 if (GVar && (GVarMD = GVar->getMetadata("spirv.Decorations")) != nullptr)

841

842 return Reg;

843}

844

845

846

847

853

856 std::nullopt, MIRBuilder, false);

857

858 buildOpDecorate(VarReg, MIRBuilder, SPIRV::Decoration::DescriptorSet, {Set});

859 buildOpDecorate(VarReg, MIRBuilder, SPIRV::Decoration::Binding, {Binding});

860 return VarReg;

861}

862

863

864

868 bool ExplicitLayoutRequired,

869 bool EmitIR) {

871 "Invalid array element type");

876 if (NumElems != 0) {

878 buildConstantInt(NumElems, MIRBuilder, SpvTypeInt32, EmitIR);

880 return MIRBuilder.buildInstr(SPIRV::OpTypeArray)

883 .addUse(NumElementsVReg);

884 });

885 } else {

886 if (.isShader()) {

888 "Runtime arrays are not allowed in non-shader "

889 "SPIR-V modules");

890 return nullptr;

891 }

892 ArrayType = createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

893 return MIRBuilder.buildInstr(SPIRV::OpTypeRuntimeArray)

896 });

897 }

898

899 if (ExplicitLayoutRequired && isResourceType (ElemType)) {

901 addArrayStrideDecorations(ArrayType->defs().begin()->getReg(), ET,

902 MIRBuilder);

903 }

904

906}

907

913 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

914 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeOpaque).addDef(ResVReg);

917 return MIB;

918 });

919}

920

921SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(

923 SPIRV::AccessQualifier::AccessQualifier AccQual,

925 Type *OriginalElementType = nullptr;

926 uint64_t TotalSize = 0;

928 SPIRVType *ElementSPIRVType = findSPIRVType(

929 OriginalElementType, MIRBuilder, AccQual,

930 Decorator != nullptr, EmitIR);

931 return getOpTypeArray(TotalSize, ElementSPIRVType, MIRBuilder,

932 Decorator != nullptr,

933 EmitIR);

934 }

935

936 const SPIRVSubtarget &ST =

939 constexpr unsigned MaxWordCount = UINT16_MAX;

941

942 size_t MaxNumElements = MaxWordCount - 2;

943 size_t SPIRVStructNumElements = NumElements;

944 if (NumElements > MaxNumElements) {

945

946 SPIRVStructNumElements = MaxNumElements;

947 MaxNumElements = MaxWordCount - 1;

948 }

949

950 for (const auto &Elem : Ty->elements()) {

951 SPIRVType *ElemTy = findSPIRVType(

953 Decorator != nullptr, EmitIR);

954 assert(ElemTy && ElemTy->getOpcode() != SPIRV::OpTypeVoid &&

955 "Invalid struct element type");

957 }

961 if (Ty->isPacked() && .isShader())

962 buildOpDecorate(ResVReg, MIRBuilder, SPIRV::Decoration::CPacked, {});

963

965 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

966 auto MIBStruct =

968 for (size_t I = 0; I < SPIRVStructNumElements; ++I)

969 MIBStruct.addUse(FieldTypes[I]);

970 for (size_t I = SPIRVStructNumElements; I < NumElements;

971 I += MaxNumElements) {

972 auto MIBCont =

973 MIRBuilder.buildInstr(SPIRV::OpTypeStructContinuedINTEL);

974 for (size_t J = I; J < std::min(I + MaxNumElements, NumElements); ++J)

975 MIBCont.addUse(FieldTypes[I]);

976 }

977 return MIBStruct;

978 });

979

980 if (Decorator)

981 Decorator(SPVType->defs().begin()->getReg());

982

983 return SPVType;

984}

985

986SPIRVType *SPIRVGlobalRegistry::getOrCreateSpecialType(

988 SPIRV::AccessQualifier::AccessQualifier AccQual) {

991}

992

993SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(

994 SPIRV::StorageClass::StorageClass SC, SPIRVType *ElemType,

998

999 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1000 return MIRBuilder.buildInstr(SPIRV::OpTypePointer)

1002 .addImm(static_cast<uint32_t>(SC))

1004 });

1005}

1006

1007SPIRVType *SPIRVGlobalRegistry::getOpTypeForwardPointer(

1008 SPIRV::StorageClass::StorageClass SC, MachineIRBuilder &MIRBuilder) {

1009 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1010 return MIRBuilder.buildInstr(SPIRV::OpTypeForwardPointer)

1012 .addImm(static_cast<uint32_t>(SC));

1013 });

1014}

1015

1016SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction(

1020 if (Ty->isVarArg()) {

1022 Ty->getContext().diagnose(DiagnosticInfoUnsupported(

1023 Fn, "SPIR-V does not support variadic functions",

1025 }

1026 return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1027 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFunction)

1030 for (const SPIRVType *ArgType : ArgTypes)

1032 return MIB;

1033 });

1034}

1035

1041 return MI;

1043 getOpTypeFunction(cast(Ty), RetType, ArgTypes, MIRBuilder);

1044 add(Ty, false, NewMI);

1045 return finishCreatingSPIRVType(Ty, NewMI);

1046}

1047

1048SPIRVType *SPIRVGlobalRegistry::findSPIRVType(

1050 SPIRV::AccessQualifier::AccessQualifier AccQual,

1051 bool ExplicitLayoutRequired, bool EmitIR) {

1052 Ty = adjustIntTypeByWidth(Ty);

1053

1055 findMI(Ty, ExplicitLayoutRequired, &MIRBuilder.getMF()))

1056 return MI;

1057 if (auto It = ForwardPointerTypes.find(Ty); It != ForwardPointerTypes.end())

1058 return It->second;

1059 return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, ExplicitLayoutRequired,

1060 EmitIR);

1061}

1062

1064 assert(SpirvType && "Attempting to get type id for nullptr type.");

1065 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||

1066 SpirvType->getOpcode() == SPIRV::OpTypeStructContinuedINTEL)

1067 return SpirvType->uses().begin()->getReg();

1068 return SpirvType->defs().begin()->getReg();

1069}

1070

1071

1072

1073

1074

1075

1076

1077

1078

1079const Type *SPIRVGlobalRegistry::adjustIntTypeByWidth(const Type *Ty) const {

1081 unsigned SrcBitWidth = IType->getBitWidth();

1082 if (SrcBitWidth > 1) {

1083 unsigned BitWidth = adjustOpTypeIntWidth(SrcBitWidth);

1084

1085 if (SrcBitWidth != BitWidth)

1087 }

1088 }

1089 return Ty;

1090}

1091

1092SPIRVType *SPIRVGlobalRegistry::createSPIRVType(

1094 SPIRV::AccessQualifier::AccessQualifier AccQual,

1095 bool ExplicitLayoutRequired, bool EmitIR) {

1097 return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);

1098

1099 if (const MachineInstr *MI =

1100 findMI(Ty, ExplicitLayoutRequired, &MIRBuilder.getMF()))

1101 return MI;

1102

1104 const unsigned Width = IType->getBitWidth();

1105 return Width == 1 ? getOpTypeBool(MIRBuilder)

1106 : getOpTypeInt(Width, MIRBuilder, false);

1107 }

1111 SPIRV::FPEncoding::BFloat16KHR);

1112 } else {

1114 }

1115 }

1117 return getOpTypeVoid(MIRBuilder);

1121 AccQual, ExplicitLayoutRequired, EmitIR);

1123 MIRBuilder);

1124 }

1127 AccQual, ExplicitLayoutRequired, EmitIR);

1129 ExplicitLayoutRequired, EmitIR);

1130 }

1132 if (SType->isOpaque())

1133 return getOpTypeOpaque(SType, MIRBuilder);

1134

1136 if (ExplicitLayoutRequired) {

1137 Decorator = [&MIRBuilder, SType, this](Register Reg) {

1138 addStructOffsetDecorations(Reg, const_cast<StructType *>(SType),

1139 MIRBuilder);

1140 };

1141 }

1142 return getOpTypeStruct(SType, MIRBuilder, AccQual, std::move(Decorator),

1143 EmitIR);

1144 }

1146 SPIRVType *RetTy = findSPIRVType(FType->getReturnType(), MIRBuilder,

1147 AccQual, ExplicitLayoutRequired, EmitIR);

1149 for (const auto &ParamTy : FType->params())

1150 ParamTypes.push_back(findSPIRVType(ParamTy, MIRBuilder, AccQual,

1151 ExplicitLayoutRequired, EmitIR));

1152 return getOpTypeFunction(FType, RetTy, ParamTypes, MIRBuilder);

1153 }

1154

1156 SPIRVType *SpvElementType = nullptr;

1159 else

1161

1162

1163 const SPIRVSubtarget *ST =

1164 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());

1166

1168 if (!ElemTy) {

1170 }

1171

1172

1173

1174 if (auto It = ForwardPointerTypes.find(Ty); It != ForwardPointerTypes.end()) {

1176

1177 return getOpTypePointer(SC, SpvElementType, MIRBuilder, Reg);

1178 }

1179

1181}

1182

1183SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(

1185 SPIRV::AccessQualifier::AccessQualifier AccessQual,

1186 bool ExplicitLayoutRequired, bool EmitIR) {

1187

1188

1190 return nullptr;

1191 TypesInProcessing.insert(Ty);

1192 SPIRVType *SpirvType = createSPIRVType(Ty, MIRBuilder, AccessQual,

1193 ExplicitLayoutRequired, EmitIR);

1194 TypesInProcessing.erase(Ty);

1195 VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;

1196

1197

1198

1199 SPIRVToLLVMType[SpirvType] = unifyPtrType(Ty);

1200

1201 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||

1203 return SpirvType;

1204

1207 add(ExtTy->getTypeParameter(0), ExtTy->getIntParameter(0), SpirvType);

1209 add(Ty, ExplicitLayoutRequired, SpirvType);

1213 else

1216 return SpirvType;

1217}

1218

1222 auto t = VRegToTypeMap.find(MF ? MF : CurMF);

1223 if (t != VRegToTypeMap.end()) {

1224 auto tt = t->second.find(VReg);

1225 if (tt != t->second.end())

1226 return tt->second;

1227 }

1228 return nullptr;

1229}

1230

1238

1241 SPIRV::AccessQualifier::AccessQualifier AccessQual,

1242 bool ExplicitLayoutRequired, bool EmitIR) {

1247 Reg = find(ExtTy->getTypeParameter(0), ExtTy->getIntParameter(0), MF);

1249 Reg = find(Ty = adjustIntTypeByWidth(Ty), ExplicitLayoutRequired, MF);

1253 else

1258

1259 TypesInProcessing.clear();

1260 SPIRVType *STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual,

1261 ExplicitLayoutRequired, EmitIR);

1262

1263 for (auto &CU : ForwardPointerTypes) {

1264

1265

1266 bool PtrNeedsLayout = false;

1267 const Type *Ty2 = CU.first;

1269 if ((Reg = find(Ty2, PtrNeedsLayout, MF)).isValid())

1271 else

1272 STy2 = restOfCreateSPIRVType(Ty2, MIRBuilder, AccessQual, PtrNeedsLayout,

1273 EmitIR);

1274 if (Ty == Ty2)

1275 STy = STy2;

1276 }

1277 ForwardPointerTypes.clear();

1278 return STy;

1279}

1280

1282 unsigned TypeOpcode) const {

1284 assert(Type && "isScalarOfType VReg has no type assigned");

1285 return Type->getOpcode() == TypeOpcode;

1286}

1287

1289 unsigned TypeOpcode) const {

1291 assert(Type && "isScalarOrVectorOfType VReg has no type assigned");

1292 if (Type->getOpcode() == TypeOpcode)

1293 return true;

1294 if (Type->getOpcode() == SPIRV::OpTypeVector) {

1295 Register ScalarTypeVReg = Type->getOperand(1).getReg();

1297 return ScalarType->getOpcode() == TypeOpcode;

1298 }

1299 return false;

1300}

1301

1303 switch (Type->getOpcode()) {

1304 case SPIRV::OpTypeImage:

1305 case SPIRV::OpTypeSampler:

1306 case SPIRV::OpTypeSampledImage:

1307 return true;

1308 case SPIRV::OpTypeStruct:

1309 return hasBlockDecoration(Type);

1310 default:

1311 return false;

1312 }

1313 return false;

1314}

1315unsigned

1319

1320unsigned

1323 return 0;

1324 return Type->getOpcode() == SPIRV::OpTypeVector

1325 ? static_cast<unsigned>(Type->getOperand(2).getImm())

1326 : 1;

1327}

1328

1333

1337 return nullptr;

1338 Register ScalarReg = Type->getOpcode() == SPIRV::OpTypeVector

1339 ? Type->getOperand(1).getReg()

1340 : Type->getOperand(0).getReg();

1344 return ScalarType;

1345}

1346

1347unsigned

1349 assert(Type && "Invalid Type pointer");

1350 if (Type->getOpcode() == SPIRV::OpTypeVector) {

1351 auto EleTypeReg = Type->getOperand(1).getReg();

1353 }

1354 if (Type->getOpcode() == SPIRV::OpTypeInt ||

1355 Type->getOpcode() == SPIRV::OpTypeFloat)

1356 return Type->getOperand(1).getImm();

1357 if (Type->getOpcode() == SPIRV::OpTypeBool)

1358 return 1;

1359 llvm_unreachable("Attempting to get bit width of non-integer/float type.");

1360}

1361

1364 assert(Type && "Invalid Type pointer");

1365 unsigned NumElements = 1;

1366 if (Type->getOpcode() == SPIRV::OpTypeVector) {

1367 NumElements = static_cast<unsigned>(Type->getOperand(2).getImm());

1369 }

1370 return Type->getOpcode() == SPIRV::OpTypeInt ||

1371 Type->getOpcode() == SPIRV::OpTypeFloat

1372 ? NumElements * Type->getOperand(1).getImm()

1373 : 0;

1374}

1375

1378 if (Type && Type->getOpcode() == SPIRV::OpTypeVector)

1380 return Type && Type->getOpcode() == SPIRV::OpTypeInt ? Type : nullptr;

1381}

1382

1387

1389 return PtrType && PtrType->getOpcode() == SPIRV::OpTypePointer

1391 : nullptr;

1392}

1393

1396 return ElemType ? ElemType->getOpcode() : 0;

1397}

1398

1401 if (!Type1 || !Type2)

1402 return false;

1404

1405

1406

1407 if (Op1 == SPIRV::OpTypePointer &&

1409 return true;

1410 if (Op2 == SPIRV::OpTypePointer &&

1412 return true;

1415 return Bits1 > 0 && Bits1 == Bits2;

1416}

1417

1418SPIRV::StorageClass::StorageClass

1421 assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&

1422 Type->getOperand(1).isImm() && "Pointer type is expected");

1424}

1425

1426SPIRV::StorageClass::StorageClass

1428 return static_castSPIRV::StorageClass::StorageClass\(

1430}

1431

1434 SPIRV::StorageClass::StorageClass SC, bool IsWritable, bool EmitIr) {

1437 return MI;

1438

1440

1441

1443 auto *BlockType =

1445 ExplicitLayoutRequired, EmitIr);

1446

1447 buildOpDecorate(BlockType->defs().begin()->getReg(), MIRBuilder,

1448 SPIRV::Decoration::Block, {});

1449

1450 if (!IsWritable) {

1452 SPIRV::Decoration::NonWritable, 0, {});

1453 }

1454

1455 SPIRVType *R = getOrCreateSPIRVPointerTypeInternal(BlockType, MIRBuilder, SC);

1457 return R;

1458}

1459

1464 return MI;

1467 finishCreatingSPIRVType(T, R);

1469 return R;

1470}

1471

1476 return MI;

1477

1480 assert(ST->getNumElements() == Offsets.size());

1481

1483 for (uint32_t I = 0; I < Offsets.size(); ++I) {

1485 {Offsets[I]});

1486 }

1487 };

1488

1489

1490

1491

1493 getOpTypeStruct(ST, MIRBuilder, SPIRV::AccessQualifier::None,

1494 std::move(Decorator), EmitIr);

1495 add(Key, SPIRVStructType);

1496 return SPIRVStructType;

1497}

1498

1501 const SPIRV::AccessQualifier::AccessQualifier Qualifier,

1504 "SPIR-V image builtin type must have sampled type parameter!");

1507 SPIRV::AccessQualifier::ReadWrite, true);

1510 "Invalid number of parameters for SPIR-V image builtin!");

1511

1512 SPIRV::AccessQualifier::AccessQualifier accessQualifier =

1513 SPIRV::AccessQualifier::None;

1515 accessQualifier = Qualifier == SPIRV::AccessQualifier::WriteOnly

1516 ? SPIRV::AccessQualifier::WriteOnly

1517 : SPIRV::AccessQualifier::AccessQualifier(

1519 }

1520

1521

1522 SPIRVType *R = getOrCreateOpTypeImage(

1523 MIRBuilder, SampledType,

1527 SPIRV::ImageFormat::ImageFormat(ExtensionType->getIntParameter(5)),

1528 accessQualifier);

1529 SPIRVToLLVMType[R] = ExtensionType;

1530 return R;

1531}

1532

1533SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeImage(

1536 SPIRV::ImageFormat::ImageFormat ImageFormat,

1537 SPIRV::AccessQualifier::AccessQualifier AccessQual) {

1539 Depth, Arrayed, Multisampled, Sampled,

1540 ImageFormat, AccessQual);

1542 return MI;

1544 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1545 auto MIB =

1546 MIRBuilder.buildInstr(SPIRV::OpTypeImage)

1550 .addImm(Depth)

1551 .addImm(Arrayed)

1552 .addImm(Multisampled)

1553 .addImm(Sampled)

1554 .addImm(ImageFormat);

1555 if (AccessQual != SPIRV::AccessQualifier::None)

1556 MIB.addImm(AccessQual);

1557 return MIB;

1558 });

1560 return NewMI;

1561}

1562

1568 return MI;

1570 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1571 return MIRBuilder.buildInstr(SPIRV::OpTypeSampler)

1573 });

1575 return NewMI;

1576}

1577

1580 SPIRV::AccessQualifier::AccessQualifier AccessQual) {

1583 return MI;

1585 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1586 return MIRBuilder.buildInstr(SPIRV::OpTypePipe)

1588 .addImm(AccessQual);

1589 });

1591 return NewMI;

1592}

1593

1598 return MI;

1600 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1601 return MIRBuilder.buildInstr(SPIRV::OpTypeDeviceEvent)

1603 });

1605 return NewMI;

1606}

1607

1613 ImageType);

1615 return MI;

1617 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1618 return MIRBuilder.buildInstr(SPIRV::OpTypeSampledImage)

1621 });

1623 return NewMI;

1624}

1625

1631 findMI(ExtensionType, false, &MIRBuilder.getMF()))

1632 return MI;

1634 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1639 .canUseExtension(SPIRV::Extension::SPV_INTEL_int4)) {

1640 MIRBuilder.buildInstr(SPIRV::OpCapability)

1641 .addImm(SPIRV::Capability::Int4CooperativeMatrixINTEL);

1642 }

1643 return MIRBuilder.buildInstr(SPIRV::OpTypeCooperativeMatrixKHR)

1650 });

1651 add(ExtensionType, false, NewMI);

1652 return NewMI;

1653}

1654

1658 return MI;

1660 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1662 });

1663 add(Ty, false, NewMI);

1664 return NewMI;

1665}

1666

1671 return MI;

1674 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1678 for (MCOperand Operand : Operands) {

1679 if (Operand.isReg()) {

1680 MIB.addUse(Operand.getReg());

1681 } else if (Operand.isImm()) {

1682 MIB.addImm(Operand.getImm());

1683 }

1684 }

1685 return MIB;

1686 });

1687 add(Ty, false, NewMI);

1688 return NewMI;

1689}

1690

1691

1694 SPIRV::StorageClass::StorageClass SC,

1695 SPIRV::AccessQualifier::AccessQualifier AQ) {

1696 unsigned VecElts = 0;

1698

1699

1703 MIRBuilder, AQ, false, true);

1704

1705

1706

1708

1710 if (!Ty)

1711

1712 return nullptr;

1713

1716

1717

1720

1721

1722 bool IsPtrToVec = TypeStr.consume_back("*");

1723

1725 TypeStr = TypeStr.substr(0, TypeStr.find(']'));

1726 }

1728 if (VecElts > 0)

1730

1731 if (IsPtrToVec)

1733

1734 return SpirvTy;

1735}

1736

1742 MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false, true);

1743}

1744

1745SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy,

1749 SPIRVToLLVMType[SpirvType] = unifyPtrType(LLVMTy);

1750 return SpirvType;

1751}

1752

1756 unsigned SPIRVOPcode,

1759 return MI;

1763 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1765 MIRBuilder.getDL(), TII.get(SPIRVOPcode))

1768

1769 if (!Ty->isFloatTy()) {

1770 return NewTypeMI.addImm(0);

1771 } else {

1772 return NewTypeMI;

1773 }

1774 });

1775 add(Ty, false, NewMI);

1776 return finishCreatingSPIRVType(Ty, NewMI);

1777}

1778

1781

1782

1783

1784

1789}

1790

1794 Type *LLVMTy;

1796 case 16:

1798 break;

1799 case 32:

1801 break;

1802 case 64:

1804 break;

1805 default:

1807 }

1809}

1810

1813 bool EmitIR) {

1816 MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false, EmitIR);

1817}

1818

1824 return MI;

1828 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1830 MIRBuilder.getDL(), TII.get(SPIRV::OpTypeBool))

1832 });

1833 add(Ty, false, NewMI);

1834 return finishCreatingSPIRVType(Ty, NewMI);

1835}

1836

1839 bool EmitIR) {

1842 NumElements),

1843 MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false, EmitIR);

1844}

1845

1852 return MI;

1856 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1858 MIRBuilder.getDL(), TII.get(SPIRV::OpTypeVector))

1861 .addImm(NumElements);

1862 });

1863 add(Ty, false, NewMI);

1864 return finishCreatingSPIRVType(Ty, NewMI);

1865}

1866

1869 SPIRV::StorageClass::StorageClass SC) {

1872}

1873

1876 SPIRV::StorageClass::StorageClass SC) {

1877

1879 BaseType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,

1881 assert(SpirvBaseType);

1882 return getOrCreateSPIRVPointerTypeInternal(SpirvBaseType, MIRBuilder, SC);

1883}

1884

1887 [[maybe_unused]] SPIRV::StorageClass::StorageClass OldSC =

1891

1894 return getOrCreateSPIRVPointerTypeInternal(PointeeType, MIRBuilder, SC);

1895}

1896

1899 SPIRV::StorageClass::StorageClass SC) {

1905 "The base type was not correctly laid out for the given storage class.");

1906 return R;

1907}

1908

1909SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerTypeInternal(

1911 SPIRV::StorageClass::StorageClass SC) {

1915 return MI;

1919 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1922 MIRBuilder.getTII().get(SPIRV::OpTypePointer))

1926 });

1928 return finishCreatingSPIRVType(Ty, NewMI);

1929}

1930

1938 return Res;

1939

1941 Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);

1942 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);

1944

1948 createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {

1950 MIRBuilder.getDL(), TII.get(SPIRV::OpUndef))

1953 const auto &ST = CurMF->getSubtarget();

1955 *ST.getRegisterInfo(),

1956 *ST.getRegBankInfo());

1957 return MIB;

1958 });

1959 add(UV, NewMI);

1960 return Res;

1961}

1962

1965 unsigned Opcode = SpvType->getOpcode();

1966 switch (Opcode) {

1967 case SPIRV::OpTypeFloat:

1968 return &SPIRV::fIDRegClass;

1969 case SPIRV::OpTypePointer:

1970 return &SPIRV::pIDRegClass;

1971 case SPIRV::OpTypeVector: {

1973 unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;

1974 if (ElemOpcode == SPIRV::OpTypeFloat)

1975 return &SPIRV::vfIDRegClass;

1976 if (ElemOpcode == SPIRV::OpTypePointer)

1977 return &SPIRV::vpIDRegClass;

1978 return &SPIRV::vIDRegClass;

1979 }

1980 }

1981 return &SPIRV::iIDRegClass;

1982}

1983

1986 static_castSPIRV::StorageClass::StorageClass\(

1988}

1989

1991 unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;

1992 switch (Opcode) {

1993 case SPIRV::OpTypeInt:

1994 case SPIRV::OpTypeFloat:

1995 case SPIRV::OpTypeBool:

1997 case SPIRV::OpTypePointer:

1999 case SPIRV::OpTypeVector: {

2002 switch (ElemType ? ElemType->getOpcode() : 0) {

2003 case SPIRV::OpTypePointer:

2005 break;

2006 case SPIRV::OpTypeInt:

2007 case SPIRV::OpTypeFloat:

2008 case SPIRV::OpTypeBool:

2010 break;

2011 default:

2013 }

2015 static_cast<unsigned>(SpvType->getOperand(2).getImm()), ET);

2016 }

2017 }

2019}

2020

2021

2022

2023

2024

2025

2026

2030 return nullptr;

2031 if (auto L = AliasInstMDMap.find(AliasingListMD); L != AliasInstMDMap.end())

2032 return L->second;

2033

2038 if (ScopeMD->getNumOperands() < 2)

2039 return nullptr;

2041 if (!DomainMD)

2042 return nullptr;

2043 auto *Domain = [&] {

2044 auto D = AliasInstMDMap.find(DomainMD);

2045 if (D != AliasInstMDMap.end())

2046 return D->second;

2047 const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);

2048 auto MIB =

2049 MIRBuilder.buildInstr(SPIRV::OpAliasDomainDeclINTEL).addDef(Ret);

2051 }();

2052 AliasInstMDMap.insert(std::make_pair(DomainMD, Domain));

2053 auto *Scope = [&] {

2054 auto S = AliasInstMDMap.find(ScopeMD);

2055 if (S != AliasInstMDMap.end())

2056 return S->second;

2057 const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);

2058 auto MIB = MIRBuilder.buildInstr(SPIRV::OpAliasScopeDeclINTEL)

2062 }();

2063 AliasInstMDMap.insert(std::make_pair(ScopeMD, Scope));

2065 }

2066 }

2067

2068 const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);

2069 auto MIB =

2070 MIRBuilder.buildInstr(SPIRV::OpAliasScopeListDeclINTEL).addDef(Ret);

2071 for (auto *Scope : ScopeList)

2072 MIB.addUse(Scope->getOperand(0).getReg());

2074 AliasInstMDMap.insert(std::make_pair(AliasingListMD, List));

2075 return List;

2076}

2077

2080 const MDNode *AliasingListMD) {

2083 if (!AliasList)

2084 return;

2085 MIRBuilder.buildInstr(SPIRV::OpDecorate)

2089}

2091 bool DeleteOld) {

2095}

2096

2100 CallInst *AssignCI = nullptr;

2107 B.CreateIntrinsic(Intrinsic::spv_value_md,

2109 AssignCI = B.CreateIntrinsic(Intrinsic::fake_use, {Arg});

2110 } else {

2112 OfType, Arg, {}, B);

2113 }

2115}

2116

2122 B.GetInsertBlock() ? B.GetInsertBlock()->getParent() : nullptr;

2123 if (AssignPtrTyCI == nullptr ||

2124 AssignPtrTyCI->getParent()->getParent() != CurrF) {

2126 Intrinsic::spv_assign_ptr_type, {Arg->getType()}, OfType, Arg,

2131 } else {

2133 }

2134}

2135

2137 Value *OfType) {

2140 Intrinsic::spv_assign_ptr_type)

2141 return;

2142

2143

2147}

2148

2149void SPIRVGlobalRegistry::addStructOffsetDecorations(

2153 for (uint32_t I = 0; I < Ty->getNumElements(); ++I) {

2155 {static_cast<uint32_t>(Offsets[I])});

2156 }

2157}

2158

2159void SPIRVGlobalRegistry::addArrayStrideDecorations(

2161 uint32_t SizeInBytes = DataLayout().getTypeSizeInBits(ElementType) / 8;

2163 {SizeInBytes});

2164}

2165

2166bool SPIRVGlobalRegistry::hasBlockDecoration(SPIRVType *Type) const {

2168 for (const MachineInstr &Use :

2169 Type->getMF()->getRegInfo().use_instructions(Def)) {

2170 if (Use.getOpcode() != SPIRV::OpDecorate)

2171 continue;

2172

2173 if (Use.getOperand(1).getImm() == SPIRV::Decoration::Block)

2174 return true;

2175 }

2176 return false;

2177}

unsigned const MachineRegisterInfo * MRI

static unsigned getIntrinsicID(const SDNode *N)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file implements a class to represent arbitrary precision integral constant values and operations...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis false

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Promote Memory to Register

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

static unsigned getNumElements(Type *Ty)

static bool storageClassRequiresExplictLayout(SPIRV::StorageClass::StorageClass SC)

Definition SPIRVGlobalRegistry.cpp:60

static Register createTypeVReg(MachineRegisterInfo &MRI)

Definition SPIRVGlobalRegistry.cpp:136

unsigned getAS(SPIRVType *SpvType)

Definition SPIRVGlobalRegistry.cpp:1984

static bool allowEmitFakeUse(const Value *Arg)

Definition SPIRVGlobalRegistry.cpp:37

static unsigned typeToAddressSpace(const Type *Ty)

Definition SPIRVGlobalRegistry.cpp:48

APInt bitcastToAPInt() const

Class for arbitrary precision integers.

uint64_t getZExtValue() const

Get zero extended value.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Class to represent array types.

uint64_t getNumElements() const

Type * getElementType() const

void setArgOperand(unsigned i, Value *v)

This class represents a function call, abstracting a target machine's calling convention.

ConstantFP - Floating Point Values [float, double].

const APFloat & getValue() const

const APFloat & getValueAPF() const

This is the shared class of boolean and integer constants.

bool isZero() const

This is just a convenience method to make client code smaller for a common code.

uint64_t getZExtValue() const

Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...

static Constant * getAnon(ArrayRef< Constant * > V, bool Packed=false)

Return an anonymous struct that has the specified elements.

static LLVM_ABI ConstantTargetNone * get(TargetExtType *T)

Static factory methods - Return objects of the specified value.

static LLVM_ABI Constant * getSplat(ElementCount EC, Constant *Elt)

Return a ConstantVector with the specified constant in each element.

This is an important base class in LLVM.

LLVM_ABI const APInt & getUniqueInteger() const

If C is a constant integer then return its value, otherwise C must be a vector of constant integers,...

LLVM_ABI bool isNullValue() const

Return true if this is the value that would be returned by getNullValue.

A parsed version of the target data layout string in and methods for querying it.

Class to represent fixed width SIMD vectors.

static LLVM_ABI FixedVectorType * get(Type *ElementType, unsigned NumElts)

Class to represent function types.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

MDNode * getMetadata(unsigned KindID) const

Get the current metadata attachments for the given kind, if any.

Module * getParent()

Get the module that this global value is contained inside of...

@ ExternalLinkage

Externally visible function.

MaybeAlign getAlign() const

Returns the alignment of the given variable.

This provides a uniform API for creating instructions and inserting them into a basic block: either a...

Class to represent integer types.

static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)

This static method is the primary way of constructing an IntegerType.

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)

Get a low-level pointer in the given address space.

static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)

Get a low-level fixed-width vector of some number of elements and element width.

This is an important class for using LLVM in a threaded context.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Instances of this class represent operands of the MCInst class.

ArrayRef< MDOperand > operands() const

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

unsigned getNumOperands() const

Return number of MDNode operands.

Tracking metadata reference owned by Metadata.

static LLVM_ABI MDString * get(LLVMContext &Context, StringRef Str)

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

LLVM_ABI iterator getFirstNonPHI()

Returns a pointer to the first instruction in this block that is not a PHINode instruction.

MachineInstrBundleIterator< MachineInstr > iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Helper class to build MachineInstr.

void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)

Set the insertion point before the specified position.

LLVMContext & getContext() const

const TargetInstrInfo & getTII()

MachineBasicBlock::iterator getInsertPt()

Current insertion point for new instructions.

MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

const DebugLoc & getDL()

Getter for DebugLoc.

MachineFunction & getMF()

Getter for the function we currently build.

const MachineBasicBlock & getMBB() const

Getter for the basic block we currently build.

const DebugLoc & getDebugLoc()

Get the current instruction's debug location.

MachineRegisterInfo * getMRI()

Getter for MRI.

MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)

Build and insert Res = COPY Op.

virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)

Build and insert Res = G_CONSTANT Val.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

mop_range defs()

Returns all explicit operands that are register definitions.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

LLVM_ABI void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)

Inserts Ops BEFORE It. Can untie/retie tied operands.

mop_range uses()

Returns all operands which may be register uses.

LLVM_ABI const MachineFunction * getMF() const

Return the function that contains the basic block that this instruction belongs to.

const MachineOperand & getOperand(unsigned i) const

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

A Module instance is used to store all the information related to an LLVM module.

static LLVM_ABI PoisonValue * get(Type *T)

Static factory methods - Return an 'poison' object of the specified type.

Wrapper class representing virtual and physical registers.

constexpr bool isValid() const

SPIRVType * getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual)

Definition SPIRVGlobalRegistry.cpp:1578

unsigned getNumScalarOrVectorTotalBitWidth(const SPIRVType *Type) const

Definition SPIRVGlobalRegistry.cpp:1362

SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const

Definition SPIRVGlobalRegistry.cpp:1220

Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)

Definition SPIRVGlobalRegistry.cpp:377

SPIRVType * getResultType(Register VReg, MachineFunction *MF=nullptr)

Definition SPIRVGlobalRegistry.cpp:1231

void addAssignPtrTypeInstr(Value *Val, CallInst *AssignPtrTyCI)

SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder, bool EmitIR)

Definition SPIRVGlobalRegistry.cpp:1812

void buildAssignPtr(IRBuilder<> &B, Type *ElemTy, Value *Arg)

Definition SPIRVGlobalRegistry.cpp:2117

SPIRVType * getOrCreatePaddingType(MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1461

SPIRVType * assignFloatTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)

Definition SPIRVGlobalRegistry.cpp:104

MachineInstr * getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD)

Definition SPIRVGlobalRegistry.cpp:2027

void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, const MachineFunction &MF)

Definition SPIRVGlobalRegistry.cpp:130

SPIRVType * assignVectTypeToVReg(SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)

Definition SPIRVGlobalRegistry.cpp:112

Definition SPIRVGlobalRegistry.cpp:1931

Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, const std::optional< SPIRV::LinkageType::LinkageType > &LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)

Definition SPIRVGlobalRegistry.cpp:743

void replaceAllUsesWith(Value *Old, Value *New, bool DeleteOld=true)

Definition SPIRVGlobalRegistry.cpp:2090

SPIRVType * changePointerStorageClass(SPIRVType *PtrType, SPIRV::StorageClass::StorageClass SC, MachineInstr &I)

Definition SPIRVGlobalRegistry.cpp:1885

const Type * getTypeForSPIRVType(const SPIRVType *Ty) const

SPIRVType * getOrCreateUnknownType(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode, const ArrayRef< MCOperand > Operands)

Definition SPIRVGlobalRegistry.cpp:1667

bool isBitcastCompatible(const SPIRVType *Type1, const SPIRVType *Type2) const

Definition SPIRVGlobalRegistry.cpp:1399

unsigned getScalarOrVectorComponentCount(Register VReg) const

Definition SPIRVGlobalRegistry.cpp:1316

Register createConstInt(const ConstantInt *CI, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull)

Definition SPIRVGlobalRegistry.cpp:390

SPIRVType * getOrCreateSPIRVFloatType(unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII)

Definition SPIRVGlobalRegistry.cpp:1791

bool isScalarOrVectorSigned(const SPIRVType *Type) const

Definition SPIRVGlobalRegistry.cpp:1383

void addDeducedElementType(Value *Val, Type *Ty)

SPIRVGlobalRegistry(unsigned PointerSize)

Definition SPIRVGlobalRegistry.cpp:91

Register getOrCreateGlobalVariableWithBinding(const SPIRVType *VarType, uint32_t Set, uint32_t Binding, StringRef Name, MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:848

SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineInstr &I, SPIRV::AccessQualifier::AccessQualifier AQ, bool EmitIR)

unsigned getPointerSize() const

SPIRVType * getOrCreateSPIRVPointerType(const Type *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SC)

Definition SPIRVGlobalRegistry.cpp:1874

SPIRVType * getOrCreateOpTypeByOpcode(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode)

Definition SPIRVGlobalRegistry.cpp:1655

Definition SPIRVGlobalRegistry.cpp:478

SPIRVType * getPointeeType(SPIRVType *PtrType)

Definition SPIRVGlobalRegistry.cpp:1388

void invalidateMachineInstr(MachineInstr *MI)

Definition SPIRVGlobalRegistry.cpp:227

Definition SPIRVGlobalRegistry.cpp:1063

Register createConstFP(const ConstantFP *CF, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull)

Definition SPIRVGlobalRegistry.cpp:339

void updateIfExistDeducedElementType(Value *OldVal, Value *NewVal, bool DeleteOld)

bool isScalarOfType(Register VReg, unsigned TypeOpcode) const

Definition SPIRVGlobalRegistry.cpp:1281

SPIRVType * assignIntTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)

Definition SPIRVGlobalRegistry.cpp:94

unsigned getPointeeTypeOp(Register PtrReg)

Definition SPIRVGlobalRegistry.cpp:1394

SPIRVType * getOrCreateOpTypeSampledImage(SPIRVType *ImageType, MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1608

SPIRVType * getOrCreateVulkanBufferType(MachineIRBuilder &MIRBuilder, Type *ElemType, SPIRV::StorageClass::StorageClass SC, bool IsWritable, bool EmitIr=false)

Definition SPIRVGlobalRegistry.cpp:1432

SPIRVType * getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder, bool EmitIR, SPIRV::StorageClass::StorageClass SC=SPIRV::StorageClass::Function, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite)

Definition SPIRVGlobalRegistry.cpp:1692

SPIRVType * getOrCreateLayoutType(MachineIRBuilder &MIRBuilder, const TargetExtType *T, bool EmitIr=false)

Definition SPIRVGlobalRegistry.cpp:1472

void addGlobalObject(const Value *V, const MachineFunction *MF, Register R)

SPIRVType * getScalarOrVectorComponentType(Register VReg) const

Definition SPIRVGlobalRegistry.cpp:1330

SPIRVType * getOrCreateOpTypeFunctionWithArgs(const Type *Ty, SPIRVType *RetType, const SmallVectorImpl< SPIRVType * > &ArgTypes, MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1036

void buildAssignType(IRBuilder<> &B, Type *Ty, Value *Arg)

Definition SPIRVGlobalRegistry.cpp:2097

Definition SPIRVGlobalRegistry.cpp:675

const TargetRegisterClass * getRegClass(SPIRVType *SpvType) const

Definition SPIRVGlobalRegistry.cpp:1964

void updateIfExistAssignPtrTypeInstr(Value *OldVal, Value *NewVal, bool DeleteOld)

SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder, bool EmitIR)

Definition SPIRVGlobalRegistry.cpp:1837

SPIRVType * getOrCreateOpTypeCoopMatr(MachineIRBuilder &MIRBuilder, const TargetExtType *ExtensionType, const SPIRVType *ElemType, uint32_t Scope, uint32_t Rows, uint32_t Columns, uint32_t Use, bool EmitIR)

Definition SPIRVGlobalRegistry.cpp:1626

bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const

Definition SPIRVGlobalRegistry.cpp:1288

Register getOrCreateConstIntArray(uint64_t Val, size_t Num, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)

Definition SPIRVGlobalRegistry.cpp:611

Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)

Definition SPIRVGlobalRegistry.cpp:573

SPIRVType * getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1594

SPIRVType * getImageType(const TargetExtType *ExtensionType, const SPIRV::AccessQualifier::AccessQualifier Qualifier, MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1499

bool isResourceType(SPIRVType *Type) const

Definition SPIRVGlobalRegistry.cpp:1302

SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1738

Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR, bool ZeroAsNull=true)

Definition SPIRVGlobalRegistry.cpp:432

SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ, bool EmitIR)

Definition SPIRVGlobalRegistry.cpp:121

LLT getRegType(SPIRVType *SpvType) const

Definition SPIRVGlobalRegistry.cpp:1990

void buildMemAliasingOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, uint32_t Dec, const MDNode *GVarMD)

Definition SPIRVGlobalRegistry.cpp:2078

SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const

Definition SPIRVGlobalRegistry.cpp:1419

SPIRVType * getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:1564

Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder)

Definition SPIRVGlobalRegistry.cpp:720

void updateAssignType(CallInst *AssignCI, Value *Arg, Value *OfType)

Definition SPIRVGlobalRegistry.cpp:2136

Register getOrCreateConstFP(APFloat Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)

Definition SPIRVGlobalRegistry.cpp:326

CallInst * findAssignPtrTypeInstr(const Value *Val)

Definition SPIRVGlobalRegistry.cpp:692

unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const

Definition SPIRVGlobalRegistry.cpp:1348

const SPIRVType * retrieveScalarOrVectorIntType(const SPIRVType *Type) const

Definition SPIRVGlobalRegistry.cpp:1376

const MachineInstr * findMI(SPIRV::IRHandle Handle, const MachineFunction *MF)

bool erase(const MachineInstr *MI)

bool add(SPIRV::IRHandle Handle, const MachineInstr *MI)

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

bool consume_back(StringRef Suffix)

Returns true if this StringRef has the given suffix and removes that suffix.

bool getAsInteger(unsigned Radix, T &Result) const

Parse the current string as an integer of the specified radix.

std::string str() const

str - Get the contents as an std::string.

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

bool consume_front(StringRef Prefix)

Returns true if this StringRef has the given prefix and removes that prefix.

size_t find(char C, size_t From=0) const

Search for the first character C in the string.

Class to represent struct types.

ArrayRef< Type * > elements() const

static LLVM_ABI StructType * create(LLVMContext &Context, StringRef Name)

This creates an identified struct.

unsigned getNumElements() const

Random access to the elements.

bool hasName() const

Return true if this is a named struct that has a non-empty name.

LLVM_ABI StringRef getName() const

Return the name for this struct type if it has an identity.

Class to represent target extensions types, which are generally unintrospectable from target-independ...

unsigned getNumIntParameters() const

Type * getTypeParameter(unsigned i) const

unsigned getNumTypeParameters() const

unsigned getIntParameter(unsigned i) const

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM_ABI unsigned getIntegerBitWidth() const

bool isVectorTy() const

True if this is an instance of VectorType.

bool isArrayTy() const

True if this is an instance of ArrayType.

Type * getArrayElementType() const

bool isBFloatTy() const

Return true if this is 'bfloat', a 16-bit bfloat type.

LLVM_ABI uint64_t getArrayNumElements() const

static LLVM_ABI IntegerType * getInt8Ty(LLVMContext &C)

LLVM_ABI TypeSize getPrimitiveSizeInBits() const LLVM_READONLY

Return the basic size of this type if it is a primitive type.

bool isAggregateType() const

Return true if the type is an aggregate type.

bool isFloatingPointTy() const

Return true if this is one of the floating-point types.

bool isIntegerTy() const

True if this is an instance of IntegerType.

static LLVM_ABI Type * getDoubleTy(LLVMContext &C)

static LLVM_ABI Type * getFloatTy(LLVMContext &C)

static LLVM_ABI Type * getHalfTy(LLVMContext &C)

bool isVoidTy() const

Return true if this is 'void'.

static LLVM_ABI TypedPointerType * get(Type *ElementType, unsigned AddressSpace)

This constructs a pointer to an object of the specified type in a numbered address space.

'undef' values are things that do not have specified contents.

static LLVM_ABI UndefValue * get(Type *T)

Static factory methods - Return an 'undef' object of the specified type.

A Use represents the edge between a Value definition and its users.

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

LLVM_ABI void replaceAllUsesWith(Value *V)

Change all uses of this to point to a new Value.

LLVM_ABI LLVMContext & getContext() const

All values hold a context through their type.

LLVM_ABI StringRef getName() const

Return a constant reference to the value's name.

ElementCount getElementCount() const

Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...

Type * getElementType() const

const ParentTy * getParent() const

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

IRHandle handle(const Type *Ty)

IRHandle irhandle_sampled_image(const Type *SampledTy, const MachineInstr *ImageTy)

IRHandle irhandle_padding()

IRHandle irhandle_vkbuffer(const Type *ElementType, StorageClass::StorageClass SC, bool IsWriteable)

IRHandle irhandle_sampler()

TargetExtType * parseBuiltinTypeNameToTargetExtType(std::string TypeName, LLVMContext &Context)

Translates a string representing a SPIR-V or OpenCL builtin type to a TargetExtType that can be furth...

SPIRVType * lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)

IRHandle irhandle_event()

IRHandle irhandle_pipe(uint8_t AQ)

IRHandle irhandle_image(const Type *SampledTy, unsigned Dim, unsigned Depth, unsigned Arrayed, unsigned MS, unsigned Sampled, unsigned ImageFormat, unsigned AQ=0)

NodeAddr< DefNode * > Def

NodeAddr< UseNode * > Use

This is an optimization pass for GlobalISel generic memory operations.

void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)

bool isTypedPointerWrapper(const TargetExtType *ExtTy)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

unsigned getPointerAddressSpace(const Type *T)

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)

LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)

Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...

CallInst * buildIntrWithMD(Intrinsic::ID IntrID, ArrayRef< Type * > Types, Value *Arg, Value *Arg2, ArrayRef< Constant * > Imms, IRBuilder<> &B)

bool matchPeeledArrayPattern(const StructType *Ty, Type *&OriginalElementType, uint64_t &TotalSize)

LLVM_ABI void reportFatalInternalError(Error Err)

Report a fatal error that indicates a bug in LLVM.

constexpr unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)

bool getSpirvBuiltInIdByName(llvm::StringRef Name, SPIRV::BuiltIn::BuiltIn &BI)

MetadataAsValue * buildMD(Value *Arg)

bool isTypedPointerTy(const Type *T)

void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

Type * getTypedPointerWrapper(Type *ElemTy, unsigned AS)

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

void buildOpMemberDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, uint32_t Member, const std::vector< uint32_t > &DecArgs, StringRef StrImm)

Type * toTypedPointer(Type *Ty)

bool isSpecialOpaqueType(const Type *Ty)

bool isPointerTy(const Type *T)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

MachineBasicBlock::iterator getInsertPtValidEnd(MachineBasicBlock *MBB)

const Type * unifyPtrType(const Type *Ty)

const MachineInstr SPIRVType

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key

std::function< void(Register)> StructOffsetDecorator

SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)

void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder, const MDNode *GVarMD, const SPIRVSubtarget &ST)

Type * parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx)

DWARFExpression::Operation Op

constexpr unsigned BitWidth

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

bool hasBuiltinTypePrefix(StringRef Name)

bool isPointerTyOrWrapper(const Type *Ty)

bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID)

PoisonValue * getNormalizedPoisonValue(Type *Ty)

void addStringImm(const StringRef &Str, MCInst &Inst)

MachineInstr * getVRegDef(MachineRegisterInfo &MRI, Register Reg)

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

constexpr uint64_t value() const

This is a hole in the type system and should not be abused.

Align valueOrOne() const

For convenience, returns a valid alignment or 1 if undefined.