LLVM: include/llvm/CodeGen/ScheduleDAG.h Source File (original) (raw)
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15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16#define LLVM_CODEGEN_SCHEDULEDAG_H
17
27#include
28#include
29#include
30#include
31#include
32
33namespace llvm {
34
35template struct GraphTraits;
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85 union {
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93 } Contents;
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100 public:
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107 switch (kind) {
108 default:
112 assert(Reg && "SDep::Anti and SDep::Output must use a non-zero Reg!");
113 Contents.Reg = Reg.id();
114 Latency = 0;
115 break;
117 Contents.Reg = Reg.id();
118 Latency = 1;
119 break;
120 }
121 }
122
124 : Dep(S, Order), Contents(), Latency(0) {
125 Contents.OrdKind = kind;
126 }
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143 return Latency;
144 }
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218 "getReg called on non-register dependence edge!");
219 return Contents.Reg;
220 }
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228 "setReg called on non-register dependence edge!");
230 "SDep::Anti edge cannot use the zero register!");
232 "SDep::Output edge cannot use the zero register!");
233 Contents.Reg = Reg.id();
234 }
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237 };
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250 private:
251 enum : unsigned { BoundaryID = ~0u };
252
253 union {
256 };
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258 public:
259 SUnit *OrigNode = nullptr;
260
261
263 nullptr;
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266 nullptr;
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276
277 unsigned NodeNum = BoundaryID;
281 unsigned NumPredsLeft = 0;
282 unsigned NumSuccsLeft = 0;
283 unsigned WeakPredsLeft = 0;
284 unsigned WeakSuccsLeft = 0;
285 unsigned TopReadyCycle = 0;
286 unsigned BotReadyCycle = 0;
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289
290 private:
291 unsigned Depth = 0;
292 unsigned Height = 0;
293
294 public:
295 bool isVRegCycle : 1;
298 bool isTwoAddress : 1;
301 bool hasPhysRegDefs : 1;
306 bool isScheduleHigh : 1;
307 bool isScheduleLow : 1;
311 unsigned short NumRegDefsLeft = 0;
312 unsigned short Latency = 0;
313
314 private:
315 bool isDepthCurrent : 1;
316 bool isHeightCurrent : 1;
317 bool isNode : 1;
318 bool isInst : 1;
319
320 public:
323 "not enough bits in bitfield");
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372 assert(!isInst && "Setting SDNode of SUnit with MachineInstr!");
374 isNode = true;
375 }
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381 "Reading SDNode of SUnit without SDNode!");
383 }
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392 assert(!isNode && "Setting MachineInstr of SUnit with SDNode!");
394 isInst = true;
395 }
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400 assert(!isNode && (isInst || ) &&
401 "Reading MachineInstr of SUnit without MachineInstr!");
403 }
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413 unsigned TrueMemOrderLatency =
414 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
417 }
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424
426 if (!isDepthCurrent)
427 const_cast<SUnit *>(this)->ComputeDepth();
428 return Depth;
429 }
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434 if (!isHeightCurrent)
435 const_cast<SUnit *>(this)->ComputeHeight();
436 return Height;
437 }
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460 if (Pred.getSUnit() == N)
461 return true;
462 return false;
463 }
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468 if (Succ.getSUnit() == N)
469 return true;
470 return false;
471 }
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486 private:
487 LLVM_ABI void ComputeDepth();
488 LLVM_ABI void ComputeHeight();
489 };
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493 if (Dep != Other.Dep)
494 return false;
495 switch (Dep.getInt()) {
499 return Contents.Reg == Other.Contents.Reg;
501 return Contents.OrdKind == Other.Contents.OrdKind;
502 }
504 }
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524 virtual void anchor();
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526 unsigned CurCycle = 0;
527 bool HasReadyFilter;
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529 public:
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536 virtual void initNodes(std::vector &SUnits) = 0;
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541 virtual bool empty() const = 0;
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548 assert(!HasReadyFilter && "The ready filter must override isReady()");
549 return true;
550 }
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554 void push_all(const std::vector<SUnit *> &Nodes) {
555 for (SUnit *SU : Nodes)
557 }
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573 CurCycle = Cycle;
574 }
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577 return CurCycle;
578 }
579 };
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582 public:
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592#ifdef NDEBUG
594#else
596#endif
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618 return getNodeDesc(SU->getNode());
619 }
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622 virtual void viewGraph(const Twine &Name, const Twine &Title);
623 virtual void viewGraph();
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626 virtual void dump() const = 0;
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638#ifndef NDEBUG
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641 unsigned VerifyScheduledDAG(bool isBottomUp);
642#endif
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644 protected:
645 void dumpNodeAll(const SUnit &SU) const;
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647 private:
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650 };
651
652 class SUnitIterator {
654 unsigned Operand;
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656 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
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658 public:
664
666 return Operand == x.Operand;
667 }
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671 return Node->Preds[Operand].getSUnit();
672 }
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676 ++Operand;
677 return *this;
678 }
680 SUnitIterator tmp = *this; ++*this; return tmp;
681 }
682
683 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
685 return SUnitIterator(N, (unsigned)N->Preds.size());
686 }
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699 return Node->Preds[Operand];
700 }
701 };
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731 std::vector &SUnits;
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735 bool Dirty = false;
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741 std::vector Index2Node;
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743 std::vector Node2Index;
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750 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
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754 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
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757 void Allocate(int n, int index);
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762 void FixOrder();
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806 typedef std::vector::iterator iterator;
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819 };
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821}
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823#endif
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Register const TargetRegisterInfo * TRI
This file defines the PointerIntPair class.
This file defines the SmallSet class.
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
This file describes how to lower LLVM code to machine code.
Describe properties that are true of each instruction in the target description file.
Representation of each machine instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PointerIntPair - This class implements a pair of a pointer and small integer.
Wrapper class representing virtual and physical registers.
Represents one node in the SelectionDAG.
Scheduling dependency.
Definition ScheduleDAG.h:51
SUnit * getSUnit() const
Definition ScheduleDAG.h:507
bool overlaps(const SDep &Other) const
Returns true if the specified SDep is equivalent except for latency.
Definition ScheduleDAG.h:492
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition ScheduleDAG.h:513
Kind
These are the different kinds of scheduling dependencies.
Definition ScheduleDAG.h:54
@ Output
A register output-dependence (aka WAW).
Definition ScheduleDAG.h:57
@ Order
Any other ordering dependency.
Definition ScheduleDAG.h:58
@ Anti
A register anti-dependence (aka WAR).
Definition ScheduleDAG.h:56
@ Data
Regular data dependence (aka true-dependence).
Definition ScheduleDAG.h:55
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition ScheduleDAG.h:147
bool isWeak() const
Tests if this a weak dependence.
Definition ScheduleDAG.h:194
OrderKind
Definition ScheduleDAG.h:70
@ Cluster
Weak DAG edge linking a chain of clustered instrs.
Definition ScheduleDAG.h:76
@ Barrier
An unknown scheduling barrier.
Definition ScheduleDAG.h:71
@ Artificial
Arbitrary strong DAG edge (no real dependence).
Definition ScheduleDAG.h:74
@ MayAliasMem
Nonvolatile load/Store instructions that may alias.
Definition ScheduleDAG.h:72
@ Weak
Arbitrary weak DAG edge.
Definition ScheduleDAG.h:75
@ MustAliasMem
Nonvolatile load/Store instructions that must alias.
Definition ScheduleDAG.h:73
unsigned OrdKind
Additional information about Order dependencies.
Definition ScheduleDAG.h:92
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition ScheduleDAG.h:142
bool isAssignedRegDep() const
Tests if this is a Data dependence that is associated with a register.
Definition ScheduleDAG.h:211
bool isNormalMemory() const
Tests if this is an Order dependence between two memory accesses where both sides of the dependence a...
Definition ScheduleDAG.h:168
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for c...
Definition ScheduleDAG.h:200
bool operator==(const SDep &Other) const
Definition ScheduleDAG.h:131
bool isCtrl() const
Shorthand for getKind() != SDep::Data.
Definition ScheduleDAG.h:161
SDep(SUnit *S, OrderKind kind)
Definition ScheduleDAG.h:123
SDep()
Constructs a null SDep.
Definition ScheduleDAG.h:103
bool operator!=(const SDep &Other) const
Definition ScheduleDAG.h:135
void setSUnit(SUnit *SU)
Definition ScheduleDAG.h:510
SDep(SUnit *S, Kind kind, Register Reg)
Constructs an SDep with the specified values.
Definition ScheduleDAG.h:106
unsigned Reg
For Data, Anti, and Output dependencies, the associated register.
Definition ScheduleDAG.h:89
Register getReg() const
Returns the register associated with this edge.
Definition ScheduleDAG.h:216
bool isCluster() const
Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants ...
Definition ScheduleDAG.h:206
LLVM_ABI void dump(const TargetRegisterInfo *TRI=nullptr) const
void setReg(Register Reg)
Assigns the associated register for this edge.
Definition ScheduleDAG.h:226
bool isBarrier() const
Tests if this is an Order dependence that is marked as a barrier.
Definition ScheduleDAG.h:174
bool isNormalMemoryOrBarrier() const
Tests if this is could be any kind of memory dependence.
Definition ScheduleDAG.h:179
bool isMustAlias() const
Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at eithe...
Definition ScheduleDAG.h:186
Definition ScheduleDAG.h:652
const SUnit * getNode() const
Definition ScheduleDAG.h:689
std::forward_iterator_tag iterator_category
Definition ScheduleDAG.h:659
unsigned getOperand() const
Definition ScheduleDAG.h:688
static SUnitIterator end(SUnit *N)
Definition ScheduleDAG.h:684
pointer operator*() const
Definition ScheduleDAG.h:670
value_type * pointer
Definition ScheduleDAG.h:662
SUnitIterator operator++(int)
Definition ScheduleDAG.h:679
value_type & reference
Definition ScheduleDAG.h:663
static SUnitIterator begin(SUnit *N)
Definition ScheduleDAG.h:683
SUnitIterator & operator++()
Definition ScheduleDAG.h:675
pointer operator->() const
Definition ScheduleDAG.h:673
bool operator==(const SUnitIterator &x) const
Definition ScheduleDAG.h:665
const SDep & getSDep() const
Definition ScheduleDAG.h:698
bool operator!=(const SUnitIterator &x) const
Definition ScheduleDAG.h:668
bool isArtificialDep() const
Definition ScheduleDAG.h:695
bool isCtrlDep() const
Tests if this is not an SDep::Data dependence.
Definition ScheduleDAG.h:692
SUnit value_type
Definition ScheduleDAG.h:660
std::ptrdiff_t difference_type
Definition ScheduleDAG.h:661
Scheduling unit. This is a node in the scheduling DAG.
Definition ScheduleDAG.h:249
bool isCloned
True if this node has been cloned.
Definition ScheduleDAG.h:308
bool isCall
Is a function call.
Definition ScheduleDAG.h:296
LLVM_ABI void setHeightToAtLeast(unsigned NewHeight)
If NewHeight is greater than this node's height value, set it to be the new height value.
bool addPredBarrier(SUnit *SU)
Adds a barrier edge to SU by calling addPred(), with latency 0 generally or latency 1 for a store fol...
Definition ScheduleDAG.h:411
unsigned NumSuccs
Definition ScheduleDAG.h:280
void setNode(SDNode *N)
Assigns the representative SDNode for this SUnit.
Definition ScheduleDAG.h:371
unsigned NumPreds
Definition ScheduleDAG.h:279
unsigned NodeQueueId
Queue id of node.
Definition ScheduleDAG.h:278
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition ScheduleDAG.h:387
unsigned TopReadyCycle
Cycle relative to start when node is ready.
Definition ScheduleDAG.h:285
SmallVectorImpl< SDep >::const_iterator const_succ_iterator
Definition ScheduleDAG.h:275
const MCSchedClassDesc * SchedClass
nullptr or resolved SchedClass.
Definition ScheduleDAG.h:262
unsigned NodeNum
Entry # of node in the node vector.
Definition ScheduleDAG.h:277
unsigned NumSuccsLeft
Definition ScheduleDAG.h:282
bool hasPhysRegClobbers
Has any physreg defs, used or not.
Definition ScheduleDAG.h:302
LLVM_ABI void biasCriticalPath()
Orders this node's predecessor edges such that the critical path edge occurs first.
bool isUnbuffered
Uses an unbuffered resource.
Definition ScheduleDAG.h:309
bool isCallOp
Is a function call operand.
Definition ScheduleDAG.h:297
const TargetRegisterClass * CopyDstRC
Is a special copy node if != nullptr.
Definition ScheduleDAG.h:265
SUnit(MachineInstr *instr, unsigned nodenum)
Constructs an SUnit for post-regalloc scheduling to represent a MachineInstr.
Definition ScheduleDAG.h:339
SmallVectorImpl< SDep >::const_iterator const_pred_iterator
Definition ScheduleDAG.h:274
unsigned getHeight() const
Returns the height of this node, which is the length of the maximum path down to any node which has n...
Definition ScheduleDAG.h:433
void setInstr(MachineInstr *MI)
Assigns the instruction for the SUnit.
Definition ScheduleDAG.h:391
LLVM_ABI void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
bool isSucc(const SUnit *N) const
Tests if node N is a successor of this node.
Definition ScheduleDAG.h:466
LLVM_ABI void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
bool isPred(const SUnit *N) const
Tests if node N is a predecessor of this node.
Definition ScheduleDAG.h:458
unsigned short Latency
Node latency.
Definition ScheduleDAG.h:312
SmallVectorImpl< SDep >::iterator pred_iterator
Definition ScheduleDAG.h:272
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
Definition ScheduleDAG.h:367
unsigned short NumRegDefsLeft
Definition ScheduleDAG.h:311
bool isScheduleHigh
True if preferable to schedule high.
Definition ScheduleDAG.h:306
bool isPending
True once pending.
Definition ScheduleDAG.h:303
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Definition ScheduleDAG.h:425
bool isScheduled
True once scheduled.
Definition ScheduleDAG.h:305
unsigned ParentClusterIdx
The parent cluster id.
Definition ScheduleDAG.h:288
bool isAvailable
True once available.
Definition ScheduleDAG.h:304
unsigned NumPredsLeft
Definition ScheduleDAG.h:281
bool isScheduleLow
True if preferable to schedule low.
Definition ScheduleDAG.h:307
bool hasPhysRegDefs
Has physreg defs that are being used.
Definition ScheduleDAG.h:301
unsigned BotReadyCycle
Cycle relative to end when node is ready.
Definition ScheduleDAG.h:286
LLVM_ABI void dumpAttributes() const
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition ScheduleDAG.h:270
Sched::Preference SchedulingPref
Scheduling preference.
Definition ScheduleDAG.h:321
SUnit(SDNode *node, unsigned nodenum)
Constructs an SUnit for pre-regalloc scheduling to represent an SDNode and any nodes flagged to it.
Definition ScheduleDAG.h:327
bool hasReservedResource
Uses a reserved resource.
Definition ScheduleDAG.h:310
unsigned WeakPredsLeft
Definition ScheduleDAG.h:283
const TargetRegisterClass * CopySrcRC
Definition ScheduleDAG.h:267
bool isBottomReady() const
Definition ScheduleDAG.h:476
SDNode * getNode() const
Returns the representative SDNode for this SUnit.
Definition ScheduleDAG.h:379
bool isTwoAddress
Is a two-address instruction.
Definition ScheduleDAG.h:298
bool isCommutable
Is a commutable instruction.
Definition ScheduleDAG.h:299
bool isVRegCycle
May use and def the same vreg.
Definition ScheduleDAG.h:295
SUnit()
Constructs a placeholder SUnit.
Definition ScheduleDAG.h:350
SDNode * Node
Representative node.
Definition ScheduleDAG.h:254
bool hasPhysRegUses
Has physreg uses.
Definition ScheduleDAG.h:300
LLVM_ABI void setDepthDirty()
Sets a flag in this node to indicate that its stored Depth value will require recomputation the next ...
MachineInstr * Instr
Alternatively, a MachineInstr.
Definition ScheduleDAG.h:255
bool isTopReady() const
Definition ScheduleDAG.h:473
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition ScheduleDAG.h:269
unsigned WeakSuccsLeft
Definition ScheduleDAG.h:284
SmallVectorImpl< SDep >::iterator succ_iterator
Definition ScheduleDAG.h:273
LLVM_ABI void setDepthToAtLeast(unsigned NewDepth)
If NewDepth is greater than this node's depth value, sets it to be the new depth value.
SUnit * OrigNode
If not this, the node from which this node was cloned.
Definition ScheduleDAG.h:259
LLVM_ABI bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition ScheduleDAG.h:399
LLVM_ABI void RemovePred(SUnit *M, SUnit *N)
Updates the topological ordering to accommodate an edge to be removed from the specified node N from ...
LLVM_ABI bool WillCreateCycle(SUnit *TargetSU, SUnit *SU)
Returns true if addPred(TargetSU, SU) creates a cycle.
void MarkDirty()
Mark the ordering as temporarily broken, after a new node has been added.
Definition ScheduleDAG.h:804
LLVM_ABI void AddSUnitWithoutPredecessors(const SUnit *SU)
Add a SUnit without predecessors to the end of the topological order.
const_reverse_iterator rbegin() const
Definition ScheduleDAG.h:816
std::vector< int >::reverse_iterator reverse_iterator
Definition ScheduleDAG.h:813
reverse_iterator rend()
Definition ScheduleDAG.h:817
LLVM_ABI ScheduleDAGTopologicalSort(std::vector< SUnit > &SUnits, SUnit *ExitSU)
iterator end()
Definition ScheduleDAG.h:810
LLVM_ABI std::vector< int > GetSubGraph(const SUnit &StartSU, const SUnit &TargetSU, bool &Success)
Returns an array of SUs that are both in the successor subtree of StartSU and in the predecessor subt...
const_iterator end() const
Definition ScheduleDAG.h:811
LLVM_ABI void InitDAGTopologicalSorting()
Creates the initial topological ordering from the DAG to be scheduled.
LLVM_ABI void AddPred(SUnit *Y, SUnit *X)
Updates the topological ordering to accommodate an edge to be added from SUnit X to SUnit Y.
std::vector< int >::const_iterator const_iterator
Definition ScheduleDAG.h:807
iterator begin()
Definition ScheduleDAG.h:808
std::vector< int >::iterator iterator
Definition ScheduleDAG.h:806
const_reverse_iterator rend() const
Definition ScheduleDAG.h:818
const_iterator begin() const
Definition ScheduleDAG.h:809
reverse_iterator rbegin()
Definition ScheduleDAG.h:815
LLVM_ABI bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
Checks if SU is reachable from TargetSU.
LLVM_ABI void AddPredQueued(SUnit *Y, SUnit *X)
Queues an update to the topological ordering to accommodate an edge to be added from SUnit X to SUnit...
std::vector< int >::const_reverse_iterator const_reverse_iterator
Definition ScheduleDAG.h:814
Definition ScheduleDAG.h:581
const MCInstrDesc * getInstrDesc(const SUnit *SU) const
Returns the MCInstrDesc of this SUnit.
Definition ScheduleDAG.h:616
MachineRegisterInfo & MRI
Virtual/real register map.
Definition ScheduleDAG.h:587
void clearDAG()
Clears the DAG state (between regions).
virtual std::string getGraphNodeLabel(const SUnit *SU) const =0
Returns a label for an SUnit node in a visualization of the ScheduleDAG.
const TargetInstrInfo * TII
Target instruction information.
Definition ScheduleDAG.h:584
virtual std::string getDAGName() const =0
Returns a label for the region of code covered by the DAG.
std::vector< SUnit > SUnits
The scheduling units.
Definition ScheduleDAG.h:588
const TargetRegisterInfo * TRI
Target processor register info.
Definition ScheduleDAG.h:585
SUnit EntrySU
Special node for the region entry.
Definition ScheduleDAG.h:589
MachineFunction & MF
Machine function.
Definition ScheduleDAG.h:586
ScheduleDAG & operator=(const ScheduleDAG &)=delete
virtual void dump() const =0
ScheduleDAG(const ScheduleDAG &)=delete
bool StressSched
Definition ScheduleDAG.h:595
const TargetMachine & TM
Target processor.
Definition ScheduleDAG.h:583
virtual void addCustomGraphFeatures(GraphWriter< ScheduleDAG * > &) const
Adds custom features for a visualization of the ScheduleDAG.
Definition ScheduleDAG.h:636
virtual void dumpNode(const SUnit &SU) const =0
void dumpNodeName(const SUnit &SU) const
SUnit ExitSU
Special node for the region exit.
Definition ScheduleDAG.h:590
void setCurCycle(unsigned Cycle)
Definition ScheduleDAG.h:572
SchedulingPriorityQueue(bool rf=false)
Definition ScheduleDAG.h:530
virtual void remove(SUnit *SU)=0
virtual bool isBottomUp() const =0
virtual void releaseState()=0
virtual void scheduledNode(SUnit *)
As each node is scheduled, this method is invoked.
Definition ScheduleDAG.h:568
virtual bool isReady(SUnit *) const
Definition ScheduleDAG.h:547
virtual bool tracksRegPressure() const
Definition ScheduleDAG.h:545
virtual void dump(ScheduleDAG *) const
Definition ScheduleDAG.h:563
bool hasReadyFilter() const
Definition ScheduleDAG.h:543
virtual void initNodes(std::vector< SUnit > &SUnits)=0
virtual ~SchedulingPriorityQueue()=default
virtual bool empty() const =0
virtual void unscheduledNode(SUnit *)
Definition ScheduleDAG.h:570
void push_all(const std::vector< SUnit * > &Nodes)
Definition ScheduleDAG.h:554
virtual void addNode(const SUnit *SU)=0
unsigned getCurCycle() const
Definition ScheduleDAG.h:576
virtual void updateNode(const SUnit *SU)=0
virtual void push(SUnit *U)=0
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
typename SuperClass::const_iterator const_iterator
typename SuperClass::iterator iterator
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
@ Success
The lock was released successfully.
constexpr unsigned InvalidClusterId
Definition ScheduleDAG.h:241
bool isTheSameCluster(unsigned A, unsigned B)
Return whether the input cluster ID's are the same and valid.
Definition ScheduleDAG.h:244
DWARFExpression::Operation Op
SmallPtrSet< SUnit *, 8 > ClusterInfo
Keep record of which SUnit are in the same cluster group.
Definition ScheduleDAG.h:240
SUnitIterator ChildIteratorType
Definition ScheduleDAG.h:705
SUnit * NodeRef
Definition ScheduleDAG.h:704
static ChildIteratorType child_begin(NodeRef N)
Definition ScheduleDAG.h:707
static NodeRef getEntryNode(SUnit *N)
Definition ScheduleDAG.h:706
static ChildIteratorType child_end(NodeRef N)
Definition ScheduleDAG.h:710
static nodes_iterator nodes_begin(ScheduleDAG *G)
Definition ScheduleDAG.h:717
static nodes_iterator nodes_end(ScheduleDAG *G)
Definition ScheduleDAG.h:720
pointer_iterator< std::vector< SUnit >::iterator > nodes_iterator
Definition ScheduleDAG.h:716
Summarize the scheduling resources required for an instruction of a particular scheduling class.