SparcISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H

15#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H

20namespace llvm {

25 public:

38 const APInt &DemandedElts,

40 unsigned Depth = 0) const override;

49 const char *constraint) const override;

51 std::vector &Ops,

54 std::pair<unsigned, const TargetRegisterClass *>

85 EVT VT) const override;

93 bool isVarArg,

98 bool isVarArg,

102

110

112 bool isVarArg,

115

121 bool IsVarArg,

126 bool IsVarArg,

130

135

140

144 const char *LibFuncName,

145 unsigned numArgs) const;

148

150

152

155

157

159 CallLoweringInfo &CLI,

161

163

164

165 return VT != MVT::f128;

166 }

167

169

171 bool ForCodeSize) const override;

172

174

178

180

182

184 EVT VT) const override;

185

190

192

193

194

195 return true;

196 }

197

199

203

205 unsigned BROpcode) const;

206

209 };

210}

211

212#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

This file describes how to lower LLVM code to machine code.

Class for arbitrary precision integers.

an instruction that atomically reads a memory location, combines it with another value,...

CCState - This class holds information needed while lowering arguments and return values.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

Common base class shared among various IRBuilders.

This is an important class for using LLVM in a threaded context.

Representation of each machine instruction.

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

Definition SparcISelLowering.h:191

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked when a node result type is illegal for the target, and the operation was reg...

SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

bool useSoftFloat() const override

SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const

MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override

Examine constraint string and operand type and determine a weight value.

AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

bool isCtlzFast() const override

Return true if ctlz instruction is fast.

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

ConstraintType getConstraintType(StringRef Constraint) const override

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const

LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition SparcISelLowering.h:175

SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

bool isCheapToSpeculateCttz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

bool IsEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

bool isFNegFree(EVT VT) const override

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...

SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const

SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const

SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const

SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const

If a physical register, this returns the register that receives the exception address on entry to an ...

Definition SparcISelLowering.h:69

Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Inserts in the IR a target-specific intrinsic specifying a fence.

void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...

SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const

SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const

If a physical register, this returns the register that receives the exception typeid on entry to a la...

Definition SparcISelLowering.h:76

SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition SparcISelLowering.h:59

SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const

SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

getSetCCResultType - Return the ISD::SETCC ValueType

bool softPromoteHalfType() const override

Definition SparcISelLowering.h:31

SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const

bool useLoadStackGuardNode(const Module &M) const override

Override to support customized stack guard loading.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const

SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const

bool ShouldShrinkFPConstant(EVT VT) const override

If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...

Definition SparcISelLowering.h:162

SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI)

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.

Return the register ID of the name passed in.

SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const

bool enableAggressiveFMAFusion(EVT VT) const override

Return true if target always benefits from combining into FMA for a given value type.

Definition SparcISelLowering.h:181

StringRef - Represent a constant reference to a string, i.e.

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

AtomicOrdering

Atomic ordering for LLVM's memory model.

DWARFExpression::Operation Op

This structure contains all information that is necessary for lowering calls.