SparcRegisterInfo.cpp Source File (original) (raw)

25using namespace llvm;

27#define GET_REGINFO_TARGET_DESC

28#include "SparcGenRegisterInfo.inc"

32 cl::desc("Reserve application registers (%g2-%g4)"));

39 return CSR_SaveList;

40}

45 return CSR_RegMask;

46}

50 return RTCSR_RegMask;

51}

64 }

66 if (!Subtarget.is64Bit())

89 if (!Subtarget.isV9()) {

90 for (unsigned n = 0; n != 16; ++n) {

93 }

94 }

97 for (unsigned n = 0; n < 31; n++)

101 i != SP::IntRegsRegClass.end(); ++i) {

104 }

105

108}

109

114

117 assert(Kind == 0 && "this should only be used for default cases");

118 return Is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;

119}

120

123 unsigned FIOperandNum, int Offset, unsigned FramePtr) {

124

126

127

128 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);

129 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);

130 return;

131 }

132

134

135

136

138

139

140

141

142 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)

144

145

146

149

150 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);

151 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));

152 return;

153 }

154

155

156

157

158

159

160 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)

162 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)

164

167

168 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);

169 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);

170}

171

172

173bool

175 int SPAdj, unsigned FIOperandNum,

177 assert(SPAdj == 0 && "Unexpected");

178

181 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

185

188 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();

189

190 Offset += MI.getOperand(FIOperandNum + 1).getImm();

191

192 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {

193 if (MI.getOpcode() == SP::STQFri) {

195 Register SrcReg = MI.getOperand(2).getReg();

196 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);

197 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);

199 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))

202 MI.setDesc(TII.get(SP::STDFri));

203 MI.getOperand(2).setReg(SrcOddReg);

205 } else if (MI.getOpcode() == SP::LDQFri) {

207 Register DestReg = MI.getOperand(0).getReg();

208 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);

209 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);

211 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)

214

215 MI.setDesc(TII.get(SP::LDDFri));

216 MI.getOperand(0).setReg(DestOddReg);

218 }

219 }

220

222

223 return false;

224}

225

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file implements the BitVector class.

uint64_t IntrinsicInst * II

static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, unsigned FramePtr)

Definition SparcRegisterInfo.cpp:121

static cl::opt< bool > ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false), cl::desc("Reserve application registers (%g2-%g4)"))

static bool is64Bit(const char *name)

static const unsigned FramePtr

MCRegAliasIterator enumerates all registers aliasing Reg.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

bool isRegisterReserved(MCPhysReg PhysReg) const

const SparcInstrInfo * getInstrInfo() const override

TargetInstrInfo - Interface to description of machine instruction set.

const MCPhysReg * iterator

virtual const TargetInstrInfo * getInstrInfo() const

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static unsigned HI22(int64_t imm)

static unsigned HIX22(int64_t imm)

static unsigned LOX10(int64_t imm)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

static unsigned LO10(int64_t imm)

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

Code Generation virtual methods...

Definition SparcRegisterInfo.cpp:38

bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

Definition SparcRegisterInfo.cpp:174

SparcRegisterInfo(const SparcSubtarget &STI)

Definition SparcRegisterInfo.cpp:34

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition SparcRegisterInfo.cpp:53

bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const

Definition SparcRegisterInfo.cpp:110

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override

Definition SparcRegisterInfo.cpp:43

const TargetRegisterClass * getPointerRegClass(unsigned Kind) const override

Definition SparcRegisterInfo.cpp:116

Definition SparcRegisterInfo.cpp:226

const uint32_t * getRTCallPreservedMask(CallingConv::ID CC) const

Definition SparcRegisterInfo.cpp:49