SparcTargetMachine.cpp Source File (original) (raw)

21#include

22using namespace llvm;

33}

37 cl::desc("Relax out of range conditional branches"));

42 Ret += "-m:e";

46 Ret += "-p:32:32";

49 Ret += "-i64:64";

53 Ret += "-i128:128";

58 Ret += "-n32:64";

59 else

60 Ret += "-f128:64-n32";

63 Ret += "-S128";

64 else

65 Ret += "-S64";

67 return Ret;

68}

72}

86 bool Is64Bit, bool JIT) {

87 if (CM) {

89 report_fatal_error("Target does not support the tiny CodeModel", false);

91 report_fatal_error("Target does not support the kernel CodeModel", false);

92 return *CM;

93 }

94 if (Is64Bit) {

95 if (JIT)

98 }

100}

101

102

106 std::optionalReloc::Model RM,

107 std::optionalCodeModel::Model CM,

109 bool is64bit)

114 JIT),

115 OL),

118}

119

121

124 Attribute CPUAttr = F.getFnAttribute("target-cpu");

125 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

126 Attribute FSAttr = F.getFnAttribute("target-features");

127

128 std::string CPU =

130 std::string TuneCPU =

132 std::string FS =

134

135

136

137

138 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();

139

140 if (softFloat)

141 FS += FS.empty() ? "+soft-float" : ",+soft-float";

142

143 auto &I = SubtargetMap[CPU + FS];

144 if () {

145

146

147

149 I = std::make_unique(CPU, TuneCPU, FS, *this,

150 this->is64Bit);

151 }

152 return I.get();

153}

154

158 return SparcMachineFunctionInfo::create(Allocator,

160}

161

162namespace {

163

165public:

168

170 return getTM();

171 }

172

173 void addIRPasses() override;

174 bool addInstSelector() override;

175 void addPreEmitPass() override;

176};

177}

178

180 return new SparcPassConfig(*this, PM);

181}

182

183void SparcPassConfig::addIRPasses() {

185

187}

188

189bool SparcPassConfig::addInstSelector() {

191 return false;

192}

193

194void SparcPassConfig::addPreEmitPass(){

195 if (BranchRelaxation)

197

203}

204

205void SparcV8TargetMachine::anchor() { }

206

210 std::optionalReloc::Model RM,

211 std::optionalCodeModel::Model CM,

214

215void SparcV9TargetMachine::anchor() { }

216

220 std::optionalReloc::Model RM,

221 std::optionalCodeModel::Model CM,

224

225void SparcelTargetMachine::anchor() {}

226

230 std::optionalReloc::Model RM,

231 std::optionalCodeModel::Model CM,

#define LLVM_EXTERNAL_VISIBILITY

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

static std::string computeDataLayout()

static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget()

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

static cl::opt< bool > BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))

static CodeModel::Model getEffectiveSparcCodeModel(std::optional< CodeModel::Model > CM, Reloc::Model RM, bool Is64Bit, bool JIT)

Target-Independent Code Generator Pass Configuration Options pass.

static bool is64Bit(const char *name)

StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

Allocate memory in an ever growing pool, as if by bump-pointer.

implements a set of functionality in the TargetMachine class for targets that make use of the indepen...

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT, bool is64bit)

Create an ILP32 architecture model.

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

const SparcSubtarget * getSubtargetImpl(const Function &F) const override

Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...

~SparcTargetMachine() override

SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

TargetSubtargetInfo - Generic base class for all target subtargets.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheSparcTarget()

void initializeSparcDAGToDAGISelLegacyPass(PassRegistry &)

char & BranchRelaxationPassID

BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

void initializeErrataWorkaroundPass(PassRegistry &)

CodeGenOptLevel

Code generation optimization level.

Target & getTheSparcV9Target()

FunctionPass * createSparcISelDag(SparcTargetMachine &TM)

createSparcISelDag - This pass converts a legalized DAG into a SPARC-specific DAG,...

Target & getTheSparcelTarget()

FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

FunctionPass * createSparcDelaySlotFillerPass()

createSparcDelaySlotFillerPass - Returns a pass that fills in delay slots in Sparc MachineFunctions

Implement std::hash so that hash_code can be used in STL containers.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

RegisterTargetMachine - Helper template for registering a target machine implementation,...