StackMaps.cpp Source File (original) (raw)

31#include

32#include

33#include

34#include

35#include

37using namespace llvm;

39#define DEBUG_TYPE "stackmaps"

43 cl::desc("Specify the stackmap encoding version (default = 3)"));

45const char *StackMaps::WSMP = "Stack Maps: ";

48 assert(MI.getOperand(Idx).isImm() &&

49 MI.getOperand(Idx).getImm() == StackMaps::ConstantOp);

50 const auto &MO = MI.getOperand(Idx + 1);

52 return MO.getImm();

53}

56 : MI(MI) {

58 "invalid stackmap definition");

59}

62 : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&

63 !MI->getOperand(0).isImplicit()) {

64#ifndef NDEBUG

65 unsigned CheckStartIdx = 0, e = MI->getNumOperands();

66 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&

67 MI->getOperand(CheckStartIdx).isDef() &&

68 !MI->getOperand(CheckStartIdx).isImplicit())

69 ++CheckStartIdx;

71 assert(getMetaIdx() == CheckStartIdx &&

72 "Unexpected additional definition in Patchpoint intrinsic.");

73#endif

74}

77 if (!StartIdx)

81 unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();

82 while (ScratchIdx < e &&

83 !(MI->getOperand(ScratchIdx).isReg() &&

84 MI->getOperand(ScratchIdx).isDef() &&

85 MI->getOperand(ScratchIdx).isImplicit() &&

86 MI->getOperand(ScratchIdx).isEarlyClobber()))

87 ++ScratchIdx;

89 assert(ScratchIdx != e && "No scratch register available");

90 return ScratchIdx;

91}

97 CurIdx++;

98 while (NumAllocas--)

100 return CurIdx + 1;

101}

102

104

107 CurIdx++;

108 while (NumGCPtrs--)

110 return CurIdx + 1;

111}

112

114

116 unsigned NumDeoptArgs = getConstMetaVal(*MI, CurIdx - 1);

117 CurIdx++;

118 while (NumDeoptArgs--) {

120 }

121 return CurIdx + 1;

122}

123

126 unsigned NumGCPtrs = getConstMetaVal(*MI, NumGCPtrsIdx - 1);

127 if (NumGCPtrs == 0)

128 return -1;

129 ++NumGCPtrsIdx;

130 assert(NumGCPtrsIdx < MI->getNumOperands());

131 return (int)NumGCPtrsIdx;

132}

133

138 CurIdx++;

139 for (unsigned N = 0; N < GCMapSize; ++N) {

140 unsigned B = MI->getOperand(CurIdx++).getImm();

141 unsigned D = MI->getOperand(CurIdx++).getImm();

142 GCMap.push_back(std::make_pair(B, D));

143 }

144

145 return GCMapSize;

146}

147

149 unsigned FoldableAreaStart = getVarIdx();

151 if (MO.getOperandNo() >= FoldableAreaStart)

152 break;

153 if (MO.isReg() && MO.getReg() == Reg)

154 return false;

155 }

156 return true;

157}

158

160 if (MI->getOpcode() != TargetOpcode::STATEPOINT)

161 return false;

163}

164

169

171 assert(CurIdx < MI->getNumOperands() && "Bad meta arg index");

172 const auto &MO = MI->getOperand(CurIdx);

173 if (MO.isImm()) {

174 switch (MO.getImm()) {

175 default:

177 case StackMaps::DirectMemRefOp:

178 CurIdx += 2;

179 break;

180 case StackMaps::IndirectMemRefOp:

181 CurIdx += 3;

182 break;

183 case StackMaps::ConstantOp:

184 ++CurIdx;

185 break;

186 }

187 }

188 ++CurIdx;

189 assert(CurIdx < MI->getNumOperands() && "points past operand list");

190 return CurIdx;

191}

192

193

195 int RegNum;

197 RegNum = TRI->getDwarfRegNum(SR, false);

198 if (RegNum >= 0)

199 break;

200 }

201

202 assert(RegNum >= 0 && isUInt<16>(RegNum) && "Invalid Dwarf register number.");

203 return (unsigned)RegNum;

204}

205

209 LiveOutVec &LiveOuts) {

210 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();

211 if (MOI->isImm()) {

212 switch (MOI->getImm()) {

213 default:

215 case StackMaps::DirectMemRefOp: {

216 auto &DL = AP.MF->getDataLayout();

217

218 unsigned Size = DL.getPointerSizeInBits();

219 assert((Size % 8) == 0 && "Need pointer size in bytes.");

225 break;

226 }

227 case StackMaps::IndirectMemRefOp: {

229 assert(Size > 0 && "Need a valid size for indirect memory locations.");

234 break;

235 }

236 case StackMaps::ConstantOp: {

237 ++MOI;

238 assert(MOI->isImm() && "Expected constant operand.");

242 } else {

243

244

245

246

247

248

249 assert((uint64_t)Imm != DenseMapInfo<uint64_t>::getEmptyKey() &&

250 (uint64_t)Imm != DenseMapInfo<uint64_t>::getTombstoneKey() &&

251 "empty and tombstone keys should fit in 32 bits!");

252 auto Result = ConstPool.insert(std::make_pair(Imm, Imm));

254 Result.first - ConstPool.begin());

255 }

256 break;

257 }

258 }

259 return ++MOI;

260 }

261

262

263

264

265

266 if (MOI->isReg()) {

267

269 return ++MOI;

270

272 "Virtreg operands should have been rewritten before now.");

273 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());

274 assert(!MOI->getSubReg() && "Physical subreg still around.");

275

278 MCRegister LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false);

279 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());

280 if (SubRegIdx)

281 Offset = TRI->getSubRegIdxOffset(SubRegIdx);

282

284 DwarfRegNum, Offset);

285 return ++MOI;

286 }

287

289 LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());

290

291 return ++MOI;

292}

293

295 const TargetRegisterInfo *TRI =

296 AP.MF ? AP.MF->getSubtarget().getRegisterInfo() : nullptr;

297 OS << WSMP << "callsites:\n";

298 for (const auto &CSI : CSInfos) {

299 const LocationVec &CSLocs = CSI.Locations;

300 const LiveOutVec &LiveOuts = CSI.LiveOuts;

301

302 OS << WSMP << "callsite " << CSI.ID << "\n";

303 OS << WSMP << " has " << CSLocs.size() << " locations\n";

304

305 unsigned Idx = 0;

306 for (const auto &Loc : CSLocs) {

307 OS << WSMP << "\t\tLoc " << Idx << ": ";

308 switch (Loc.Type) {

310 OS << "";

311 break;

313 OS << "Register ";

316 else

317 OS << Loc.Reg;

318 break;

320 OS << "Direct ";

323 else

324 OS << Loc.Reg;

325 if (Loc.Offset)

326 OS << " + " << Loc.Offset;

327 break;

329 OS << "Indirect ";

332 else

333 OS << Loc.Reg;

334 OS << "+" << Loc.Offset;

335 break;

337 OS << "Constant " << Loc.Offset;

338 break;

340 OS << "Constant Index " << Loc.Offset;

341 break;

342 }

343 OS << "\t[encoding: .byte " << Loc.Type << ", .byte 0"

344 << ", .short " << Loc.Size << ", .short " << Loc.Reg << ", .short 0"

345 << ", .int " << Loc.Offset << "]\n";

346 Idx++;

347 }

348

349 OS << WSMP << "\thas " << LiveOuts.size() << " live-out registers\n";

350

351 Idx = 0;

352 for (const auto &LO : LiveOuts) {

353 OS << WSMP << "\t\tLO " << Idx << ": ";

356 else

357 OS << LO.Reg;

358 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "

359 << LO.Size << "]\n";

360 Idx++;

361 }

362 }

363}

364

365

369 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg));

371}

372

373

374

376StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {

377 assert(Mask && "No register mask specified");

378 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();

380

381

382 for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)

383 if ((Mask[Reg / 32] >> (Reg % 32)) & 1)

384 LiveOuts.push_back(createLiveOutReg(Reg, TRI));

385

386

387

388

389

391

392 return LHS.DwarfRegNum < RHS.DwarfRegNum;

393 });

394

395 for (auto I = LiveOuts.begin(), E = LiveOuts.end(); I != E; ++I) {

396 for (auto *II = std::next(I); II != E; ++II) {

397 if (I->DwarfRegNum != II->DwarfRegNum) {

398

399 I = --II;

400 break;

401 }

402 I->Size = std::max(I->Size, II->Size);

403 if (I->Reg && TRI->isSuperRegister(I->Reg, II->Reg))

404 I->Reg = II->Reg;

405 II->Reg = 0;

406 }

407 }

408

410

411 return LiveOuts;

412}

413

414

415

416void StackMaps::parseStatepointOpers(const MachineInstr &MI,

419 LocationVec &Locations,

420 LiveOutVec &LiveOuts) {

422 StatepointOpers SO(&MI);

423 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);

424 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);

425 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);

426

427

428 unsigned NumDeoptArgs = Locations.back().Offset;

430 assert(NumDeoptArgs == SO.getNumDeoptArgs());

431

432 while (NumDeoptArgs--)

433 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);

434

435

437 ++MOI;

439 unsigned NumGCPointers = MOI->getImm();

440 ++MOI;

441 if (NumGCPointers) {

442

443 SmallVector<unsigned, 8> GCPtrIndices;

444 unsigned GCPtrIdx = (unsigned)SO.getFirstGCPtrIdx();

445 assert((int)GCPtrIdx != -1);

446 assert(MOI - MI.operands_begin() == GCPtrIdx + 0LL);

447 while (NumGCPointers--) {

448 GCPtrIndices.push_back(GCPtrIdx);

450 }

451

453 unsigned NumGCPairs = SO.getGCPointerMap(GCPairs);

454 (void)NumGCPairs;

455 LLVM_DEBUG(dbgs() << "NumGCPairs = " << NumGCPairs << "\n");

456

457 auto MOB = MI.operands_begin();

458 for (auto &P : GCPairs) {

459 assert(P.first < GCPtrIndices.size() && "base pointer index not found");

461 "derived pointer index not found");

462 unsigned BaseIdx = GCPtrIndices[P.first];

463 unsigned DerivedIdx = GCPtrIndices[P.second];

464 LLVM_DEBUG(dbgs() << "Base : " << BaseIdx << " Derived : " << DerivedIdx

465 << "\n");

466 (void)parseOperand(MOB + BaseIdx, MOE, Locations, LiveOuts);

467 (void)parseOperand(MOB + DerivedIdx, MOE, Locations, LiveOuts);

468 }

469

470 MOI = MOB + GCPtrIdx;

471 }

472

473

476 ++MOI;

477 unsigned NumAllocas = MOI->getImm();

478 ++MOI;

479 while (NumAllocas--) {

480 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);

482 }

483}

484

485void StackMaps::recordStackMapOpers(const MCSymbol &MILabel,

489 bool recordResult) {

490 MCContext &OutContext = AP.OutStreamer->getContext();

491

494

495 if (recordResult) {

496 assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");

497 parseOperand(MI.operands_begin(), std::next(MI.operands_begin()), Locations,

498 LiveOuts);

499 }

500

501

502 if (MI.getOpcode() == TargetOpcode::STATEPOINT)

503 parseStatepointOpers(MI, MOI, MOE, Locations, LiveOuts);

504 else

505 while (MOI != MOE)

506 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);

507

508

509

513

514 CSInfos.emplace_back(CSOffsetExpr, ID, std::move(Locations),

515 std::move(LiveOuts));

516

517

518 const MachineFrameInfo &MFI = AP.MF->getFrameInfo();

519 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();

520 bool HasDynamicFrameSize =

523

524 auto [CurrentIt, Inserted] = FnInfos.try_emplace(AP.CurrentFnSym, FrameSize);

525 if (!Inserted)

526 CurrentIt->second.RecordCount++;

527}

528

530 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");

531

534 recordStackMapOpers(L, MI, ID, std::next(MI.operands_begin(),

536 MI.operands_end());

537}

538

540 assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");

541

543 const int64_t ID = opers.getID();

545 recordStackMapOpers(L, MI, ID, MOI, MI.operands_end(),

547

548#ifndef NDEBUG

549

550 auto &Locations = CSInfos.back().Locations;

553 for (unsigned i = 0, e = (opers.hasDef() ? NArgs + 1 : NArgs); i != e; ++i)

555 "anyreg arg must be in reg.");

556 }

557#endif

558}

559

561 assert(MI.getOpcode() == TargetOpcode::STATEPOINT && "expected statepoint");

562

564 const unsigned StartIdx = opers.getVarIdx();

565 recordStackMapOpers(L, MI, opers.getID(), MI.operands_begin() + StartIdx,

566 MI.operands_end(), false);

567}

568

569

570

571

572

573

574

575

576

577

578

579void StackMaps::emitStackmapHeader(MCStreamer &OS) {

580

584

585

586 LLVM_DEBUG(dbgs() << WSMP << "#functions = " << FnInfos.size() << '\n');

588

589 LLVM_DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.size() << '\n');

591

592 LLVM_DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n');

594}

595

596

597

598

599

600

601

602

603void StackMaps::emitFunctionFrameRecords(MCStreamer &OS) {

604

606 for (auto const &FR : FnInfos) {

607 LLVM_DEBUG(dbgs() << WSMP << "function addr: " << FR.first

608 << " frame size: " << FR.second.StackSize

609 << " callsite count: " << FR.second.RecordCount << '\n');

613 }

614}

615

616

617

618

619void StackMaps::emitConstantPoolEntries(MCStreamer &OS) {

620

622 for (const auto &ConstEntry : ConstPool) {

623 LLVM_DEBUG(dbgs() << WSMP << ConstEntry.second << '\n');

625 }

626}

627

628

629

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631

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635

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654

655

656

657void StackMaps::emitCallsiteEntries(MCStreamer &OS) {

659

660 for (const auto &CSI : CSInfos) {

661 const LocationVec &CSLocs = CSI.Locations;

662 const LiveOutVec &LiveOuts = CSI.LiveOuts;

663

664

665

666

667

668 if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {

670 OS.emitValue(CSI.CSOffsetExpr, 4);

674 OS.emitInt16(0);

676 continue;

677 }

678

680 OS.emitValue(CSI.CSOffsetExpr, 4);

681

682

685

686 for (const auto &Loc : CSLocs) {

693 }

694

695

697

698

701

702 for (const auto &LO : LiveOuts) {

706 }

707

709 }

710}

711

712

714 (void)WSMP;

715

716 assert((!CSInfos.empty() || ConstPool.empty()) &&

717 "Expected empty constant pool too!");

718 assert((!CSInfos.empty() || FnInfos.empty()) &&

719 "Expected empty function record too!");

720 if (CSInfos.empty())

721 return;

722

723 MCContext &OutContext = AP.OutStreamer->getContext();

725

726

730

731

733

734

735 LLVM_DEBUG(dbgs() << "********** Stack Map Output **********\n");

736 emitStackmapHeader(OS);

737 emitFunctionFrameRecords(OS);

738 emitConstantPoolEntries(OS);

739 emitCallsiteEntries(OS);

741

742

743 CSInfos.clear();

744 ConstPool.clear();

745}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

This file defines DenseMapInfo traits for DenseMap.

Promote Memory to Register

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

static bool isReg(const MCInst &MI, unsigned OpNo)

uint64_t IntrinsicInst * II

static uint64_t getConstMetaVal(const MachineInstr &MI, unsigned Idx)

Definition StackMaps.cpp:47

static cl::opt< int > StackMapVersion("stackmap-version", cl::init(3), cl::Hidden, cl::desc("Specify the stackmap encoding version (default = 3)"))

static unsigned getDwarfRegNum(MCRegister Reg, const TargetRegisterInfo *TRI)

Go up the super-register chain until we hit a valid dwarf register number.

Definition StackMaps.cpp:194

This class is intended to be used as a driving class for all asm writers.

static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

Context object for machine code objects.

const MCObjectFileInfo * getObjectFileInfo() const

LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)

Lookup the symbol inside with the specified Name.

MCSection * getStackMapSection() const

Wrapper class representing physical registers. Should be passed by value.

Instances of this class represent a uniqued identifier for a section in the current translation unit.

Streaming machine code generation interface.

virtual void addBlankLine()

Emit a blank line to a .s file to pretty it up.

void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())

void emitSymbolValue(const MCSymbol *Sym, unsigned Size, bool IsSectionRelative=false)

Special case of EmitValue that avoids the client having to pass in a MCExpr for MCSymbols.

virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())

Emit a label for Symbol into the current section.

virtual void emitValueToAlignment(Align Alignment, int64_t Fill=0, uint8_t FillLen=1, unsigned MaxBytesToEmit=0)

Emit some number of copies of Value until the byte alignment ByteAlignment is reached.

virtual void emitIntValue(uint64_t Value, unsigned Size)

Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.

void emitInt16(uint64_t Value)

virtual void switchSection(MCSection *Section, uint32_t Subsec=0)

Set the current section where code is being emitted to Section.

void emitInt32(uint64_t Value)

static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

bool hasVarSizedObjects() const

This method may be called any time after instruction selection is complete to determine if the stack ...

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

Representation of each machine instruction.

const MachineOperand * const_mop_iterator

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

const uint32_t * getRegLiveOut() const

getRegLiveOut - Returns a bit mask of live-out registers.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

bool isRegLiveOut() const

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

getReg - Returns the register number.

MI-level patchpoint operands.

uint32_t getNumCallArgs() const

Return the number of call arguments.

LLVM_ABI PatchPointOpers(const MachineInstr *MI)

Definition StackMaps.cpp:61

LLVM_ABI unsigned getNextScratchIdx(unsigned StartIdx=0) const

Get the next scratch register operand index.

Definition StackMaps.cpp:76

uint64_t getID() const

Return the ID for the given patchpoint.

unsigned getStackMapStartIdx() const

Get the index at which stack map locations will be recorded.

unsigned getVarIdx() const

Get the operand index of the variable list of non-argument operands.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

MI-level stackmap operands.

LLVM_ABI StackMapOpers(const MachineInstr *MI)

Definition StackMaps.cpp:55

unsigned getVarIdx() const

Get the operand index of the variable list of non-argument operands.

static LLVM_ABI unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)

Get index of next meta operand.

Definition StackMaps.cpp:170

LLVM_ABI StackMaps(AsmPrinter &AP)

Definition StackMaps.cpp:165

LLVM_ABI void serializeToStackMapSection()

If there is any stack map data, create a stack map section and serialize the map info into it.

Definition StackMaps.cpp:713

SmallVector< LiveOutReg, 8 > LiveOutVec

SmallVector< Location, 8 > LocationVec

LLVM_ABI void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)

Generate a stackmap record for a statepoint instruction.

Definition StackMaps.cpp:560

LLVM_ABI void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)

Generate a stackmap record for a patchpoint instruction.

Definition StackMaps.cpp:539

LLVM_ABI void recordStackMap(const MCSymbol &L, const MachineInstr &MI)

Generate a stackmap record for a stackmap instruction.

Definition StackMaps.cpp:529

MI-level Statepoint operands.

StatepointOpers(const MachineInstr *MI)

LLVM_ABI unsigned getGCPointerMap(SmallVectorImpl< std::pair< unsigned, unsigned > > &GCMap)

Get vector of base/derived pairs from statepoint.

Definition StackMaps.cpp:134

LLVM_ABI unsigned getNumAllocaIdx()

Get index of number of gc allocas.

Definition StackMaps.cpp:103

LLVM_ABI unsigned getNumGcMapEntriesIdx()

Get index of number of gc map entries.

Definition StackMaps.cpp:93

LLVM_ABI int getFirstGCPtrIdx()

Get index of first GC pointer operand of -1 if there are none.

Definition StackMaps.cpp:124

unsigned getNumDeoptArgsIdx() const

Get index of Number Deopt Arguments operand.

uint64_t getID() const

Return the ID for the given statepoint.

LLVM_ABI bool isFoldableReg(Register Reg) const

Return true if Reg is used only in operands which can be folded to stack usage.

Definition StackMaps.cpp:148

unsigned getVarIdx() const

Get starting index of non call related arguments (calling convention, statepoint flags,...

LLVM_ABI unsigned getNumGCPtrIdx()

Get index of number of GC pointers.

Definition StackMaps.cpp:113

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

bool hasStackRealignment(const MachineFunction &MF) const

True if stack realignment is required and still possible.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

void sort(IteratorTy Start, IteratorTy End)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

void erase_if(Container &C, UnaryPredicate P)

Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.