SystemZInstrInfo.cpp Source File (original) (raw)

42#include

43#include

44#include

46using namespace llvm;

48#define GET_INSTRINFO_CTOR_DTOR

49#define GET_INSTRMAP_INFO

50#include "SystemZGenInstrInfo.inc"

52#define DEBUG_TYPE "systemz-II"

60void SystemZInstrInfo::anchor() {}

64 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister(),

65 sti.getHwMode()),

66 STI(sti) {}

71 unsigned NewOpcode) const {

77 MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);

79 MBB->insert(LowPartMI, HighPartMI);

87 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));

88 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));

99 assert(HighOpcode && LowOpcode && "Both offsets should be in range");

100 HighPartMI->setDesc(get(HighOpcode));

102

104 if (MI->mayStore()) {

106

107

108

109

113 } else {

114

115

116 auto overlapsAddressReg = [&](Register Reg) -> bool {

117 return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||

118 RI.regsOverlap(Reg, MI->getOperand(3).getReg());

119 };

120 if (overlapsAddressReg(HighRegOp.getReg())) {

121 assert(!overlapsAddressReg(LowRegOp.getReg()) &&

122 "Both loads clobber address!");

124 FirstMI = LowPartMI;

125 }

126 }

127

128

131}

132

133

135 MachineBasicBlock *MBB = MI->getParent();

137 MachineFrameInfo &MFFrame = MF.getFrameInfo();

138 MachineOperand &OffsetMO = MI->getOperand(2);

139 SystemZCallingConventionRegisters *Regs = STI.getSpecialRegisters();

140

146 assert(NewOpcode && "No support for huge argument lists yet");

147 MI->setDesc(get(NewOpcode));

149}

150

151

152

153

154

155

156

157void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,

158 unsigned HighOpcode,

159 bool ConvertHigh) const {

162 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));

163 if (IsHigh && ConvertHigh)

164 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));

165}

166

167

168

169

170

171void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,

172 unsigned LowOpcodeK,

173 unsigned HighOpcode) const {

174 Register DestReg = MI.getOperand(0).getReg();

175 Register SrcReg = MI.getOperand(1).getReg();

178 if (!DestIsHigh && !SrcIsHigh)

179 MI.setDesc(get(LowOpcodeK));

180 else {

181 if (DestReg != SrcReg) {

182 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,

183 SystemZ::LR, 32, MI.getOperand(1).isKill(),

184 MI.getOperand(1).isUndef());

185 MI.getOperand(1).setReg(DestReg);

186 }

187 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));

188 MI.tieOperands(0, 1);

189 }

190}

191

192

193

194

195void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,

196 unsigned HighOpcode) const {

200 MI.getOperand(2).getImm());

201 MI.setDesc(get(Opcode));

202}

203

204

205

206

207void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,

208 unsigned HighOpcode) const {

211 MI.setDesc(get(Opcode));

212}

213

214

215

216

217void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,

218 unsigned Size) const {

219 MachineInstrBuilder MIB =

220 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),

221 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,

222 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());

223

224

226 MIB.add(MO);

227

228 MI.eraseFromParent();

229}

230

231void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {

232 MachineBasicBlock *MBB = MI->getParent();

234 const Register Reg64 = MI->getOperand(0).getReg();

235 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);

236

237

238

239

240

244

245

250

251

253 .addReg(SystemZ::A1);

254

255

256 MI->setDesc(get(SystemZ::LG));

257 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);

258}

259

260

261

262

263

264

268 const DebugLoc &DL, unsigned DestReg,

269 unsigned SrcReg, unsigned LowLowOpcode,

270 unsigned Size, bool KillSrc,

271 bool UndefSrc) const {

272 unsigned Opcode;

275 if (DestIsHigh && SrcIsHigh)

276 Opcode = SystemZ::RISBHH;

277 else if (DestIsHigh && !SrcIsHigh)

278 Opcode = SystemZ::RISBHL;

279 else if (!DestIsHigh && SrcIsHigh)

280 Opcode = SystemZ::RISBLH;

281 else {

284 }

285 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);

290}

291

293 bool NewMI,

294 unsigned OpIdx1,

295 unsigned OpIdx2) const {

297 if (NewMI)

298 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);

299 return MI;

300 };

301

302 switch (MI.getOpcode()) {

303 case SystemZ::SELRMux:

304 case SystemZ::SELFHR:

305 case SystemZ::SELR:

306 case SystemZ::SELGR:

307 case SystemZ::LOCRMux:

308 case SystemZ::LOCFHR:

309 case SystemZ::LOCR:

310 case SystemZ::LOCGR: {

311 auto &WorkingMI = cloneIfNew(MI);

312

313 unsigned CCValid = WorkingMI.getOperand(3).getImm();

314 unsigned CCMask = WorkingMI.getOperand(4).getImm();

315 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);

317 OpIdx1, OpIdx2);

318 }

319 default:

321 }

322}

323

324

325

326

327

328

330 unsigned Flag) {

332 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&

333 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {

334 FrameIndex = MI.getOperand(1).getIndex();

335 return MI.getOperand(0).getReg();

336 }

337 return 0;

338}

339

341 int &FrameIndex) const {

343}

344

346 int &FrameIndex) const {

348}

349

351 int &FrameIndex) const {

352

353

356 return 0;

357

358

359

360 assert(.getOperand(1).isFI());

361

362

364 if (hasLoadFromStackSlot(MI, Accesses)) {

365 FrameIndex =

367 ->getFrameIndex();

368 return MI.getOperand(0).getReg();

369 }

370 return 0;

371}

372

374 int &FrameIndex) const {

375

376

379 return 0;

380

381

382

383 assert(.getOperand(1).isFI());

384

385

387 if (hasStoreToStackSlot(MI, Accesses)) {

388 FrameIndex =

390 ->getFrameIndex();

391 return MI.getOperand(0).getReg();

392 }

393 return 0;

394}

395

397 int &DestFrameIndex,

398 int &SrcFrameIndex) const {

399

400 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();

401 if (MI.getOpcode() != SystemZ::MVC || .getOperand(0).isFI() ||

402 MI.getOperand(1).getImm() != 0 || .getOperand(3).isFI() ||

403 MI.getOperand(4).getImm() != 0)

404 return false;

405

406

407 int64_t Length = MI.getOperand(2).getImm();

408 unsigned FI1 = MI.getOperand(0).getIndex();

409 unsigned FI2 = MI.getOperand(3).getIndex();

412 return false;

413

414 DestFrameIndex = FI1;

415 SrcFrameIndex = FI2;

416 return true;

417}

418

423 bool AllowModify) const {

424

425

426

427

429 while (I != MBB.begin()) {

430 --I;

431 if (I->isDebugInstr())

432 continue;

433

434

435

436 if (!isUnpredicatedTerminator(*I))

437 break;

438

439

440

441 if (->isBranch())

442 return true;

443

444

446 if (!Branch.hasMBBTarget())

447 return true;

448

449

451 return true;

452

454

455 if (!AllowModify) {

456 TBB = Branch.getMBBTarget();

457 continue;

458 }

459

460

461 MBB.erase(std::next(I), MBB.end());

462

463 Cond.clear();

464 FBB = nullptr;

465

466

467 if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {

468 TBB = nullptr;

469 I->eraseFromParent();

470 I = MBB.end();

471 continue;

472 }

473

474

475 TBB = Branch.getMBBTarget();

476 continue;

477 }

478

479

480 if (Cond.empty()) {

481

482 FBB = TBB;

483 TBB = Branch.getMBBTarget();

486 continue;

487 }

488

489

490 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");

491

492

493

494 if (TBB != Branch.getMBBTarget())

495 return true;

496

497

498 unsigned OldCCValid = Cond[0].getImm();

499 unsigned OldCCMask = Cond[1].getImm();

500 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)

501 continue;

502

503

504 return false;

505 }

506

507 return false;

508}

509

511 int *BytesRemoved) const {

512 assert(!BytesRemoved && "code size not handled");

513

514

516 unsigned Count = 0;

517

518 while (I != MBB.begin()) {

519 --I;

520 if (I->isDebugInstr())

521 continue;

522 if (->isBranch())

523 break;

525 break;

526

527 I->eraseFromParent();

528 I = MBB.end();

530 }

531

533}

534

537 assert(Cond.size() == 2 && "Invalid condition");

539 return false;

540}

541

547 int *BytesAdded) const {

548

549

550

551

552

553 assert(TBB && "insertBranch must not be told to insert a fallthrough");

555 "SystemZ branch conditions have one component!");

556 assert(!BytesAdded && "code size not handled");

557

558 if (Cond.empty()) {

559

560 assert(!FBB && "Unconditional branch with multiple successors!");

562 return 1;

563 }

564

565

566 unsigned Count = 0;

567 unsigned CCValid = Cond[0].getImm();

568 unsigned CCMask = Cond[1].getImm();

572

573 if (FBB) {

574

577 }

579}

580

582 Register &SrcReg2, int64_t &Mask,

583 int64_t &Value) const {

584 assert(MI.isCompare() && "Caller should have checked for a comparison");

585

586 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&

587 MI.getOperand(1).isImm()) {

588 SrcReg = MI.getOperand(0).getReg();

589 SrcReg2 = 0;

590 Value = MI.getOperand(1).getImm();

591 Mask = ~0;

592 return true;

593 }

594

595 return false;

596}

597

601 Register FalseReg, int &CondCycles,

602 int &TrueCycles,

603 int &FalseCycles) const {

604

605 if (!STI.hasLoadStoreOnCond())

606 return false;

607 if (Pred.size() != 2)

608 return false;

609

610

613 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));

614 if (!RC)

615 return false;

616

617

618 if ((STI.hasLoadStoreOnCond2() &&

619 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||

620 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||

621 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {

622 CondCycles = 2;

623 TrueCycles = 2;

624 FalseCycles = 2;

625 return true;

626 }

627

628

629 return false;

630}

631

640

641 assert(Pred.size() == 2 && "Invalid condition");

642 unsigned CCValid = Pred[0].getImm();

643 unsigned CCMask = Pred[1].getImm();

644

645 unsigned Opc;

646 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {

647 if (STI.hasMiscellaneousExtensions3())

648 Opc = SystemZ::SELRMux;

649 else if (STI.hasLoadStoreOnCond2())

650 Opc = SystemZ::LOCRMux;

651 else {

652 Opc = SystemZ::LOCR;

653 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);

654 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);

655 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);

658 TrueReg = TReg;

659 FalseReg = FReg;

660 }

661 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {

662 if (STI.hasMiscellaneousExtensions3())

663 Opc = SystemZ::SELGR;

664 else

665 Opc = SystemZ::LOCGR;

666 } else

668

672}

673

677 unsigned DefOpc = DefMI.getOpcode();

678

679 if (DefOpc == SystemZ::VGBM) {

680 int64_t ImmVal = DefMI.getOperand(1).getImm();

681 if (ImmVal != 0)

682 return false;

683

684

685

686

687

688 assert(DefMI.getOperand(0).getReg() == Reg);

689

690 if ( UseMI .isCopy())

691 return false;

692

693 Register CopyDstReg = UseMI.getOperand(0).getReg();

695 MRI->getRegClass(CopyDstReg) == &SystemZ::GR128BitRegClass &&

696 MRI->hasOneNonDBGUse(Reg)) {

697

698

699

700 Register TmpReg = MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);

702

704

705 UseMI.setDesc(get(SystemZ::REG_SEQUENCE));

706 UseMI.getOperand(1).setReg(TmpReg);

708 .addImm(SystemZ::subreg_h64)

710 .addImm(SystemZ::subreg_l64);

711

712 if (MRI->use_nodbg_empty(Reg))

713 DefMI.eraseFromParent();

714 return true;

715 }

716

717 return false;

718 }

719

720 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&

721 DefOpc != SystemZ::LGHI)

722 return false;

723 if (DefMI.getOperand(0).getReg() != Reg)

724 return false;

725 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();

726

727 unsigned UseOpc = UseMI.getOpcode();

728 unsigned NewUseOpc;

729 unsigned UseIdx;

730 int CommuteIdx = -1;

731 bool TieOps = false;

732 switch (UseOpc) {

733 case SystemZ::SELRMux:

734 TieOps = true;

735 [[fallthrough]];

736 case SystemZ::LOCRMux:

737 if (!STI.hasLoadStoreOnCond2())

738 return false;

739 NewUseOpc = SystemZ::LOCHIMux;

740 if (UseMI.getOperand(2).getReg() == Reg)

741 UseIdx = 2;

742 else if (UseMI.getOperand(1).getReg() == Reg)

743 UseIdx = 2, CommuteIdx = 1;

744 else

745 return false;

746 break;

747 case SystemZ::SELGR:

748 TieOps = true;

749 [[fallthrough]];

750 case SystemZ::LOCGR:

751 if (!STI.hasLoadStoreOnCond2())

752 return false;

753 NewUseOpc = SystemZ::LOCGHI;

754 if (UseMI.getOperand(2).getReg() == Reg)

755 UseIdx = 2;

756 else if (UseMI.getOperand(1).getReg() == Reg)

757 UseIdx = 2, CommuteIdx = 1;

758 else

759 return false;

760 break;

761 default:

762 return false;

763 }

764

765 if (CommuteIdx != -1)

766 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))

767 return false;

768

769 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);

770 UseMI.setDesc(get(NewUseOpc));

771 if (TieOps)

772 UseMI.tieOperands(0, 1);

773 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);

774 if (DeleteDef)

775 DefMI.eraseFromParent();

776

777 return true;

778}

779

781 unsigned Opcode = MI.getOpcode();

782 if (Opcode == SystemZ::Return ||

783 Opcode == SystemZ::Return_XPLINK ||

784 Opcode == SystemZ::Trap ||

785 Opcode == SystemZ::CallJG ||

786 Opcode == SystemZ::CallBR)

787 return true;

788 return false;

789}

790

793 unsigned NumCycles, unsigned ExtraPredCycles,

795

796

797

798

799

800

801

802

803 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&

805 return false;

806

807 return NumCycles == 1;

808}

809

812 unsigned NumCyclesT, unsigned ExtraPredCyclesT,

814 unsigned NumCyclesF, unsigned ExtraPredCyclesF,

816

817 return false;

818}

819

823

824 return NumCycles == 1;

825}

826

829 assert(Pred.size() == 2 && "Invalid condition");

830 unsigned CCValid = Pred[0].getImm();

831 unsigned CCMask = Pred[1].getImm();

832 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");

833 unsigned Opcode = MI.getOpcode();

834 if (Opcode == SystemZ::Trap) {

835 MI.setDesc(get(SystemZ::CondTrap));

839 return true;

840 }

841 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {

842 MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn

843 : SystemZ::CondReturn_XPLINK));

848 return true;

849 }

850 if (Opcode == SystemZ::CallJG) {

852 const uint32_t *RegMask = MI.getOperand(1).getRegMask();

853 MI.removeOperand(1);

854 MI.removeOperand(0);

855 MI.setDesc(get(SystemZ::CallBRCL));

859 .add(FirstOp)

862 return true;

863 }

864 if (Opcode == SystemZ::CallBR) {

866 const uint32_t *RegMask = MI.getOperand(1).getRegMask();

867 MI.removeOperand(1);

868 MI.removeOperand(0);

869 MI.setDesc(get(SystemZ::CallBCR));

875 return true;

876 }

877 return false;

878}

879

883 Register SrcReg, bool KillSrc,

884 bool RenamableDest,

885 bool RenamableSrc) const {

886

887

888

889 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {

891 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);

895 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);

898 return;

899 }

900

901 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {

902 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,

903 false);

904 return;

905 }

906

907

908 if (SystemZ::VR128BitRegClass.contains(DestReg) &&

909 SystemZ::FP128BitRegClass.contains(SrcReg)) {

911 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),

912 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

914 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),

915 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

916

920 return;

921 }

922 if (SystemZ::FP128BitRegClass.contains(DestReg) &&

923 SystemZ::VR128BitRegClass.contains(SrcReg)) {

925 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),

926 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

928 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),

929 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

930

931 if (DestRegHi != SrcReg.asMCReg())

935 return;

936 }

937

938 if (SystemZ::FP128BitRegClass.contains(DestReg) &&

939 SystemZ::GR128BitRegClass.contains(SrcReg)) {

940 MCRegister DestRegHi = RI.getSubReg(DestReg, SystemZ::subreg_h64);

941 MCRegister DestRegLo = RI.getSubReg(DestReg, SystemZ::subreg_l64);

942 MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64);

943 MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64);

944

948

951 return;

952 }

953

954

955 if (DestReg == SystemZ::CC) {

956 unsigned Opcode =

957 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;

961 return;

962 }

963

964 if (SystemZ::GR128BitRegClass.contains(DestReg) &&

965 SystemZ::VR128BitRegClass.contains(SrcReg)) {

966 MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64);

967 MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64);

968

971 .addReg(SystemZ::NoRegister)

976 .addReg(SystemZ::NoRegister)

978 return;

979 }

980

981 if (SystemZ::VR128BitRegClass.contains(DestReg) &&

982 SystemZ::GR128BitRegClass.contains(SrcReg)) {

984 .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64))

985 .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64));

986 return;

987 }

988

989

990 unsigned Opcode;

991 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))

992 Opcode = SystemZ::LGR;

993 else if (SystemZ::FP16BitRegClass.contains(DestReg, SrcReg))

994 Opcode = STI.hasVector() ? SystemZ::LDR16 : SystemZ::LER16;

995 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))

996

997 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;

998 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))

999 Opcode = SystemZ::LDR;

1000 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))

1001 Opcode = SystemZ::LXR;

1002 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))

1003 Opcode = SystemZ::VLR32;

1004 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))

1005 Opcode = SystemZ::VLR64;

1006 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))

1007 Opcode = SystemZ::VLR;

1008 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))

1009 Opcode = SystemZ::CPYA;

1010 else if (SystemZ::GR64BitRegClass.contains(DestReg) &&

1011 SystemZ::FP64BitRegClass.contains(SrcReg))

1012 Opcode = SystemZ::LGDR;

1013 else if (SystemZ::FP64BitRegClass.contains(DestReg) &&

1014 SystemZ::GR64BitRegClass.contains(SrcReg))

1015 Opcode = SystemZ::LDGR;

1016 else

1018

1021}

1022

1026

1029

1030

1031

1032 unsigned LoadOpcode, StoreOpcode;

1036 FrameIdx);

1037}

1038

1041 Register DestReg, int FrameIdx,

1046

1047

1048

1049 unsigned LoadOpcode, StoreOpcode;

1052 FrameIdx);

1053}

1054

1055

1056

1059 return ((MCID.TSFlags & Flag) &&

1061 MI->getOperand(3).getReg() == 0);

1062}

1063

1064namespace {

1065

1066struct LogicOp {

1067 LogicOp() = default;

1068 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)

1069 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}

1070

1071 explicit operator bool() const { return RegSize; }

1072

1074 unsigned ImmLSB = 0;

1075 unsigned ImmSize = 0;

1076};

1077

1078}

1079

1081 switch (Opcode) {

1082 case SystemZ::NILMux: return LogicOp(32, 0, 16);

1083 case SystemZ::NIHMux: return LogicOp(32, 16, 16);

1084 case SystemZ::NILL64: return LogicOp(64, 0, 16);

1085 case SystemZ::NILH64: return LogicOp(64, 16, 16);

1086 case SystemZ::NIHL64: return LogicOp(64, 32, 16);

1087 case SystemZ::NIHH64: return LogicOp(64, 48, 16);

1088 case SystemZ::NIFMux: return LogicOp(32, 0, 32);

1089 case SystemZ::NILF64: return LogicOp(64, 0, 32);

1090 case SystemZ::NIHF64: return LogicOp(64, 32, 32);

1091 default: return LogicOp();

1092 }

1093}

1094

1099 if (CCDef != nullptr)

1101 }

1102}

1103

1106 if (OldMI->getFlag(Flag))

1108}

1109

1114

1115

1116

1118 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;

1119

1121 unsigned Start, End;

1123 unsigned NewOpcode;

1124 if (And.RegSize == 64) {

1125 NewOpcode = SystemZ::RISBG;

1126

1127 if (STI.hasMiscellaneousExtensions())

1128 NewOpcode = SystemZ::RISBGN;

1129 } else {

1130 NewOpcode = SystemZ::RISBMux;

1131 Start &= 31;

1132 End &= 31;

1133 }

1138 .add(Dest)

1141 Src.getSubReg())

1145 if (LV) {

1146 unsigned NumOps = MI.getNumOperands();

1147 for (unsigned I = 1; I < NumOps; ++I) {

1149 if (Op.isReg() && Op.isKill())

1151 }

1152 }

1153 if (LIS)

1156 return MIB;

1157 }

1158 }

1159 return nullptr;

1160}

1161

1163 bool Invert) const {

1165 if (Invert) {

1167 if (!InverseOpcode)

1168 return false;

1169 Opc = *InverseOpcode;

1170 }

1171

1172 switch (Opc) {

1173 default:

1174 break;

1175

1176 case SystemZ::WFADB:

1177 case SystemZ::WFASB:

1178 case SystemZ::WFAXB:

1179 case SystemZ::VFADB:

1180 case SystemZ::VFASB:

1181 case SystemZ::WFMDB:

1182 case SystemZ::WFMSB:

1183 case SystemZ::WFMXB:

1184 case SystemZ::VFMDB:

1185 case SystemZ::VFMSB:

1188 }

1189

1190 return false;

1191}

1192

1193std::optional

1195

1196 switch (Opcode) {

1197 case SystemZ::WFADB:

1198 return SystemZ::WFSDB;

1199 case SystemZ::WFASB:

1200 return SystemZ::WFSSB;

1201 case SystemZ::WFAXB:

1202 return SystemZ::WFSXB;

1203 case SystemZ::VFADB:

1204 return SystemZ::VFSDB;

1205 case SystemZ::VFASB:

1206 return SystemZ::VFSSB;

1207

1208 case SystemZ::WFSDB:

1209 return SystemZ::WFADB;

1210 case SystemZ::WFSSB:

1211 return SystemZ::WFASB;

1212 case SystemZ::WFSXB:

1213 return SystemZ::WFAXB;

1214 case SystemZ::VFSDB:

1215 return SystemZ::VFADB;

1216 case SystemZ::VFSSB:

1217 return SystemZ::VFASB;

1218 default:

1219 return std::nullopt;

1220 }

1221}

1222

1231 unsigned Opcode = MI.getOpcode();

1232

1233

1235 LiveRange *CCLiveRange = nullptr;

1236 bool CCLiveAtMI = true;

1237 if (LIS) {

1240 assert(range_size(CCUnits) == 1 && "CC only has one reg unit.");

1241 CCLiveRange = &LIS->getRegUnit(*CCUnits.begin());

1242 CCLiveAtMI = CCLiveRange->liveAt(MISlot);

1243 }

1244

1245 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {

1246 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&

1247 isInt<8>(MI.getOperand(2).getImm()) && .getOperand(3).getReg()) {

1248

1250 MI.getDebugLoc(), get(SystemZ::AGSI))

1253 .addImm(MI.getOperand(2).getImm());

1257 return BuiltMI;

1258 }

1259 return nullptr;

1260 }

1261

1262

1263 if (Ops.size() != 1)

1264 return nullptr;

1265

1266 unsigned OpNum = Ops[0];

1269 assert((Size * 8 == TRI->getRegSizeInBits(*RC) ||

1270 (RC == &SystemZ::FP16BitRegClass && Size == 4 && !STI.hasVector())) &&

1271 "Invalid size combination");

1272 (void)RC;

1273

1274 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&

1275 isInt<8>(MI.getOperand(2).getImm())) {

1276

1277 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);

1279 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))

1282 .addImm(MI.getOperand(2).getImm());

1285 return BuiltMI;

1286 }

1287

1288 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&

1289 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||

1290 (Opcode == SystemZ::ALGFI && OpNum == 0 &&

1291 isInt<8>(MI.getOperand(2).getImm()))) {

1292

1293 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);

1295 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))

1298 .addImm((int8_t)MI.getOperand(2).getImm());

1300 return BuiltMI;

1301 }

1302

1303 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&

1304 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||

1305 (Opcode == SystemZ::SLGFI && OpNum == 0 &&

1306 isInt<8>((-MI.getOperand(2).getImm())))) {

1307

1308 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);

1310 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))

1313 .addImm((int8_t)-MI.getOperand(2).getImm());

1315 return BuiltMI;

1316 }

1317

1318 unsigned MemImmOpc = 0;

1319 switch (Opcode) {

1320 case SystemZ::LHIMux:

1321 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;

1322 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;

1323 case SystemZ::CHIMux:

1324 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;

1325 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;

1326 case SystemZ::CLFIMux:

1327 case SystemZ::CLFI:

1329 MemImmOpc = SystemZ::CLFHSI;

1330 break;

1331 case SystemZ::CLGFI:

1333 MemImmOpc = SystemZ::CLGHSI;

1334 break;

1335 default: break;

1336 }

1337 if (MemImmOpc)

1338 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1339 get(MemImmOpc))

1342 .addImm(MI.getOperand(1).getImm());

1343

1344 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {

1345 bool Op0IsGPR = (Opcode == SystemZ::LGDR);

1346 bool Op1IsGPR = (Opcode == SystemZ::LDGR);

1347

1348

1349 if (OpNum == 0) {

1350 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;

1351 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1352 get(StoreOpcode))

1353 .add(MI.getOperand(1))

1357 }

1358

1359

1360 if (OpNum == 1) {

1361 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;

1362 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1363 get(LoadOpcode))

1364 .add(MI.getOperand(0))

1368 }

1369 }

1370

1371

1372

1373

1374

1375

1376

1377

1378

1379

1380

1381

1382

1383

1384 if (OpNum == 0 && MI.hasOneMemOperand()) {

1387

1389 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1390 get(SystemZ::MVC))

1394 .add(MI.getOperand(1))

1395 .addImm(MI.getOperand(2).getImm())

1397 }

1398

1400 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1401 get(SystemZ::MVC))

1402 .add(MI.getOperand(1))

1403 .addImm(MI.getOperand(2).getImm())

1408 }

1409 }

1410 }

1411

1412

1413

1414

1415 unsigned NumOps = MI.getNumExplicitOperands();

1416 int MemOpcode = SystemZ::getMemOpcode(Opcode);

1417 if (MemOpcode == -1 ||

1418 (CCLiveAtMI && .definesRegister(SystemZ::CC, nullptr) &&

1419 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))

1420 return nullptr;

1421

1422

1423

1425 for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {

1428 continue;

1430 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {

1431 Register Reg = MI.getOperand(I).getReg();

1434 : Reg;

1435 if (!PhysReg ||

1436 !(SystemZ::FP32BitRegClass.contains(PhysReg) ||

1437 SystemZ::FP64BitRegClass.contains(PhysReg) ||

1438 SystemZ::VF128BitRegClass.contains(PhysReg)))

1439 return nullptr;

1440 }

1441 }

1442

1443 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||

1444 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);

1445 if (FusedFPOp) {

1448 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)

1449 return nullptr;

1450 }

1451

1452

1453 bool NeedsCommute = false;

1454 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||

1455 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||

1456 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||

1457 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&

1459 NeedsCommute = true;

1460

1461 bool CCOperands = false;

1462 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||

1463 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {

1465 "LOCR/SELR instruction operands corrupt?");

1467 CCOperands = true;

1468 }

1469

1470

1471

1472

1474 if (VRM == nullptr)

1475 return nullptr;

1476 else {

1477 Register DstReg = MI.getOperand(0).getReg();

1481 : ((OpNum == 1 && MI.isCommutable())

1482 ? MI.getOperand(2).getReg()

1484 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&

1486 NeedsCommute = (OpNum == 1);

1487 else

1488 return nullptr;

1489 }

1490 }

1491

1492 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {

1495 assert(AccessBytes != 0 && "Size of access should be known");

1496 assert(AccessBytes <= Size && "Access outside the frame index");

1499 MI.getDebugLoc(), get(MemOpcode));

1500 if (MI.isCompare()) {

1501 assert(NumOps == 2 && "Expected 2 register operands for a compare.");

1502 MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));

1503 }

1504 else if (FusedFPOp) {

1505 MIB.add(MI.getOperand(0));

1506 MIB.add(MI.getOperand(3));

1507 MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));

1508 }

1509 else {

1510 MIB.add(MI.getOperand(0));

1511 if (NeedsCommute)

1512 MIB.add(MI.getOperand(2));

1513 else

1514 for (unsigned I = 1; I < OpNum; ++I)

1515 MIB.add(MI.getOperand(I));

1516 }

1520 if (CCOperands) {

1521 unsigned CCValid = MI.getOperand(NumOps).getImm();

1522 unsigned CCMask = MI.getOperand(NumOps + 1).getImm();

1523 MIB.addImm(CCValid);

1524 MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);

1525 }

1526 if (MIB->definesRegister(SystemZ::CC, nullptr) &&

1527 (.definesRegister(SystemZ::CC, nullptr) ||

1528 MI.registerDefIsDead(SystemZ::CC, nullptr))) {

1530 if (CCLiveRange)

1532 }

1533

1534

1536 if (MO.isReg() && MO.getReg().isVirtual()) {

1538 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)

1539 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);

1540 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)

1541 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);

1542 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)

1543 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);

1544 }

1545

1549 return MIB;

1550 }

1551

1552 return nullptr;

1553}

1554

1561

1562

1563

1564

1565

1566

1567

1568 unsigned LoadOpc = 0;

1569 unsigned RegMemOpcode = 0;

1571 RegMemOpcode = MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB

1572 : MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB

1573 : MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB

1574 : 0;

1575 if (RegMemOpcode) {

1576 LoadOpc = SystemZ::VL64;

1577 FPRC = &SystemZ::FP64BitRegClass;

1578 } else {

1579 RegMemOpcode = MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB

1580 : MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB

1581 : MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB

1582 : 0;

1583 if (RegMemOpcode) {

1584 LoadOpc = SystemZ::VL32;

1585 FPRC = &SystemZ::FP32BitRegClass;

1586 }

1587 }

1588 if (!RegMemOpcode || LoadMI.getOpcode() != LoadOpc)

1589 return nullptr;

1590

1591

1592 if (get(RegMemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)) {

1593 assert(LoadMI.getParent() == MI.getParent() && "Assuming a local fold.");

1594 assert(LoadMI != InsertPt && "Assuming InsertPt not to be first in MBB.");

1596 --MII) {

1597 if (MII->definesRegister(SystemZ::CC, nullptr)) {

1598 if (!MII->registerDefIsDead(SystemZ::CC, nullptr))

1599 return nullptr;

1600 break;

1601 }

1602 if (MII == MBB->begin()) {

1603 if (MBB->isLiveIn(SystemZ::CC))

1604 return nullptr;

1605 break;

1606 }

1607 }

1608 }

1609

1611 if (Ops.size() != 1 || FoldAsLoadDefReg != MI.getOperand(Ops[0]).getReg())

1612 return nullptr;

1613 Register DstReg = MI.getOperand(0).getReg();

1617 if ((RegMemOpcode == SystemZ::SDB || RegMemOpcode == SystemZ::SEB) &&

1618 FoldAsLoadDefReg != RHS.getReg())

1619 return nullptr;

1620

1625 BuildMI(*MI.getParent(), InsertPt, MI.getDebugLoc(), get(RegMemOpcode), DstReg)

1626 .add(RegMO)

1628 .add(Disp)

1629 .add(Indx);

1631 MRI->setRegClass(DstReg, FPRC);

1632 MRI->setRegClass(RegMO.getReg(), FPRC);

1634

1635 return MIB;

1636}

1637

1639 switch (MI.getOpcode()) {

1640 case SystemZ::L128:

1641 splitMove(MI, SystemZ::LG);

1642 return true;

1643

1644 case SystemZ::ST128:

1645 splitMove(MI, SystemZ::STG);

1646 return true;

1647

1648 case SystemZ::LX:

1649 splitMove(MI, SystemZ::LD);

1650 return true;

1651

1652 case SystemZ::STX:

1653 splitMove(MI, SystemZ::STD);

1654 return true;

1655

1656 case SystemZ::LBMux:

1657 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);

1658 return true;

1659

1660 case SystemZ::LHMux:

1661 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);

1662 return true;

1663

1664 case SystemZ::LLCRMux:

1665 expandZExtPseudo(MI, SystemZ::LLCR, 8);

1666 return true;

1667

1668 case SystemZ::LLHRMux:

1669 expandZExtPseudo(MI, SystemZ::LLHR, 16);

1670 return true;

1671

1672 case SystemZ::LLCMux:

1673 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);

1674 return true;

1675

1676 case SystemZ::LLHMux:

1677 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);

1678 return true;

1679

1680 case SystemZ::LMux:

1681 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);

1682 return true;

1683

1684 case SystemZ::LOCMux:

1685 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);

1686 return true;

1687

1688 case SystemZ::LOCHIMux:

1689 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);

1690 return true;

1691

1692 case SystemZ::STCMux:

1693 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);

1694 return true;

1695

1696 case SystemZ::STHMux:

1697 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);

1698 return true;

1699

1700 case SystemZ::STMux:

1701 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);

1702 return true;

1703

1704 case SystemZ::STOCMux:

1705 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);

1706 return true;

1707

1708 case SystemZ::LHIMux:

1709 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);

1710 return true;

1711

1712 case SystemZ::IIFMux:

1713 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);

1714 return true;

1715

1716 case SystemZ::IILMux:

1717 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);

1718 return true;

1719

1720 case SystemZ::IIHMux:

1721 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);

1722 return true;

1723

1724 case SystemZ::NIFMux:

1725 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);

1726 return true;

1727

1728 case SystemZ::NILMux:

1729 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);

1730 return true;

1731

1732 case SystemZ::NIHMux:

1733 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);

1734 return true;

1735

1736 case SystemZ::OIFMux:

1737 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);

1738 return true;

1739

1740 case SystemZ::OILMux:

1741 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);

1742 return true;

1743

1744 case SystemZ::OIHMux:

1745 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);

1746 return true;

1747

1748 case SystemZ::XIFMux:

1749 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);

1750 return true;

1751

1752 case SystemZ::TMLMux:

1753 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);

1754 return true;

1755

1756 case SystemZ::TMHMux:

1757 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);

1758 return true;

1759

1760 case SystemZ::AHIMux:

1761 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);

1762 return true;

1763

1764 case SystemZ::AHIMuxK:

1765 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);

1766 return true;

1767

1768 case SystemZ::AFIMux:

1769 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);

1770 return true;

1771

1772 case SystemZ::CHIMux:

1773 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);

1774 return true;

1775

1776 case SystemZ::CFIMux:

1777 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);

1778 return true;

1779

1780 case SystemZ::CLFIMux:

1781 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);

1782 return true;

1783

1784 case SystemZ::CMux:

1785 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);

1786 return true;

1787

1788 case SystemZ::CLMux:

1789 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);

1790 return true;

1791

1792 case SystemZ::RISBMux: {

1795 if (SrcIsHigh == DestIsHigh)

1796 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));

1797 else {

1798 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));

1799 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);

1800 }

1801 return true;

1802 }

1803

1804 case SystemZ::ADJDYNALLOC:

1805 splitAdjDynAlloc(MI);

1806 return true;

1807

1808 case TargetOpcode::LOAD_STACK_GUARD:

1809 expandLoadStackGuard(&MI);

1810 return true;

1811

1812 default:

1813 return false;

1814 }

1815}

1816

1818 if (MI.isInlineAsm()) {

1820 const char *AsmStr = MI.getOperand(0).getSymbolName();

1822 }

1823 else if (MI.getOpcode() == SystemZ::PATCHPOINT)

1825 else if (MI.getOpcode() == SystemZ::STACKMAP)

1826 return MI.getOperand(1).getImm();

1827 else if (MI.getOpcode() == SystemZ::FENTRY_CALL)

1828 return 6;

1829 if (MI.getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER)

1830 return 18;

1831 if (MI.getOpcode() == TargetOpcode::PATCHABLE_RET)

1832 return 18 + (MI.getOperand(0).getImm() == SystemZ::CondReturn ? 4 : 0);

1833

1834 return MI.getDesc().getSize();

1835}

1836

1839 switch (MI.getOpcode()) {

1840 case SystemZ::BR:

1841 case SystemZ::BI:

1842 case SystemZ::J:

1843 case SystemZ::JG:

1846

1847 case SystemZ::BRC:

1848 case SystemZ::BRCL:

1850 MI.getOperand(1).getImm(), &MI.getOperand(2));

1851

1852 case SystemZ::BRCT:

1853 case SystemZ::BRCTH:

1856

1857 case SystemZ::BRCTG:

1860

1861 case SystemZ::CIJ:

1862 case SystemZ::CRJ:

1864 MI.getOperand(2).getImm(), &MI.getOperand(3));

1865

1866 case SystemZ::CLIJ:

1867 case SystemZ::CLRJ:

1869 MI.getOperand(2).getImm(), &MI.getOperand(3));

1870

1871 case SystemZ::CGIJ:

1872 case SystemZ::CGRJ:

1874 MI.getOperand(2).getImm(), &MI.getOperand(3));

1875

1876 case SystemZ::CLGIJ:

1877 case SystemZ::CLGRJ:

1879 MI.getOperand(2).getImm(), &MI.getOperand(3));

1880

1881 case SystemZ::INLINEASM_BR:

1882

1884

1885 default:

1887 }

1888}

1889

1891 unsigned &LoadOpcode,

1892 unsigned &StoreOpcode) const {

1893 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {

1894 LoadOpcode = SystemZ::L;

1895 StoreOpcode = SystemZ::ST;

1896 } else if (RC == &SystemZ::GRH32BitRegClass) {

1897 LoadOpcode = SystemZ::LFH;

1898 StoreOpcode = SystemZ::STFH;

1899 } else if (RC == &SystemZ::GRX32BitRegClass) {

1900 LoadOpcode = SystemZ::LMux;

1901 StoreOpcode = SystemZ::STMux;

1902 } else if (RC == &SystemZ::GR64BitRegClass ||

1903 RC == &SystemZ::ADDR64BitRegClass) {

1904 LoadOpcode = SystemZ::LG;

1905 StoreOpcode = SystemZ::STG;

1906 } else if (RC == &SystemZ::GR128BitRegClass ||

1907 RC == &SystemZ::ADDR128BitRegClass) {

1908 LoadOpcode = SystemZ::L128;

1909 StoreOpcode = SystemZ::ST128;

1910 } else if (RC == &SystemZ::FP16BitRegClass && !STI.hasVector()) {

1911 LoadOpcode = SystemZ::LE16;

1912 StoreOpcode = SystemZ::STE16;

1913 } else if (RC == &SystemZ::FP32BitRegClass) {

1914 LoadOpcode = SystemZ::LE;

1915 StoreOpcode = SystemZ::STE;

1916 } else if (RC == &SystemZ::FP64BitRegClass) {

1917 LoadOpcode = SystemZ::LD;

1918 StoreOpcode = SystemZ::STD;

1919 } else if (RC == &SystemZ::FP128BitRegClass) {

1920 LoadOpcode = SystemZ::LX;

1921 StoreOpcode = SystemZ::STX;

1922 } else if (RC == &SystemZ::FP16BitRegClass ||

1923 RC == &SystemZ::VR16BitRegClass) {

1924 LoadOpcode = SystemZ::VL16;

1925 StoreOpcode = SystemZ::VST16;

1926 } else if (RC == &SystemZ::VR32BitRegClass) {

1927 LoadOpcode = SystemZ::VL32;

1928 StoreOpcode = SystemZ::VST32;

1929 } else if (RC == &SystemZ::VR64BitRegClass) {

1930 LoadOpcode = SystemZ::VL64;

1931 StoreOpcode = SystemZ::VST64;

1932 } else if (RC == &SystemZ::VF128BitRegClass ||

1933 RC == &SystemZ::VR128BitRegClass) {

1934 LoadOpcode = SystemZ::VL;

1935 StoreOpcode = SystemZ::VST;

1936 } else

1938}

1939

1946

1947 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);

1948 if (Disp12Opcode >= 0)

1949 return Disp12Opcode;

1950

1951

1952

1953 return Opcode;

1954 }

1956

1957 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);

1958 if (Disp20Opcode >= 0)

1959 return Disp20Opcode;

1960

1961

1963 return Opcode;

1964

1965

1966 if (MI && MI->getOperand(0).isReg()) {

1967 Register Reg = MI->getOperand(0).getReg();

1969 switch (Opcode) {

1970 case SystemZ::VL32:

1971 return SystemZ::LEY;

1972 case SystemZ::VST32:

1973 return SystemZ::STEY;

1974 case SystemZ::VL64:

1975 return SystemZ::LDY;

1976 case SystemZ::VST64:

1977 return SystemZ::STDY;

1978 default: break;

1979 }

1980 }

1981 }

1982 }

1983 return 0;

1984}

1985

1989 return SystemZ::getDisp12Opcode(Opcode) >= 0;

1990 return SystemZ::getDisp20Opcode(Opcode) >= 0;

1991}

1992

1994 switch (Opcode) {

1995 case SystemZ::L: return SystemZ::LT;

1996 case SystemZ::LY: return SystemZ::LT;

1997 case SystemZ::LG: return SystemZ::LTG;

1998 case SystemZ::LGF: return SystemZ::LTGF;

1999 case SystemZ::LR: return SystemZ::LTR;

2000 case SystemZ::LGFR: return SystemZ::LTGFR;

2001 case SystemZ::LGR: return SystemZ::LTGR;

2002 case SystemZ::LCDFR: return SystemZ::LCDBR;

2003 case SystemZ::LPDFR: return SystemZ::LPDBR;

2004 case SystemZ::LNDFR: return SystemZ::LNDBR;

2005 case SystemZ::LCDFR_32: return SystemZ::LCEBR;

2006 case SystemZ::LPDFR_32: return SystemZ::LPEBR;

2007 case SystemZ::LNDFR_32: return SystemZ::LNEBR;

2008

2009

2010

2011

2012 case SystemZ::RISBGN: return SystemZ::RISBG;

2013 default: return 0;

2014 }

2015}

2016

2018 unsigned &Start, unsigned &End) const {

2019

2020 Mask &= allOnes(BitSize);

2021 if (Mask == 0)

2022 return false;

2023

2024

2025

2026 unsigned LSB, Length;

2028 Start = 63 - (LSB + Length - 1);

2029 End = 63 - LSB;

2030 return true;

2031 }

2032

2033

2034

2036 assert(LSB > 0 && "Bottom bit must be set");

2037 assert(LSB + Length < BitSize && "Top bit must be set");

2038 Start = 63 - (LSB - 1);

2039 End = 63 - (LSB + Length);

2040 return true;

2041 }

2042

2043 return false;

2044}

2045

2049 switch (Opcode) {

2050 case SystemZ::CHI:

2051 case SystemZ::CGHI:

2052 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))

2053 return 0;

2054 break;

2055 case SystemZ::CLFI:

2056 case SystemZ::CLGFI:

2057 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))

2058 return 0;

2059 break;

2060 case SystemZ::CL:

2061 case SystemZ::CLG:

2062 if (!STI.hasMiscellaneousExtensions())

2063 return 0;

2064 if (!(MI && MI->getOperand(3).getReg() == 0))

2065 return 0;

2066 break;

2067 }

2068 switch (Type) {

2070 switch (Opcode) {

2071 case SystemZ::CR:

2072 return SystemZ::CRJ;

2073 case SystemZ::CGR:

2074 return SystemZ::CGRJ;

2075 case SystemZ::CHI:

2076 return SystemZ::CIJ;

2077 case SystemZ::CGHI:

2078 return SystemZ::CGIJ;

2079 case SystemZ::CLR:

2080 return SystemZ::CLRJ;

2081 case SystemZ::CLGR:

2082 return SystemZ::CLGRJ;

2083 case SystemZ::CLFI:

2084 return SystemZ::CLIJ;

2085 case SystemZ::CLGFI:

2086 return SystemZ::CLGIJ;

2087 default:

2088 return 0;

2089 }

2091 switch (Opcode) {

2092 case SystemZ::CR:

2093 return SystemZ::CRBReturn;

2094 case SystemZ::CGR:

2095 return SystemZ::CGRBReturn;

2096 case SystemZ::CHI:

2097 return SystemZ::CIBReturn;

2098 case SystemZ::CGHI:

2099 return SystemZ::CGIBReturn;

2100 case SystemZ::CLR:

2101 return SystemZ::CLRBReturn;

2102 case SystemZ::CLGR:

2103 return SystemZ::CLGRBReturn;

2104 case SystemZ::CLFI:

2105 return SystemZ::CLIBReturn;

2106 case SystemZ::CLGFI:

2107 return SystemZ::CLGIBReturn;

2108 default:

2109 return 0;

2110 }

2112 switch (Opcode) {

2113 case SystemZ::CR:

2114 return SystemZ::CRBCall;

2115 case SystemZ::CGR:

2116 return SystemZ::CGRBCall;

2117 case SystemZ::CHI:

2118 return SystemZ::CIBCall;

2119 case SystemZ::CGHI:

2120 return SystemZ::CGIBCall;

2121 case SystemZ::CLR:

2122 return SystemZ::CLRBCall;

2123 case SystemZ::CLGR:

2124 return SystemZ::CLGRBCall;

2125 case SystemZ::CLFI:

2126 return SystemZ::CLIBCall;

2127 case SystemZ::CLGFI:

2128 return SystemZ::CLGIBCall;

2129 default:

2130 return 0;

2131 }

2133 switch (Opcode) {

2134 case SystemZ::CR:

2135 return SystemZ::CRT;

2136 case SystemZ::CGR:

2137 return SystemZ::CGRT;

2138 case SystemZ::CHI:

2139 return SystemZ::CIT;

2140 case SystemZ::CGHI:

2141 return SystemZ::CGIT;

2142 case SystemZ::CLR:

2143 return SystemZ::CLRT;

2144 case SystemZ::CLGR:

2145 return SystemZ::CLGRT;

2146 case SystemZ::CLFI:

2147 return SystemZ::CLFIT;

2148 case SystemZ::CLGFI:

2149 return SystemZ::CLGIT;

2150 case SystemZ::CL:

2151 return SystemZ::CLT;

2152 case SystemZ::CLG:

2153 return SystemZ::CLGT;

2154 default:

2155 return 0;

2156 }

2157 }

2158 return 0;

2159}

2160

2163 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&

2164 MBBI->getOperand(1).isReg() && MBBI ->mayLoad() &&

2165 "Not a compare reg/reg.");

2166

2168 bool CCLive = true;

2171 if (MI.readsRegister(SystemZ::CC, nullptr)) {

2172 unsigned Flags = MI.getDesc().TSFlags;

2175 else

2176 return false;

2177 }

2178 if (MI.definesRegister(SystemZ::CC, nullptr)) {

2179 CCLive = false;

2180 break;

2181 }

2182 }

2183 if (CCLive) {

2186 if ( LiveRegs .available(SystemZ::CC))

2187 return false;

2188 }

2189

2190

2191 for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {

2192 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;

2194 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);

2195 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);

2197 CCMaskMO.setImm(NewCCMask);

2198 }

2199

2200 return true;

2201}

2202

2209

2214 return NewMBB;

2215}

2216

2223 return NewMBB;

2224}

2225

2231 return NewMBB;

2232}

2233

2235 if (!STI.hasLoadAndTrap())

2236 return 0;

2237 switch (Opcode) {

2238 case SystemZ::L:

2239 case SystemZ::LY:

2240 return SystemZ::LAT;

2241 case SystemZ::LG:

2242 return SystemZ::LGAT;

2243 case SystemZ::LFH:

2244 return SystemZ::LFHAT;

2245 case SystemZ::LLGF:

2246 return SystemZ::LLGFAT;

2247 case SystemZ::LLGT:

2248 return SystemZ::LLGTAT;

2249 }

2250 return 0;

2251}

2252

2257 unsigned Opcode = 0;

2259 Opcode = SystemZ::LGHI;

2261 Opcode = SystemZ::LLILL;

2263 Opcode = SystemZ::LLILH;

2265 }

2267 Opcode = SystemZ::LGFI;

2268 if (Opcode) {

2270 return;

2271 }

2272

2274 assert (MRI.isSSA() && "Huge values only handled before reg-alloc .");

2275 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);

2276 Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);

2282}

2283

2287 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {

2288 if (I >= MCID.getNumOperands())

2289 break;

2292

2293

2294

2296 ((MCOI.RegClass != -1 && .isReg() && .isFI()) ||

2297 (MCOI.RegClass == -1 && .isImm()))) {

2298 ErrInfo = "Addressing mode operands corrupt!";

2299 return false;

2300 }

2301 }

2302

2303 return true;

2304}

2305

2309

2311 return false;

2312

2313

2314

2315

2316

2321 bool SameVal = (VALa && VALb && (VALa == VALb));

2322 if (!SameVal) {

2325 if (PSVa && PSVb && (PSVa == PSVb))

2326 SameVal = true;

2327 }

2328 if (SameVal) {

2331 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;

2332 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;

2333 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;

2335 LowOffset + (int)LowWidth.getValue() <= HighOffset)

2336 return true;

2337 }

2338

2339 return false;

2340}

2341

2344 int64_t &ImmVal) const {

2345

2346 if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(0).getReg()) {

2347 ImmVal = MI.getOperand(1).getImm();

2348

2349 return ImmVal == 0;

2350 }

2351

2352 return false;

2353}

2354

2355std::optional

2357

2358 if (MI.isMoveReg())

2360

2361 return std::nullopt;

2362}

2363

2364std::pair<unsigned, unsigned>

2366 return std::make_pair(TF, 0u);

2367}

2368

2372

2373 static const std::pair<unsigned, const char *> TargetFlags[] = {

2374 {MO_ADA_DATA_SYMBOL_ADDR, "systemz-ada-datasymboladdr"},

2375 {MO_ADA_INDIRECT_FUNC_DESC, "systemz-ada-indirectfuncdesc"},

2376 {MO_ADA_DIRECT_FUNC_DESC, "systemz-ada-directfuncdesc"}};

2377 return ArrayRef(TargetFlags);

2378}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

DXIL Forward Handle Accesses

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)

Definition SystemZInstrInfo.cpp:1057

static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)

Definition SystemZInstrInfo.cpp:1095

static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)

Definition SystemZInstrInfo.cpp:1104

static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)

Definition SystemZInstrInfo.cpp:329

static LogicOp interpretAndImmediate(unsigned Opcode)

Definition SystemZInstrInfo.cpp:1080

static uint64_t allOnes(unsigned int Count)

Definition SystemZInstrInfo.cpp:55

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

SlotIndexes * getSlotIndexes() const

VNInfo::Allocator & getVNInfoAllocator()

LiveRange & getRegUnit(MCRegUnit Unit)

Return the live range for register unit Unit.

SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)

This class represents the liveness of a register, stack slot, etc.

bool liveAt(SlotIndex index) const

LLVM_ABI VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)

createDeadDef - Make sure the range has a value defined at Def.

A set of register units used to track register liveness.

LLVM_ABI void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)

replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.

TypeSize getValue() const

Describe properties that are true of each instruction in the target description file.

This holds information about one operand of a machine instruction, indicating the register class for ...

Wrapper class representing physical registers. Should be passed by value.

static MCRegister from(unsigned Val)

Check the provided unsigned value is a valid MCRegister.

LLVM_ABI void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)

Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

uint64_t getMaxCallFrameSize() const

Return the maximum size of a call frame that must be allocated for an outgoing function call.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

BasicBlockListType::iterator iterator

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineInstr - Allocate a new MachineInstr.

void insert(iterator MBBI, MachineBasicBlock *MBB)

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

bool getFlag(MIFlag Flag) const

Return whether an MI flag is set.

bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const

Returns true if the register is dead in this machine instruction.

bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const

Return true if the MachineInstr fully defines the specified register.

LLVM_ABI void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

bool hasOneMemOperand() const

Return true if this instruction has exactly one MachineMemOperand.

mmo_iterator memoperands_begin() const

Access to memory operands of the instruction.

void setFlag(MIFlag Flag)

Set a MI flag.

const MachineOperand & getOperand(unsigned i) const

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

LLVM_ABI bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

const PseudoSourceValue * getPseudoValue() const

bool isAtomic() const

Returns true if this operation has an atomic ordering requirement of unordered or higher,...

const Value * getValue() const

Return the base address of the memory access.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

MachineOperand class - Representation of each machine instruction operand.

void setImm(int64_t immVal)

void setIsDead(bool Val=true)

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsKill(bool Val=true)

static MachineOperand CreateImm(int64_t Val)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

MI-level patchpoint operands.

uint32_t getNumPatchBytes() const

Return the number of patchable bytes the given patchpoint should emit.

Special value supplied for machine level alias analysis.

Wrapper class representing virtual and physical registers.

MCRegister asMCReg() const

Utility to check-convert this value to a MCRegister.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

SlotIndex - An opaque wrapper around machine indexes.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const

Returns the base index for the given instruction.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

virtual int getStackPointerBias()=0

virtual int getCallFrameSize()=0

unsigned getLoadAndTrap(unsigned Opcode) const

Definition SystemZInstrInfo.cpp:2234

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition SystemZInstrInfo.cpp:1023

Definition SystemZInstrInfo.cpp:350

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition SystemZInstrInfo.cpp:542

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

Definition SystemZInstrInfo.cpp:792

unsigned getLoadAndTest(unsigned Opcode) const

Definition SystemZInstrInfo.cpp:1993

bool isPredicable(const MachineInstr &MI) const override

Definition SystemZInstrInfo.cpp:780

Definition SystemZInstrInfo.cpp:373

bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override

Definition SystemZInstrInfo.cpp:396

MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override

Definition SystemZInstrInfo.cpp:1111

unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const

Definition SystemZInstrInfo.cpp:1940

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

Definition SystemZInstrInfo.cpp:1817

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition SystemZInstrInfo.cpp:510

Definition SystemZInstrInfo.cpp:345

bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override

Definition SystemZInstrInfo.cpp:2342

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

Definition SystemZInstrInfo.cpp:1162

bool hasDisplacementPairInsn(unsigned Opcode) const

Definition SystemZInstrInfo.cpp:1986

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override

Commutes the operands in the given instruction by changing the operands order and/or changing the ins...

Definition SystemZInstrInfo.cpp:292

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

Definition SystemZInstrInfo.cpp:2370

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

Definition SystemZInstrInfo.cpp:632

std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override

Definition SystemZInstrInfo.cpp:1194

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

Definition SystemZInstrInfo.cpp:821

SystemZII::Branch getBranchInfo(const MachineInstr &MI) const

Definition SystemZInstrInfo.cpp:1838

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition SystemZInstrInfo.cpp:880

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

Definition SystemZInstrInfo.cpp:2307

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Definition SystemZInstrInfo.cpp:536

unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const

Definition SystemZInstrInfo.cpp:2046

bool expandPostRAPseudo(MachineInstr &MBBI) const override

Definition SystemZInstrInfo.cpp:1638

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override

Definition SystemZInstrInfo.cpp:581

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

Definition SystemZInstrInfo.cpp:2284

void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const

Definition SystemZInstrInfo.cpp:1890

bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const

Definition SystemZInstrInfo.cpp:2017

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

Definition SystemZInstrInfo.cpp:674

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

Definition SystemZInstrInfo.cpp:598

std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override

Definition SystemZInstrInfo.cpp:2356

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

Definition SystemZInstrInfo.cpp:2365

bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const

Definition SystemZInstrInfo.cpp:2162

Definition SystemZInstrInfo.cpp:340

MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override

Definition SystemZInstrInfo.cpp:1223

SystemZInstrInfo(const SystemZSubtarget &STI)

Definition SystemZInstrInfo.cpp:62

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition SystemZInstrInfo.cpp:1039

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Definition SystemZInstrInfo.cpp:419

void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const

Definition SystemZInstrInfo.cpp:2253

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

Definition SystemZInstrInfo.cpp:827

virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const

This method commutes the operands of the given machine instruction MI.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

Target - Wrapper for Target specific information.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Implicit

Not emitted register (e.g. carry, or temporary result).

@ Undef

Value of the register doesn't matter.

static unsigned getAccessSize(unsigned int Flags)

unsigned getFirstReg(unsigned Reg)

MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)

Definition SystemZInstrInfo.cpp:2226

int getTargetMemOpcode(uint16_t Opcode)

const unsigned CCMASK_CMP_GT

const unsigned CCMASK_ANY

static bool isImmLL(uint64_t Val)

static bool isImmLH(uint64_t Val)

MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)

Definition SystemZInstrInfo.cpp:2210

unsigned reverseCCMask(unsigned CCMask)

Definition SystemZInstrInfo.cpp:2203

const unsigned CCMASK_CMP_EQ

const unsigned CCMASK_ICMP

MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)

Definition SystemZInstrInfo.cpp:2217

const unsigned CCMASK_CMP_LT

const unsigned CCMASK_CMP_NE

bool isHighReg(unsigned int Reg)

const unsigned CCMASK_CMP_UO

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

constexpr bool isShiftedMask_64(uint64_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...

constexpr size_t range_size(R &&Range)

Returns the size of the Range, i.e., the number of elements.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

FunctionAddr VTableAddr Count

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

unsigned getUndefRegState(bool B)

unsigned getKillRegState(bool B)

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.