SystemZInstrInfo.cpp Source File (original) (raw)

42#include

43#include

44#include

46using namespace llvm;

48#define GET_INSTRINFO_CTOR_DTOR

49#define GET_INSTRMAP_INFO

50#include "SystemZGenInstrInfo.inc"

52#define DEBUG_TYPE "systemz-II"

56 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;

57}

60void SystemZInstrInfo::anchor() {}

64 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),

65 STI(sti) {}

70 unsigned NewOpcode) const {

78 MBB->insert(LowPartMI, HighPartMI);

86 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));

87 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));

98 assert(HighOpcode && LowOpcode && "Both offsets should be in range");

101

103 if (MI->mayStore()) {

105

106

107

108

112 } else {

113

114

115 auto overlapsAddressReg = [&](Register Reg) -> bool {

116 return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||

117 RI.regsOverlap(Reg, MI->getOperand(3).getReg());

118 };

119 if (overlapsAddressReg(HighRegOp.getReg())) {

120 assert(!overlapsAddressReg(LowRegOp.getReg()) &&

121 "Both loads clobber address!");

123 FirstMI = LowPartMI;

124 }

125 }

126

127

130}

131

132

139

145 assert(NewOpcode && "No support for huge argument lists yet");

146 MI->setDesc(get(NewOpcode));

148}

149

150

151

152

153

154

155

156void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,

157 unsigned HighOpcode,

158 bool ConvertHigh) const {

161 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));

162 if (IsHigh && ConvertHigh)

163 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));

164}

165

166

167

168

169

170void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,

171 unsigned LowOpcodeK,

172 unsigned HighOpcode) const {

173 Register DestReg = MI.getOperand(0).getReg();

174 Register SrcReg = MI.getOperand(1).getReg();

177 if (!DestIsHigh && !SrcIsHigh)

178 MI.setDesc(get(LowOpcodeK));

179 else {

180 if (DestReg != SrcReg) {

181 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,

182 SystemZ::LR, 32, MI.getOperand(1).isKill(),

183 MI.getOperand(1).isUndef());

184 MI.getOperand(1).setReg(DestReg);

185 }

186 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));

187 MI.tieOperands(0, 1);

188 }

189}

190

191

192

193

194void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,

195 unsigned HighOpcode) const {

199 MI.getOperand(2).getImm());

200 MI.setDesc(get(Opcode));

201}

202

203

204

205

206void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,

207 unsigned HighOpcode) const {

210 MI.setDesc(get(Opcode));

211}

212

213

214

215

216void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,

217 unsigned Size) const {

219 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),

220 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,

221 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());

222

223

225 MIB.add(MO);

226

227 MI.eraseFromParent();

228}

229

230void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {

233 const Register Reg64 = MI->getOperand(0).getReg();

234 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);

235

236

237

238

239

243

244

249

250

252 .addReg(SystemZ::A1);

253

254

255 MI->setDesc(get(SystemZ::LG));

257}

258

259

260

261

262

263

267 const DebugLoc &DL, unsigned DestReg,

268 unsigned SrcReg, unsigned LowLowOpcode,

269 unsigned Size, bool KillSrc,

270 bool UndefSrc) const {

271 unsigned Opcode;

274 if (DestIsHigh && SrcIsHigh)

275 Opcode = SystemZ::RISBHH;

276 else if (DestIsHigh && !SrcIsHigh)

277 Opcode = SystemZ::RISBHL;

278 else if (!DestIsHigh && SrcIsHigh)

279 Opcode = SystemZ::RISBLH;

280 else {

283 }

284 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);

289}

290

292 bool NewMI,

293 unsigned OpIdx1,

294 unsigned OpIdx2) const {

296 if (NewMI)

297 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);

298 return MI;

299 };

300

301 switch (MI.getOpcode()) {

302 case SystemZ::SELRMux:

303 case SystemZ::SELFHR:

304 case SystemZ::SELR:

305 case SystemZ::SELGR:

306 case SystemZ::LOCRMux:

307 case SystemZ::LOCFHR:

308 case SystemZ::LOCR:

309 case SystemZ::LOCGR: {

310 auto &WorkingMI = cloneIfNew(MI);

311

312 unsigned CCValid = WorkingMI.getOperand(3).getImm();

313 unsigned CCMask = WorkingMI.getOperand(4).getImm();

314 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);

316 OpIdx1, OpIdx2);

317 }

318 default:

320 }

321}

322

323

324

325

326

327

329 unsigned Flag) {

331 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&

332 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {

333 FrameIndex = MI.getOperand(1).getIndex();

334 return MI.getOperand(0).getReg();

335 }

336 return 0;

337}

338

340 int &FrameIndex) const {

342}

343

345 int &FrameIndex) const {

347}

348

350 int &DestFrameIndex,

351 int &SrcFrameIndex) const {

352

353 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();

354 if (MI.getOpcode() != SystemZ::MVC || .getOperand(0).isFI() ||

355 MI.getOperand(1).getImm() != 0 || .getOperand(3).isFI() ||

356 MI.getOperand(4).getImm() != 0)

357 return false;

358

359

360 int64_t Length = MI.getOperand(2).getImm();

361 unsigned FI1 = MI.getOperand(0).getIndex();

362 unsigned FI2 = MI.getOperand(3).getIndex();

365 return false;

366

367 DestFrameIndex = FI1;

368 SrcFrameIndex = FI2;

369 return true;

370}

371

376 bool AllowModify) const {

377

378

379

380

383 --I;

384 if (I->isDebugInstr())

385 continue;

386

387

388

389 if (!isUnpredicatedTerminator(*I))

390 break;

391

392

393

394 if (->isBranch())

395 return true;

396

397

399 if (!Branch.hasMBBTarget())

400 return true;

401

402

404 return true;

405

407

408 if (!AllowModify) {

409 TBB = Branch.getMBBTarget();

410 continue;

411 }

412

413

415

416 Cond.clear();

417 FBB = nullptr;

418

419

421 TBB = nullptr;

422 I->eraseFromParent();

424 continue;

425 }

426

427

428 TBB = Branch.getMBBTarget();

429 continue;

430 }

431

432

433 if (Cond.empty()) {

434

435 FBB = TBB;

436 TBB = Branch.getMBBTarget();

439 continue;

440 }

441

442

443 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");

444

445

446

447 if (TBB != Branch.getMBBTarget())

448 return true;

449

450

451 unsigned OldCCValid = Cond[0].getImm();

452 unsigned OldCCMask = Cond[1].getImm();

453 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)

454 continue;

455

456

457 return false;

458 }

459

460 return false;

461}

462

464 int *BytesRemoved) const {

465 assert(!BytesRemoved && "code size not handled");

466

467

469 unsigned Count = 0;

470

472 --I;

473 if (I->isDebugInstr())

474 continue;

475 if (->isBranch())

476 break;

478 break;

479

480 I->eraseFromParent();

482 ++Count;

483 }

484

485 return Count;

486}

487

490 assert(Cond.size() == 2 && "Invalid condition");

491 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());

492 return false;

493}

494

500 int *BytesAdded) const {

501

502

503

504

505

506 assert(TBB && "insertBranch must not be told to insert a fallthrough");

508 "SystemZ branch conditions have one component!");

509 assert(!BytesAdded && "code size not handled");

510

511 if (Cond.empty()) {

512

513 assert(!FBB && "Unconditional branch with multiple successors!");

515 return 1;

516 }

517

518

519 unsigned Count = 0;

520 unsigned CCValid = Cond[0].getImm();

521 unsigned CCMask = Cond[1].getImm();

524 ++Count;

525

526 if (FBB) {

527

529 ++Count;

530 }

531 return Count;

532}

533

535 Register &SrcReg2, int64_t &Mask,

536 int64_t &Value) const {

537 assert(MI.isCompare() && "Caller should have checked for a comparison");

538

539 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&

540 MI.getOperand(1).isImm()) {

541 SrcReg = MI.getOperand(0).getReg();

542 SrcReg2 = 0;

543 Value = MI.getOperand(1).getImm();

544 Mask = ~0;

545 return true;

546 }

547

548 return false;

549}

550

554 Register FalseReg, int &CondCycles,

555 int &TrueCycles,

556 int &FalseCycles) const {

557

558 if (!STI.hasLoadStoreOnCond())

559 return false;

560 if (Pred.size() != 2)

561 return false;

562

563

566 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));

567 if (!RC)

568 return false;

569

570

571 if ((STI.hasLoadStoreOnCond2() &&

572 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||

573 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||

574 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {

575 CondCycles = 2;

576 TrueCycles = 2;

577 FalseCycles = 2;

578 return true;

579 }

580

581

582 return false;

583}

584

593

594 assert(Pred.size() == 2 && "Invalid condition");

595 unsigned CCValid = Pred[0].getImm();

596 unsigned CCMask = Pred[1].getImm();

597

598 unsigned Opc;

599 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {

600 if (STI.hasMiscellaneousExtensions3())

601 Opc = SystemZ::SELRMux;

602 else if (STI.hasLoadStoreOnCond2())

603 Opc = SystemZ::LOCRMux;

604 else {

605 Opc = SystemZ::LOCR;

606 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);

607 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);

608 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);

611 TrueReg = TReg;

612 FalseReg = FReg;

613 }

614 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {

615 if (STI.hasMiscellaneousExtensions3())

616 Opc = SystemZ::SELGR;

617 else

618 Opc = SystemZ::LOCGR;

619 } else

621

625}

626

631

632 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);

634 bool SawStore = false;

635 if ( DefMI ->isSafeToMove(SawStore) || MRI ->hasOneNonDBGUse(FoldAsLoadDefReg))

636 return nullptr;

637

638 int UseOpIdx =

639 MI.findRegisterUseOperandIdx(FoldAsLoadDefReg, nullptr);

640 assert(UseOpIdx != -1 && "Expected FoldAsLoadDefReg to be used by MI.");

641

642

645 FoldAsLoadDefReg = 0;

646 return FoldMI;

647 }

648

649 return nullptr;

650}

651

655 unsigned DefOpc = DefMI.getOpcode();

656

657 if (DefOpc == SystemZ::VGBM) {

658 int64_t ImmVal = DefMI.getOperand(1).getImm();

659 if (ImmVal != 0)

660 return false;

661

662

663

664

665

667

668 if ( UseMI .isCopy())

669 return false;

670

673 MRI->getRegClass(CopyDstReg) == &SystemZ::GR128BitRegClass &&

674 MRI->hasOneNonDBGUse(Reg)) {

675

676

677

678 Register TmpReg = MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);

680

682

683 UseMI.setDesc(get(SystemZ::REG_SEQUENCE));

684 UseMI.getOperand(1).setReg(TmpReg);

686 .addImm(SystemZ::subreg_h64)

688 .addImm(SystemZ::subreg_l64);

689

690 if (MRI->use_nodbg_empty(Reg))

691 DefMI.eraseFromParent();

692 return true;

693 }

694

695 return false;

696 }

697

698 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&

699 DefOpc != SystemZ::LGHI)

700 return false;

702 return false;

703 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();

704

705 unsigned UseOpc = UseMI.getOpcode();

706 unsigned NewUseOpc;

707 unsigned UseIdx;

708 int CommuteIdx = -1;

709 bool TieOps = false;

710 switch (UseOpc) {

711 case SystemZ::SELRMux:

712 TieOps = true;

713 [[fallthrough]];

714 case SystemZ::LOCRMux:

715 if (!STI.hasLoadStoreOnCond2())

716 return false;

717 NewUseOpc = SystemZ::LOCHIMux;

719 UseIdx = 2;

720 else if (UseMI.getOperand(1).getReg() == Reg)

721 UseIdx = 2, CommuteIdx = 1;

722 else

723 return false;

724 break;

725 case SystemZ::SELGR:

726 TieOps = true;

727 [[fallthrough]];

728 case SystemZ::LOCGR:

729 if (!STI.hasLoadStoreOnCond2())

730 return false;

731 NewUseOpc = SystemZ::LOCGHI;

733 UseIdx = 2;

734 else if (UseMI.getOperand(1).getReg() == Reg)

735 UseIdx = 2, CommuteIdx = 1;

736 else

737 return false;

738 break;

739 default:

740 return false;

741 }

742

743 if (CommuteIdx != -1)

744 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))

745 return false;

746

747 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);

748 UseMI.setDesc(get(NewUseOpc));

749 if (TieOps)

750 UseMI.tieOperands(0, 1);

751 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);

752 if (DeleteDef)

753 DefMI.eraseFromParent();

754

755 return true;

756}

757

759 unsigned Opcode = MI.getOpcode();

760 if (Opcode == SystemZ::Return ||

761 Opcode == SystemZ::Return_XPLINK ||

762 Opcode == SystemZ::Trap ||

763 Opcode == SystemZ::CallJG ||

764 Opcode == SystemZ::CallBR)

765 return true;

766 return false;

767}

768

771 unsigned NumCycles, unsigned ExtraPredCycles,

773

774

775

776

777

778

779

780

783 return false;

784

785 return NumCycles == 1;

786}

787

790 unsigned NumCyclesT, unsigned ExtraPredCyclesT,

792 unsigned NumCyclesF, unsigned ExtraPredCyclesF,

794

795 return false;

796}

797

801

802 return NumCycles == 1;

803}

804

807 assert(Pred.size() == 2 && "Invalid condition");

808 unsigned CCValid = Pred[0].getImm();

809 unsigned CCMask = Pred[1].getImm();

810 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");

811 unsigned Opcode = MI.getOpcode();

812 if (Opcode == SystemZ::Trap) {

813 MI.setDesc(get(SystemZ::CondTrap));

817 return true;

818 }

819 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {

820 MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn

821 : SystemZ::CondReturn_XPLINK));

826 return true;

827 }

828 if (Opcode == SystemZ::CallJG) {

830 const uint32_t *RegMask = MI.getOperand(1).getRegMask();

831 MI.removeOperand(1);

832 MI.removeOperand(0);

833 MI.setDesc(get(SystemZ::CallBRCL));

837 .add(FirstOp)

840 return true;

841 }

842 if (Opcode == SystemZ::CallBR) {

844 const uint32_t *RegMask = MI.getOperand(1).getRegMask();

845 MI.removeOperand(1);

846 MI.removeOperand(0);

847 MI.setDesc(get(SystemZ::CallBCR));

853 return true;

854 }

855 return false;

856}

857

862 bool RenamableDest,

863 bool RenamableSrc) const {

864

865

866

867 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {

869 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);

873 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);

876 return;

877 }

878

879 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {

880 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,

881 false);

882 return;

883 }

884

885

886 if (SystemZ::VR128BitRegClass.contains(DestReg) &&

887 SystemZ::FP128BitRegClass.contains(SrcReg)) {

889 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),

890 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

892 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),

893 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

894

898 return;

899 }

900 if (SystemZ::FP128BitRegClass.contains(DestReg) &&

901 SystemZ::VR128BitRegClass.contains(SrcReg)) {

903 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),

904 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

906 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),

907 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

908

909 if (DestRegHi != SrcReg)

913 return;

914 }

915

916 if (SystemZ::FP128BitRegClass.contains(DestReg) &&

917 SystemZ::GR128BitRegClass.contains(SrcReg)) {

918 MCRegister DestRegHi = RI.getSubReg(DestReg, SystemZ::subreg_h64);

919 MCRegister DestRegLo = RI.getSubReg(DestReg, SystemZ::subreg_l64);

920 MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64);

921 MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64);

922

926

929 return;

930 }

931

932

933 if (DestReg == SystemZ::CC) {

934 unsigned Opcode =

935 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;

939 return;

940 }

941

942 if (SystemZ::GR128BitRegClass.contains(DestReg) &&

943 SystemZ::VR128BitRegClass.contains(SrcReg)) {

944 MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64);

945 MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64);

946

949 .addReg(SystemZ::NoRegister)

954 .addReg(SystemZ::NoRegister)

956 return;

957 }

958

959 if (SystemZ::VR128BitRegClass.contains(DestReg) &&

960 SystemZ::GR128BitRegClass.contains(SrcReg)) {

962 .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64))

963 .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64));

964 return;

965 }

966

967

968 unsigned Opcode;

969 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))

970 Opcode = SystemZ::LGR;

971 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))

972

973 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;

974 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))

975 Opcode = SystemZ::LDR;

976 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))

977 Opcode = SystemZ::LXR;

978 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))

979 Opcode = SystemZ::VLR32;

980 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))

981 Opcode = SystemZ::VLR64;

982 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))

983 Opcode = SystemZ::VLR;

984 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))

985 Opcode = SystemZ::CPYA;

986 else

988

991}

992

998

999

1000

1001 unsigned LoadOpcode, StoreOpcode;

1005 FrameIdx);

1006}

1007

1010 Register DestReg, int FrameIdx,

1015

1016

1017

1018 unsigned LoadOpcode, StoreOpcode;

1021 FrameIdx);

1022}

1023

1024

1025

1028 return ((MCID.TSFlags & Flag) &&

1029 isUInt<12>(MI->getOperand(2).getImm()) &&

1030 MI->getOperand(3).getReg() == 0);

1031}

1032

1033namespace {

1034

1035struct LogicOp {

1036 LogicOp() = default;

1037 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)

1038 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}

1039

1040 explicit operator bool() const { return RegSize; }

1041

1043 unsigned ImmLSB = 0;

1044 unsigned ImmSize = 0;

1045};

1046

1047}

1048

1050 switch (Opcode) {

1051 case SystemZ::NILMux: return LogicOp(32, 0, 16);

1052 case SystemZ::NIHMux: return LogicOp(32, 16, 16);

1053 case SystemZ::NILL64: return LogicOp(64, 0, 16);

1054 case SystemZ::NILH64: return LogicOp(64, 16, 16);

1055 case SystemZ::NIHL64: return LogicOp(64, 32, 16);

1056 case SystemZ::NIHH64: return LogicOp(64, 48, 16);

1057 case SystemZ::NIFMux: return LogicOp(32, 0, 32);

1058 case SystemZ::NILF64: return LogicOp(64, 0, 32);

1059 case SystemZ::NIHF64: return LogicOp(64, 32, 32);

1060 default: return LogicOp();

1061 }

1062}

1063

1068 if (CCDef != nullptr)

1070 }

1071}

1072

1075 if (OldMI->getFlag(Flag))

1077}

1078

1083

1084

1085

1087 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;

1088

1090 unsigned Start, End;

1092 unsigned NewOpcode;

1093 if (And.RegSize == 64) {

1094 NewOpcode = SystemZ::RISBG;

1095

1096 if (STI.hasMiscellaneousExtensions())

1097 NewOpcode = SystemZ::RISBGN;

1098 } else {

1099 NewOpcode = SystemZ::RISBMux;

1100 Start &= 31;

1101 End &= 31;

1102 }

1107 .add(Dest)

1110 Src.getSubReg())

1114 if (LV) {

1115 unsigned NumOps = MI.getNumOperands();

1116 for (unsigned I = 1; I < NumOps; ++I) {

1118 if (Op.isReg() && Op.isKill())

1120 }

1121 }

1122 if (LIS)

1125 return MIB;

1126 }

1127 }

1128 return nullptr;

1129}

1130

1132 bool Invert) const {

1133 unsigned Opc = Inst.getOpcode();

1134 if (Invert) {

1136 if (!InverseOpcode)

1137 return false;

1138 Opc = *InverseOpcode;

1139 }

1140

1141 switch (Opc) {

1142 default:

1143 break;

1144

1145 case SystemZ::WFADB:

1146 case SystemZ::WFASB:

1147 case SystemZ::WFAXB:

1148 case SystemZ::VFADB:

1149 case SystemZ::VFASB:

1150 case SystemZ::WFMDB:

1151 case SystemZ::WFMSB:

1152 case SystemZ::WFMXB:

1153 case SystemZ::VFMDB:

1154 case SystemZ::VFMSB:

1157 }

1158

1159 return false;

1160}

1161

1162std::optional

1164

1165 switch (Opcode) {

1166 case SystemZ::WFADB:

1167 return SystemZ::WFSDB;

1168 case SystemZ::WFASB:

1169 return SystemZ::WFSSB;

1170 case SystemZ::WFAXB:

1171 return SystemZ::WFSXB;

1172 case SystemZ::VFADB:

1173 return SystemZ::VFSDB;

1174 case SystemZ::VFASB:

1175 return SystemZ::VFSSB;

1176

1177 case SystemZ::WFSDB:

1178 return SystemZ::WFADB;

1179 case SystemZ::WFSSB:

1180 return SystemZ::WFASB;

1181 case SystemZ::WFSXB:

1182 return SystemZ::WFAXB;

1183 case SystemZ::VFSDB:

1184 return SystemZ::VFADB;

1185 case SystemZ::VFSSB:

1186 return SystemZ::VFASB;

1187 default:

1188 return std::nullopt;

1189 }

1190}

1191

1200 unsigned Opcode = MI.getOpcode();

1201

1202

1204 LiveRange *CCLiveRange = nullptr;

1205 bool CCLiveAtMI = true;

1206 if (LIS) {

1209 assert(range_size(CCUnits) == 1 && "CC only has one reg unit.");

1210 CCLiveRange = &LIS->getRegUnit(*CCUnits.begin());

1211 CCLiveAtMI = CCLiveRange->liveAt(MISlot);

1212 }

1213

1214 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {

1215 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&

1216 isInt<8>(MI.getOperand(2).getImm()) && .getOperand(3).getReg()) {

1217

1219 MI.getDebugLoc(), get(SystemZ::AGSI))

1222 .addImm(MI.getOperand(2).getImm());

1226 return BuiltMI;

1227 }

1228 return nullptr;

1229 }

1230

1231

1232 if (Ops.size() != 1)

1233 return nullptr;

1234

1235 unsigned OpNum = Ops[0];

1239 "Invalid size combination");

1240

1241 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&

1242 isInt<8>(MI.getOperand(2).getImm())) {

1243

1244 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);

1246 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))

1249 .addImm(MI.getOperand(2).getImm());

1252 return BuiltMI;

1253 }

1254

1255 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&

1256 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||

1257 (Opcode == SystemZ::ALGFI && OpNum == 0 &&

1258 isInt<8>((int64_t)MI.getOperand(2).getImm()))) {

1259

1260 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);

1262 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))

1265 .addImm((int8_t)MI.getOperand(2).getImm());

1267 return BuiltMI;

1268 }

1269

1270 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&

1271 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||

1272 (Opcode == SystemZ::SLGFI && OpNum == 0 &&

1273 isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {

1274

1275 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);

1277 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))

1280 .addImm((int8_t)-MI.getOperand(2).getImm());

1282 return BuiltMI;

1283 }

1284

1285 unsigned MemImmOpc = 0;

1286 switch (Opcode) {

1287 case SystemZ::LHIMux:

1288 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;

1289 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;

1290 case SystemZ::CHIMux:

1291 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;

1292 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;

1293 case SystemZ::CLFIMux:

1294 case SystemZ::CLFI:

1295 if (isUInt<16>(MI.getOperand(1).getImm()))

1296 MemImmOpc = SystemZ::CLFHSI;

1297 break;

1298 case SystemZ::CLGFI:

1299 if (isUInt<16>(MI.getOperand(1).getImm()))

1300 MemImmOpc = SystemZ::CLGHSI;

1301 break;

1302 default: break;

1303 }

1304 if (MemImmOpc)

1305 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1306 get(MemImmOpc))

1309 .addImm(MI.getOperand(1).getImm());

1310

1311 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {

1312 bool Op0IsGPR = (Opcode == SystemZ::LGDR);

1313 bool Op1IsGPR = (Opcode == SystemZ::LDGR);

1314

1315

1316 if (OpNum == 0) {

1317 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;

1318 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1319 get(StoreOpcode))

1320 .add(MI.getOperand(1))

1324 }

1325

1326

1327 if (OpNum == 1) {

1328 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;

1329 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1330 get(LoadOpcode))

1331 .add(MI.getOperand(0))

1335 }

1336 }

1337

1338

1339

1340

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350

1351 if (OpNum == 0 && MI.hasOneMemOperand()) {

1354

1356 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1357 get(SystemZ::MVC))

1361 .add(MI.getOperand(1))

1362 .addImm(MI.getOperand(2).getImm())

1364 }

1365

1367 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),

1368 get(SystemZ::MVC))

1369 .add(MI.getOperand(1))

1370 .addImm(MI.getOperand(2).getImm())

1375 }

1376 }

1377 }

1378

1379

1380

1381

1382 unsigned NumOps = MI.getNumExplicitOperands();

1383 int MemOpcode = SystemZ::getMemOpcode(Opcode);

1384 if (MemOpcode == -1 ||

1385 (CCLiveAtMI && .definesRegister(SystemZ::CC, nullptr) &&

1386 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))

1387 return nullptr;

1388

1389

1390

1395 continue;

1397 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {

1398 Register Reg = MI.getOperand(I).getReg();

1399 Register PhysReg = Reg.isVirtual()

1401 : Reg;

1402 if (!PhysReg ||

1403 !(SystemZ::FP32BitRegClass.contains(PhysReg) ||

1404 SystemZ::FP64BitRegClass.contains(PhysReg) ||

1405 SystemZ::VF128BitRegClass.contains(PhysReg)))

1406 return nullptr;

1407 }

1408 }

1409

1410 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||

1411 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);

1412 if (FusedFPOp) {

1415 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)

1416 return nullptr;

1417 }

1418

1419

1420 bool NeedsCommute = false;

1421 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||

1422 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||

1423 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||

1424 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&

1426 NeedsCommute = true;

1427

1428 bool CCOperands = false;

1429 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||

1430 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {

1431 assert(MI.getNumOperands() == 6 && NumOps == 5 &&

1432 "LOCR/SELR instruction operands corrupt?");

1433 NumOps -= 2;

1434 CCOperands = true;

1435 }

1436

1437

1438

1439

1441 if (VRM == nullptr)

1442 return nullptr;

1443 else {

1444 Register DstReg = MI.getOperand(0).getReg();

1447 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()

1448 : ((OpNum == 1 && MI.isCommutable())

1449 ? MI.getOperand(2).getReg()

1451 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&

1453 NeedsCommute = (OpNum == 1);

1454 else

1455 return nullptr;

1456 }

1457 }

1458

1459 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {

1462 assert(AccessBytes != 0 && "Size of access should be known");

1463 assert(AccessBytes <= Size && "Access outside the frame index");

1466 MI.getDebugLoc(), get(MemOpcode));

1467 if (MI.isCompare()) {

1468 assert(NumOps == 2 && "Expected 2 register operands for a compare.");

1469 MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));

1470 }

1471 else if (FusedFPOp) {

1472 MIB.add(MI.getOperand(0));

1473 MIB.add(MI.getOperand(3));

1474 MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));

1475 }

1476 else {

1477 MIB.add(MI.getOperand(0));

1478 if (NeedsCommute)

1479 MIB.add(MI.getOperand(2));

1480 else

1481 for (unsigned I = 1; I < OpNum; ++I)

1482 MIB.add(MI.getOperand(I));

1483 }

1487 if (CCOperands) {

1488 unsigned CCValid = MI.getOperand(NumOps).getImm();

1489 unsigned CCMask = MI.getOperand(NumOps + 1).getImm();

1490 MIB.addImm(CCValid);

1491 MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);

1492 }

1493 if (MIB->definesRegister(SystemZ::CC, nullptr) &&

1494 (.definesRegister(SystemZ::CC, nullptr) ||

1495 MI.registerDefIsDead(SystemZ::CC, nullptr))) {

1497 if (CCLiveRange)

1499 }

1500

1501

1503 if (MO.isReg() && MO.getReg().isVirtual()) {

1505 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)

1506 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);

1507 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)

1508 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);

1509 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)

1510 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);

1511 }

1512

1516 return MIB;

1517 }

1518

1519 return nullptr;

1520}

1521

1528

1529

1530

1531

1532

1533

1534

1535 unsigned LoadOpc = 0;

1536 unsigned RegMemOpcode = 0;

1538 RegMemOpcode = MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB

1539 : MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB

1540 : MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB

1541 : 0;

1542 if (RegMemOpcode) {

1543 LoadOpc = SystemZ::VL64;

1544 FPRC = &SystemZ::FP64BitRegClass;

1545 } else {

1546 RegMemOpcode = MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB

1547 : MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB

1548 : MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB

1549 : 0;

1550 if (RegMemOpcode) {

1551 LoadOpc = SystemZ::VL32;

1552 FPRC = &SystemZ::FP32BitRegClass;

1553 }

1554 }

1555 if (!RegMemOpcode || LoadMI.getOpcode() != LoadOpc)

1556 return nullptr;

1557

1558

1559 if (get(RegMemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)) {

1560 assert(LoadMI.getParent() == MI.getParent() && "Assuming a local fold.");

1561 assert(LoadMI != InsertPt && "Assuming InsertPt not to be first in MBB.");

1563 --MII) {

1564 if (MII->definesRegister(SystemZ::CC, nullptr)) {

1565 if (!MII->registerDefIsDead(SystemZ::CC, nullptr))

1566 return nullptr;

1567 break;

1568 }

1571 return nullptr;

1572 break;

1573 }

1574 }

1575 }

1576

1578 if (Ops.size() != 1 || FoldAsLoadDefReg != MI.getOperand(Ops[0]).getReg())

1579 return nullptr;

1580 Register DstReg = MI.getOperand(0).getReg();

1584 if ((RegMemOpcode == SystemZ::SDB || RegMemOpcode == SystemZ::SEB) &&

1585 FoldAsLoadDefReg != RHS.getReg())

1586 return nullptr;

1587

1592 BuildMI(*MI.getParent(), InsertPt, MI.getDebugLoc(), get(RegMemOpcode), DstReg)

1593 .add(RegMO)

1595 .add(Disp)

1596 .add(Indx);

1598 MRI->setRegClass(DstReg, FPRC);

1599 MRI->setRegClass(RegMO.getReg(), FPRC);

1601

1602 return MIB;

1603}

1604

1606 switch (MI.getOpcode()) {

1607 case SystemZ::L128:

1608 splitMove(MI, SystemZ::LG);

1609 return true;

1610

1611 case SystemZ::ST128:

1612 splitMove(MI, SystemZ::STG);

1613 return true;

1614

1615 case SystemZ::LX:

1616 splitMove(MI, SystemZ::LD);

1617 return true;

1618

1619 case SystemZ::STX:

1620 splitMove(MI, SystemZ::STD);

1621 return true;

1622

1623 case SystemZ::LBMux:

1624 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);

1625 return true;

1626

1627 case SystemZ::LHMux:

1628 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);

1629 return true;

1630

1631 case SystemZ::LLCRMux:

1632 expandZExtPseudo(MI, SystemZ::LLCR, 8);

1633 return true;

1634

1635 case SystemZ::LLHRMux:

1636 expandZExtPseudo(MI, SystemZ::LLHR, 16);

1637 return true;

1638

1639 case SystemZ::LLCMux:

1640 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);

1641 return true;

1642

1643 case SystemZ::LLHMux:

1644 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);

1645 return true;

1646

1647 case SystemZ::LMux:

1648 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);

1649 return true;

1650

1651 case SystemZ::LOCMux:

1652 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);

1653 return true;

1654

1655 case SystemZ::LOCHIMux:

1656 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);

1657 return true;

1658

1659 case SystemZ::STCMux:

1660 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);

1661 return true;

1662

1663 case SystemZ::STHMux:

1664 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);

1665 return true;

1666

1667 case SystemZ::STMux:

1668 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);

1669 return true;

1670

1671 case SystemZ::STOCMux:

1672 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);

1673 return true;

1674

1675 case SystemZ::LHIMux:

1676 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);

1677 return true;

1678

1679 case SystemZ::IIFMux:

1680 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);

1681 return true;

1682

1683 case SystemZ::IILMux:

1684 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);

1685 return true;

1686

1687 case SystemZ::IIHMux:

1688 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);

1689 return true;

1690

1691 case SystemZ::NIFMux:

1692 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);

1693 return true;

1694

1695 case SystemZ::NILMux:

1696 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);

1697 return true;

1698

1699 case SystemZ::NIHMux:

1700 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);

1701 return true;

1702

1703 case SystemZ::OIFMux:

1704 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);

1705 return true;

1706

1707 case SystemZ::OILMux:

1708 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);

1709 return true;

1710

1711 case SystemZ::OIHMux:

1712 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);

1713 return true;

1714

1715 case SystemZ::XIFMux:

1716 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);

1717 return true;

1718

1719 case SystemZ::TMLMux:

1720 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);

1721 return true;

1722

1723 case SystemZ::TMHMux:

1724 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);

1725 return true;

1726

1727 case SystemZ::AHIMux:

1728 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);

1729 return true;

1730

1731 case SystemZ::AHIMuxK:

1732 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);

1733 return true;

1734

1735 case SystemZ::AFIMux:

1736 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);

1737 return true;

1738

1739 case SystemZ::CHIMux:

1740 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);

1741 return true;

1742

1743 case SystemZ::CFIMux:

1744 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);

1745 return true;

1746

1747 case SystemZ::CLFIMux:

1748 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);

1749 return true;

1750

1751 case SystemZ::CMux:

1752 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);

1753 return true;

1754

1755 case SystemZ::CLMux:

1756 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);

1757 return true;

1758

1759 case SystemZ::RISBMux: {

1762 if (SrcIsHigh == DestIsHigh)

1763 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));

1764 else {

1765 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));

1766 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);

1767 }

1768 return true;

1769 }

1770

1771 case SystemZ::ADJDYNALLOC:

1772 splitAdjDynAlloc(MI);

1773 return true;

1774

1775 case TargetOpcode::LOAD_STACK_GUARD:

1776 expandLoadStackGuard(&MI);

1777 return true;

1778

1779 default:

1780 return false;

1781 }

1782}

1783

1785 if (MI.isInlineAsm()) {

1787 const char *AsmStr = MI.getOperand(0).getSymbolName();

1789 }

1790 else if (MI.getOpcode() == SystemZ::PATCHPOINT)

1792 else if (MI.getOpcode() == SystemZ::STACKMAP)

1793 return MI.getOperand(1).getImm();

1794 else if (MI.getOpcode() == SystemZ::FENTRY_CALL)

1795 return 6;

1796 if (MI.getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER)

1797 return 18;

1798 if (MI.getOpcode() == TargetOpcode::PATCHABLE_RET)

1799 return 18 + (MI.getOperand(0).getImm() == SystemZ::CondReturn ? 4 : 0);

1800

1801 return MI.getDesc().getSize();

1802}

1803

1806 switch (MI.getOpcode()) {

1807 case SystemZ::BR:

1808 case SystemZ::BI:

1809 case SystemZ::J:

1810 case SystemZ::JG:

1813

1814 case SystemZ::BRC:

1815 case SystemZ::BRCL:

1817 MI.getOperand(1).getImm(), &MI.getOperand(2));

1818

1819 case SystemZ::BRCT:

1820 case SystemZ::BRCTH:

1823

1824 case SystemZ::BRCTG:

1827

1828 case SystemZ::CIJ:

1829 case SystemZ::CRJ:

1831 MI.getOperand(2).getImm(), &MI.getOperand(3));

1832

1833 case SystemZ::CLIJ:

1834 case SystemZ::CLRJ:

1836 MI.getOperand(2).getImm(), &MI.getOperand(3));

1837

1838 case SystemZ::CGIJ:

1839 case SystemZ::CGRJ:

1841 MI.getOperand(2).getImm(), &MI.getOperand(3));

1842

1843 case SystemZ::CLGIJ:

1844 case SystemZ::CLGRJ:

1846 MI.getOperand(2).getImm(), &MI.getOperand(3));

1847

1848 case SystemZ::INLINEASM_BR:

1849

1851

1852 default:

1854 }

1855}

1856

1858 unsigned &LoadOpcode,

1859 unsigned &StoreOpcode) const {

1860 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {

1861 LoadOpcode = SystemZ::L;

1862 StoreOpcode = SystemZ::ST;

1863 } else if (RC == &SystemZ::GRH32BitRegClass) {

1864 LoadOpcode = SystemZ::LFH;

1865 StoreOpcode = SystemZ::STFH;

1866 } else if (RC == &SystemZ::GRX32BitRegClass) {

1867 LoadOpcode = SystemZ::LMux;

1868 StoreOpcode = SystemZ::STMux;

1869 } else if (RC == &SystemZ::GR64BitRegClass ||

1870 RC == &SystemZ::ADDR64BitRegClass) {

1871 LoadOpcode = SystemZ::LG;

1872 StoreOpcode = SystemZ::STG;

1873 } else if (RC == &SystemZ::GR128BitRegClass ||

1874 RC == &SystemZ::ADDR128BitRegClass) {

1875 LoadOpcode = SystemZ::L128;

1876 StoreOpcode = SystemZ::ST128;

1877 } else if (RC == &SystemZ::FP32BitRegClass) {

1878 LoadOpcode = SystemZ::LE;

1879 StoreOpcode = SystemZ::STE;

1880 } else if (RC == &SystemZ::FP64BitRegClass) {

1881 LoadOpcode = SystemZ::LD;

1882 StoreOpcode = SystemZ::STD;

1883 } else if (RC == &SystemZ::FP128BitRegClass) {

1884 LoadOpcode = SystemZ::LX;

1885 StoreOpcode = SystemZ::STX;

1886 } else if (RC == &SystemZ::VR32BitRegClass) {

1887 LoadOpcode = SystemZ::VL32;

1888 StoreOpcode = SystemZ::VST32;

1889 } else if (RC == &SystemZ::VR64BitRegClass) {

1890 LoadOpcode = SystemZ::VL64;

1891 StoreOpcode = SystemZ::VST64;

1892 } else if (RC == &SystemZ::VF128BitRegClass ||

1893 RC == &SystemZ::VR128BitRegClass) {

1894 LoadOpcode = SystemZ::VL;

1895 StoreOpcode = SystemZ::VST;

1896 } else

1898}

1899

1905 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {

1906

1907 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);

1908 if (Disp12Opcode >= 0)

1909 return Disp12Opcode;

1910

1911

1912

1913 return Opcode;

1914 }

1915 if (isInt<20>(Offset) && isInt<20>(Offset2)) {

1916

1917 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);

1918 if (Disp20Opcode >= 0)

1919 return Disp20Opcode;

1920

1921

1923 return Opcode;

1924

1925

1926 if (MI && MI->getOperand(0).isReg()) {

1927 Register Reg = MI->getOperand(0).getReg();

1929 switch (Opcode) {

1930 case SystemZ::VL32:

1931 return SystemZ::LEY;

1932 case SystemZ::VST32:

1933 return SystemZ::STEY;

1934 case SystemZ::VL64:

1935 return SystemZ::LDY;

1936 case SystemZ::VST64:

1937 return SystemZ::STDY;

1938 default: break;

1939 }

1940 }

1941 }

1942 }

1943 return 0;

1944}

1945

1949 return SystemZ::getDisp12Opcode(Opcode) >= 0;

1950 return SystemZ::getDisp20Opcode(Opcode) >= 0;

1951}

1952

1954 switch (Opcode) {

1955 case SystemZ::L: return SystemZ::LT;

1956 case SystemZ::LY: return SystemZ::LT;

1957 case SystemZ::LG: return SystemZ::LTG;

1958 case SystemZ::LGF: return SystemZ::LTGF;

1959 case SystemZ::LR: return SystemZ::LTR;

1960 case SystemZ::LGFR: return SystemZ::LTGFR;

1961 case SystemZ::LGR: return SystemZ::LTGR;

1962 case SystemZ::LCDFR: return SystemZ::LCDBR;

1963 case SystemZ::LPDFR: return SystemZ::LPDBR;

1964 case SystemZ::LNDFR: return SystemZ::LNDBR;

1965 case SystemZ::LCDFR_32: return SystemZ::LCEBR;

1966 case SystemZ::LPDFR_32: return SystemZ::LPEBR;

1967 case SystemZ::LNDFR_32: return SystemZ::LNEBR;

1968

1969

1970

1971

1972 case SystemZ::RISBGN: return SystemZ::RISBG;

1973 default: return 0;

1974 }

1975}

1976

1978 unsigned &Start, unsigned &End) const {

1979

1980 Mask &= allOnes(BitSize);

1981 if (Mask == 0)

1982 return false;

1983

1984

1985

1986 unsigned LSB, Length;

1988 Start = 63 - (LSB + Length - 1);

1989 End = 63 - LSB;

1990 return true;

1991 }

1992

1993

1994

1996 assert(LSB > 0 && "Bottom bit must be set");

1997 assert(LSB + Length < BitSize && "Top bit must be set");

1998 Start = 63 - (LSB - 1);

2000 return true;

2001 }

2002

2003 return false;

2004}

2005

2009 switch (Opcode) {

2010 case SystemZ::CHI:

2011 case SystemZ::CGHI:

2012 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))

2013 return 0;

2014 break;

2015 case SystemZ::CLFI:

2016 case SystemZ::CLGFI:

2017 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))

2018 return 0;

2019 break;

2020 case SystemZ::CL:

2021 case SystemZ::CLG:

2022 if (!STI.hasMiscellaneousExtensions())

2023 return 0;

2024 if (!(MI && MI->getOperand(3).getReg() == 0))

2025 return 0;

2026 break;

2027 }

2028 switch (Type) {

2030 switch (Opcode) {

2031 case SystemZ::CR:

2032 return SystemZ::CRJ;

2033 case SystemZ::CGR:

2034 return SystemZ::CGRJ;

2035 case SystemZ::CHI:

2036 return SystemZ::CIJ;

2037 case SystemZ::CGHI:

2038 return SystemZ::CGIJ;

2039 case SystemZ::CLR:

2040 return SystemZ::CLRJ;

2041 case SystemZ::CLGR:

2042 return SystemZ::CLGRJ;

2043 case SystemZ::CLFI:

2044 return SystemZ::CLIJ;

2045 case SystemZ::CLGFI:

2046 return SystemZ::CLGIJ;

2047 default:

2048 return 0;

2049 }

2051 switch (Opcode) {

2052 case SystemZ::CR:

2053 return SystemZ::CRBReturn;

2054 case SystemZ::CGR:

2055 return SystemZ::CGRBReturn;

2056 case SystemZ::CHI:

2057 return SystemZ::CIBReturn;

2058 case SystemZ::CGHI:

2059 return SystemZ::CGIBReturn;

2060 case SystemZ::CLR:

2061 return SystemZ::CLRBReturn;

2062 case SystemZ::CLGR:

2063 return SystemZ::CLGRBReturn;

2064 case SystemZ::CLFI:

2065 return SystemZ::CLIBReturn;

2066 case SystemZ::CLGFI:

2067 return SystemZ::CLGIBReturn;

2068 default:

2069 return 0;

2070 }

2072 switch (Opcode) {

2073 case SystemZ::CR:

2074 return SystemZ::CRBCall;

2075 case SystemZ::CGR:

2076 return SystemZ::CGRBCall;

2077 case SystemZ::CHI:

2078 return SystemZ::CIBCall;

2079 case SystemZ::CGHI:

2080 return SystemZ::CGIBCall;

2081 case SystemZ::CLR:

2082 return SystemZ::CLRBCall;

2083 case SystemZ::CLGR:

2084 return SystemZ::CLGRBCall;

2085 case SystemZ::CLFI:

2086 return SystemZ::CLIBCall;

2087 case SystemZ::CLGFI:

2088 return SystemZ::CLGIBCall;

2089 default:

2090 return 0;

2091 }

2093 switch (Opcode) {

2094 case SystemZ::CR:

2095 return SystemZ::CRT;

2096 case SystemZ::CGR:

2097 return SystemZ::CGRT;

2098 case SystemZ::CHI:

2099 return SystemZ::CIT;

2100 case SystemZ::CGHI:

2101 return SystemZ::CGIT;

2102 case SystemZ::CLR:

2103 return SystemZ::CLRT;

2104 case SystemZ::CLGR:

2105 return SystemZ::CLGRT;

2106 case SystemZ::CLFI:

2107 return SystemZ::CLFIT;

2108 case SystemZ::CLGFI:

2109 return SystemZ::CLGIT;

2110 case SystemZ::CL:

2111 return SystemZ::CLT;

2112 case SystemZ::CLG:

2113 return SystemZ::CLGT;

2114 default:

2115 return 0;

2116 }

2117 }

2118 return 0;

2119}

2120

2123 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&

2124 MBBI->getOperand(1).isReg() && MBBI ->mayLoad() &&

2125 "Not a compare reg/reg.");

2126

2128 bool CCLive = true;

2131 if (MI.readsRegister(SystemZ::CC, nullptr)) {

2132 unsigned Flags = MI.getDesc().TSFlags;

2135 else

2136 return false;

2137 }

2138 if (MI.definesRegister(SystemZ::CC, nullptr)) {

2139 CCLive = false;

2140 break;

2141 }

2142 }

2143 if (CCLive) {

2146 if (!LiveRegs.available(SystemZ::CC))

2147 return false;

2148 }

2149

2150

2151 for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {

2152 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;

2154 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);

2155 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);

2157 CCMaskMO.setImm(NewCCMask);

2158 }

2159

2160 return true;

2161}

2162

2168}

2169

2174 return NewMBB;

2175}

2176

2183 return NewMBB;

2184}

2185

2191 return NewMBB;

2192}

2193

2195 if (!STI.hasLoadAndTrap())

2196 return 0;

2197 switch (Opcode) {

2198 case SystemZ::L:

2199 case SystemZ::LY:

2200 return SystemZ::LAT;

2201 case SystemZ::LG:

2202 return SystemZ::LGAT;

2203 case SystemZ::LFH:

2204 return SystemZ::LFHAT;

2205 case SystemZ::LLGF:

2206 return SystemZ::LLGFAT;

2207 case SystemZ::LLGT:

2208 return SystemZ::LLGTAT;

2209 }

2210 return 0;

2211}

2212

2217 unsigned Opcode = 0;

2218 if (isInt<16>(Value))

2219 Opcode = SystemZ::LGHI;

2221 Opcode = SystemZ::LLILL;

2223 Opcode = SystemZ::LLILH;

2225 }

2226 else if (isInt<32>(Value))

2227 Opcode = SystemZ::LGFI;

2228 if (Opcode) {

2230 return;

2231 }

2232

2234 assert (MRI.isSSA() && "Huge values only handled before reg-alloc .");

2235 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);

2236 Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);

2242}

2243

2247 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {

2249 break;

2252

2253

2254

2256 ((MCOI.RegClass != -1 && .isReg() && .isFI()) ||

2257 (MCOI.RegClass == -1 && .isImm()))) {

2258 ErrInfo = "Addressing mode operands corrupt!";

2259 return false;

2260 }

2261 }

2262

2263 return true;

2264}

2265

2269

2271 return false;

2272

2273

2274

2275

2276

2281 bool SameVal = (VALa && VALb && (VALa == VALb));

2282 if (!SameVal) {

2285 if (PSVa && PSVb && (PSVa == PSVb))

2286 SameVal = true;

2287 }

2288 if (SameVal) {

2291 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;

2292 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;

2293 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;

2295 LowOffset + (int)LowWidth.getValue() <= HighOffset)

2296 return true;

2297 }

2298

2299 return false;

2300}

2301

2304 int64_t &ImmVal) const {

2305

2306 if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(0).getReg()) {

2307 ImmVal = MI.getOperand(1).getImm();

2308

2309 return ImmVal == 0;

2310 }

2311

2312 return false;

2313}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

unsigned const TargetRegisterInfo * TRI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)

static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)

static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)

static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)

static LogicOp interpretAndImmediate(unsigned Opcode)

static uint64_t allOnes(unsigned int Count)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

This class represents an Operation in the Expression.

SlotIndexes * getSlotIndexes() const

VNInfo::Allocator & getVNInfoAllocator()

LiveRange & getRegUnit(unsigned Unit)

Return the live range for register unit Unit.

SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)

This class represents the liveness of a register, stack slot, etc.

bool liveAt(SlotIndex index) const

VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)

createDeadDef - Make sure the range has a value defined at Def.

A set of register units used to track register liveness.

bool available(MCPhysReg Reg) const

Returns true if no part of physical register Reg is live.

void addLiveOuts(const MachineBasicBlock &MBB)

Adds registers living out of block MBB.

void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)

replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.

TypeSize getValue() const

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

ArrayRef< MCOperandInfo > operands() const

This holds information about one operand of a machine instruction, indicating the register class for ...

uint8_t OperandType

Information about the type of the operand.

int16_t RegClass

This specifies the register class enumeration of the operand if the operand is a register.

Wrapper class representing physical registers. Should be passed by value.

static MCRegister from(unsigned Val)

Check the provided unsigned value is a valid MCRegister.

void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)

Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

iterator getLastNonDebugInstr(bool SkipPseudoOp=true)

Returns an iterator to the last non-debug instruction in the basic block, or end().

bool isLayoutSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const

Return true if the specified register is in the live in set.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

uint64_t getMaxCallFrameSize() const

Return the maximum size of a call frame that must be allocated for an outgoing function call.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

MachineInstr * CloneMachineInstr(const MachineInstr *Orig)

Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineBasicBlock - Allocate a new MachineBasicBlock.

void insert(iterator MBBI, MachineBasicBlock *MBB)

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Get the register for the operand index.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

bool getFlag(MIFlag Flag) const

Return whether an MI flag is set.

bool isSafeToMove(bool &SawStore) const

Return true if it is safe to move this instruction.

bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const

Returns true if the register is dead in this machine instruction.

bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const

Return true if the MachineInstr fully defines the specified register.

void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

bool hasOneMemOperand() const

Return true if this instruction has exactly one MachineMemOperand.

iterator_range< mop_iterator > operands()

mmo_iterator memoperands_begin() const

Access to memory operands of the instruction.

void setFlag(MIFlag Flag)

Set a MI flag.

const MachineOperand & getOperand(unsigned i) const

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

const PseudoSourceValue * getPseudoValue() const

bool isAtomic() const

Returns true if this operation has an atomic ordering requirement of unordered or higher,...

const Value * getValue() const

Return the base address of the memory access.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

MachineOperand class - Representation of each machine instruction operand.

void setImm(int64_t immVal)

void setIsDead(bool Val=true)

void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsKill(bool Val=true)

static MachineOperand CreateImm(int64_t Val)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

MI-level patchpoint operands.

uint32_t getNumPatchBytes() const

Return the number of patchable bytes the given patchpoint should emit.

Special value supplied for machine level alias analysis.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

SlotIndex - An opaque wrapper around machine indexes.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const

Returns the base index for the given instruction.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

A SystemZ-specific class detailing special use registers particular for calling conventions.

virtual int getStackPointerBias()=0

virtual int getCallFrameSize()=0

unsigned getLoadAndTrap(unsigned Opcode) const

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

unsigned getLoadAndTest(unsigned Opcode) const

bool isPredicable(const MachineInstr &MI) const override

bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override

MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override

SystemZInstrInfo(SystemZSubtarget &STI)

bool hasDisplacementPairInsn(unsigned Opcode) const

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override

Commutes the operands in the given instruction by changing the operands order and/or changing the ins...

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

SystemZII::Branch getBranchInfo(const MachineInstr &MI) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const

bool expandPostRAPseudo(MachineInstr &MBBI) const override

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const

bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const

MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

SystemZCallingConventionRegisters * getSpecialRegisters() const

virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const

This method commutes the operands of the given machine instruction MI.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

Target - Wrapper for Target specific information.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Implicit

Not emitted register (e.g. carry, or temporary result).

@ Undef

Value of the register doesn't matter.

static unsigned getAccessSize(unsigned int Flags)

unsigned getFirstReg(unsigned Reg)

MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)

int getTargetMemOpcode(uint16_t Opcode)

const unsigned CCMASK_CMP_GT

const unsigned CCMASK_ANY

static bool isImmLL(uint64_t Val)

static bool isImmLH(uint64_t Val)

MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)

unsigned reverseCCMask(unsigned CCMask)

const unsigned CCMASK_CMP_EQ

const unsigned CCMASK_ICMP

MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)

const unsigned CCMASK_CMP_LT

const unsigned CCMASK_CMP_NE

bool isHighReg(unsigned int Reg)

const unsigned CCMASK_CMP_UO

Reg

All possible values of the reg field in the ModR/M byte.

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

constexpr bool isShiftedMask_64(uint64_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...

constexpr size_t range_size(R &&Range)

Returns the size of the Range, i.e., the number of elements.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getUndefRegState(bool B)

@ And

Bitwise or logical AND of integers.

unsigned getKillRegState(bool B)