SystemZInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H

14#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H

23#include

25#define GET_INSTRINFO_HEADER

26#include "SystemZGenInstrInfo.inc"

28namespace llvm {

30class SystemZSubtarget;

34enum {

51};

66enum {

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121public:

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135 bool isIndirect() { return Target != nullptr && Target->isReg(); }

136 bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }

138 return hasMBBTarget() ? Target->getMBB() : nullptr;

139 }

140};

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157};

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159}

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161namespace SystemZ {

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178}

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183

186 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,

187 bool ConvertHigh) const;

188 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,

189 unsigned LowOpcodeK, unsigned HighOpcode) const;

190 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,

191 unsigned HighOpcode) const;

192 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,

193 unsigned HighOpcode) const;

194 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,

195 unsigned Size) const;

197

200 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,

201 unsigned LowLowOpcode, unsigned Size, bool KillSrc,

202 bool UndefSrc) const;

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204 virtual void anchor();

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206protected:

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219 unsigned CommuteOpIdx1,

220 unsigned CommuteOpIdx2) const override;

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222public:

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227 int &FrameIndex) const override;

229 int &FrameIndex) const override;

231 int &FrameIndex) const override;

233 int &FrameIndex) const override;

235 int &SrcFrameIndex) const override;

239 bool AllowModify) const override;

241 int *BytesRemoved = nullptr) const override;

245 int *BytesAdded = nullptr) const override;

247 Register &SrcReg2, int64_t &Mask,

248 int64_t &Value) const override;

251 int &) const override;

255 Register FalseReg) const override;

258

261 unsigned ExtraPredCycles,

264 unsigned NumCyclesT, unsigned ExtraPredCyclesT,

266 unsigned NumCyclesF, unsigned ExtraPredCyclesF,

274 bool KillSrc, bool RenamableDest = false,

275 bool RenamableSrc = false) const override;

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293 bool Invert) const override;

294 std::optional getInverseOpcode(unsigned Opcode) const override;

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301 VirtRegMap *VRM = nullptr) const override;

308 override;

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325 unsigned &LoadOpcode, unsigned &StoreOpcode) const;

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347 unsigned &Start, unsigned &End) const;

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374 StringRef &ErrInfo) const override;

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380 bool

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385 int64_t &ImmVal) const override;

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387 std::optional

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390 std::pair<unsigned, unsigned>

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395};

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397}

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399#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

Definition SystemZInstrInfo.h:117

unsigned CCValid

Definition SystemZInstrInfo.h:126

BranchType Type

Definition SystemZInstrInfo.h:123

unsigned CCMask

Definition SystemZInstrInfo.h:129

MachineBasicBlock * getMBBTarget()

Definition SystemZInstrInfo.h:137

bool isIndirect()

Definition SystemZInstrInfo.h:135

Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)

Definition SystemZInstrInfo.h:131

bool hasMBBTarget()

Definition SystemZInstrInfo.h:136

unsigned getLoadAndTrap(unsigned Opcode) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

unsigned getLoadAndTest(unsigned Opcode) const

bool isPredicable(const MachineInstr &MI) const override

bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override

MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override

unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

const SystemZRegisterInfo & getRegisterInfo() const

Definition SystemZInstrInfo.h:311

bool useMachineCombiner() const override

Definition SystemZInstrInfo.h:291

bool hasDisplacementPairInsn(unsigned Opcode) const

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override

Commutes the operands in the given instruction by changing the operands order and/or changing the ins...

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

SystemZII::Branch getBranchInfo(const MachineInstr &MI) const

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const

bool expandPostRAPseudo(MachineInstr &MBBI) const override

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const

bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const

MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override

SystemZInstrInfo(const SystemZSubtarget &STI)

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

Definition SystemZInstrInfo.h:32

static unsigned getCCValues(unsigned int Flags)

Definition SystemZInstrInfo.h:57

static unsigned getCompareZeroCCMask(unsigned int Flags)

Definition SystemZInstrInfo.h:61

BranchType

Definition SystemZInstrInfo.h:84

@ BranchCL