TargetLoweringBase.cpp Source File (original) (raw)

58#include

59#include

60#include

61#include

62#include

63#include

64#include

66using namespace llvm;

69 "jump-is-expensive", cl::init(false),

70 cl::desc("Do not create extra branches to split comparison logic."),

75 cl::desc("Set minimum number of entries to use a jump table."));

79 cl::desc("Set maximum size of jump tables."));

84 cl::desc("Minimum density for building a jump table in "

85 "a normal function"));

90 cl::desc("Minimum density for building a jump table in "

91 "an optsize function"));

95 cl::desc("Set minimum of largest number of comparisons "

96 "to use bit test for switch."));

100

101

103 cl::desc("Don't mutate strict-float node to a legalize node"),

105

107 if (VT == MVT::i16)

108 return RTLIB::SHL_I16;

109 if (VT == MVT::i32)

110 return RTLIB::SHL_I32;

111 if (VT == MVT::i64)

112 return RTLIB::SHL_I64;

113 if (VT == MVT::i128)

114 return RTLIB::SHL_I128;

115

116 return RTLIB::UNKNOWN_LIBCALL;

117}

118

120 if (VT == MVT::i16)

121 return RTLIB::SRL_I16;

122 if (VT == MVT::i32)

123 return RTLIB::SRL_I32;

124 if (VT == MVT::i64)

125 return RTLIB::SRL_I64;

126 if (VT == MVT::i128)

127 return RTLIB::SRL_I128;

128

129 return RTLIB::UNKNOWN_LIBCALL;

130}

131

133 if (VT == MVT::i16)

134 return RTLIB::SRA_I16;

135 if (VT == MVT::i32)

136 return RTLIB::SRA_I32;

137 if (VT == MVT::i64)

138 return RTLIB::SRA_I64;

139 if (VT == MVT::i128)

140 return RTLIB::SRA_I128;

141

142 return RTLIB::UNKNOWN_LIBCALL;

143}

144

146 if (VT == MVT::i16)

147 return RTLIB::MUL_I16;

148 if (VT == MVT::i32)

149 return RTLIB::MUL_I32;

150 if (VT == MVT::i64)

151 return RTLIB::MUL_I64;

152 if (VT == MVT::i128)

153 return RTLIB::MUL_I128;

154 return RTLIB::UNKNOWN_LIBCALL;

155}

156

158 if (VT == MVT::i32)

159 return RTLIB::MULO_I32;

160 if (VT == MVT::i64)

161 return RTLIB::MULO_I64;

162 if (VT == MVT::i128)

163 return RTLIB::MULO_I128;

164 return RTLIB::UNKNOWN_LIBCALL;

165}

166

168 if (VT == MVT::i16)

169 return RTLIB::SDIV_I16;

170 if (VT == MVT::i32)

171 return RTLIB::SDIV_I32;

172 if (VT == MVT::i64)

173 return RTLIB::SDIV_I64;

174 if (VT == MVT::i128)

175 return RTLIB::SDIV_I128;

176 return RTLIB::UNKNOWN_LIBCALL;

177}

178

180 if (VT == MVT::i16)

181 return RTLIB::UDIV_I16;

182 if (VT == MVT::i32)

183 return RTLIB::UDIV_I32;

184 if (VT == MVT::i64)

185 return RTLIB::UDIV_I64;

186 if (VT == MVT::i128)

187 return RTLIB::UDIV_I128;

188 return RTLIB::UNKNOWN_LIBCALL;

189}

190

192 if (VT == MVT::i16)

193 return RTLIB::SREM_I16;

194 if (VT == MVT::i32)

195 return RTLIB::SREM_I32;

196 if (VT == MVT::i64)

197 return RTLIB::SREM_I64;

198 if (VT == MVT::i128)

199 return RTLIB::SREM_I128;

200 return RTLIB::UNKNOWN_LIBCALL;

201}

202

204 if (VT == MVT::i16)

205 return RTLIB::UREM_I16;

206 if (VT == MVT::i32)

207 return RTLIB::UREM_I32;

208 if (VT == MVT::i64)

209 return RTLIB::UREM_I64;

210 if (VT == MVT::i128)

211 return RTLIB::UREM_I128;

212 return RTLIB::UNKNOWN_LIBCALL;

213}

214

216 if (VT == MVT::i32)

217 return RTLIB::CTPOP_I32;

218 if (VT == MVT::i64)

219 return RTLIB::CTPOP_I64;

220 if (VT == MVT::i128)

221 return RTLIB::CTPOP_I128;

222 return RTLIB::UNKNOWN_LIBCALL;

223}

224

225

226

228 RTLIB::Libcall Call_F32,

229 RTLIB::Libcall Call_F64,

230 RTLIB::Libcall Call_F80,

231 RTLIB::Libcall Call_F128,

232 RTLIB::Libcall Call_PPCF128) {

233 return

234 VT == MVT::f32 ? Call_F32 :

235 VT == MVT::f64 ? Call_F64 :

236 VT == MVT::f80 ? Call_F80 :

237 VT == MVT::f128 ? Call_F128 :

238 VT == MVT::ppcf128 ? Call_PPCF128 :

239 RTLIB::UNKNOWN_LIBCALL;

240}

241

242

243

245 if (OpVT == MVT::f16) {

246 if (RetVT == MVT::f32)

247 return FPEXT_F16_F32;

248 if (RetVT == MVT::f64)

249 return FPEXT_F16_F64;

250 if (RetVT == MVT::f80)

251 return FPEXT_F16_F80;

252 if (RetVT == MVT::f128)

253 return FPEXT_F16_F128;

254 } else if (OpVT == MVT::f32) {

255 if (RetVT == MVT::f64)

256 return FPEXT_F32_F64;

257 if (RetVT == MVT::f128)

258 return FPEXT_F32_F128;

259 if (RetVT == MVT::ppcf128)

260 return FPEXT_F32_PPCF128;

261 } else if (OpVT == MVT::f64) {

262 if (RetVT == MVT::f128)

263 return FPEXT_F64_F128;

264 else if (RetVT == MVT::ppcf128)

265 return FPEXT_F64_PPCF128;

266 } else if (OpVT == MVT::f80) {

267 if (RetVT == MVT::f128)

268 return FPEXT_F80_F128;

269 } else if (OpVT == MVT::bf16) {

270 if (RetVT == MVT::f32)

271 return FPEXT_BF16_F32;

272 }

273

274 return UNKNOWN_LIBCALL;

275}

276

277

278

280 if (RetVT == MVT::f16) {

281 if (OpVT == MVT::f32)

282 return FPROUND_F32_F16;

283 if (OpVT == MVT::f64)

284 return FPROUND_F64_F16;

285 if (OpVT == MVT::f80)

286 return FPROUND_F80_F16;

287 if (OpVT == MVT::f128)

288 return FPROUND_F128_F16;

289 if (OpVT == MVT::ppcf128)

290 return FPROUND_PPCF128_F16;

291 } else if (RetVT == MVT::bf16) {

292 if (OpVT == MVT::f32)

293 return FPROUND_F32_BF16;

294 if (OpVT == MVT::f64)

295 return FPROUND_F64_BF16;

296 if (OpVT == MVT::f80)

297 return FPROUND_F80_BF16;

298 if (OpVT == MVT::f128)

299 return FPROUND_F128_BF16;

300 } else if (RetVT == MVT::f32) {

301 if (OpVT == MVT::f64)

302 return FPROUND_F64_F32;

303 if (OpVT == MVT::f80)

304 return FPROUND_F80_F32;

305 if (OpVT == MVT::f128)

306 return FPROUND_F128_F32;

307 if (OpVT == MVT::ppcf128)

308 return FPROUND_PPCF128_F32;

309 } else if (RetVT == MVT::f64) {

310 if (OpVT == MVT::f80)

311 return FPROUND_F80_F64;

312 if (OpVT == MVT::f128)

313 return FPROUND_F128_F64;

314 if (OpVT == MVT::ppcf128)

315 return FPROUND_PPCF128_F64;

316 } else if (RetVT == MVT::f80) {

317 if (OpVT == MVT::f128)

318 return FPROUND_F128_F80;

319 }

320

321 return UNKNOWN_LIBCALL;

322}

323

324

325

327 if (OpVT == MVT::f16) {

328 if (RetVT == MVT::i32)

329 return FPTOSINT_F16_I32;

330 if (RetVT == MVT::i64)

331 return FPTOSINT_F16_I64;

332 if (RetVT == MVT::i128)

333 return FPTOSINT_F16_I128;

334 } else if (OpVT == MVT::f32) {

335 if (RetVT == MVT::i32)

336 return FPTOSINT_F32_I32;

337 if (RetVT == MVT::i64)

338 return FPTOSINT_F32_I64;

339 if (RetVT == MVT::i128)

340 return FPTOSINT_F32_I128;

341 } else if (OpVT == MVT::f64) {

342 if (RetVT == MVT::i32)

343 return FPTOSINT_F64_I32;

344 if (RetVT == MVT::i64)

345 return FPTOSINT_F64_I64;

346 if (RetVT == MVT::i128)

347 return FPTOSINT_F64_I128;

348 } else if (OpVT == MVT::f80) {

349 if (RetVT == MVT::i32)

350 return FPTOSINT_F80_I32;

351 if (RetVT == MVT::i64)

352 return FPTOSINT_F80_I64;

353 if (RetVT == MVT::i128)

354 return FPTOSINT_F80_I128;

355 } else if (OpVT == MVT::f128) {

356 if (RetVT == MVT::i32)

357 return FPTOSINT_F128_I32;

358 if (RetVT == MVT::i64)

359 return FPTOSINT_F128_I64;

360 if (RetVT == MVT::i128)

361 return FPTOSINT_F128_I128;

362 } else if (OpVT == MVT::ppcf128) {

363 if (RetVT == MVT::i32)

364 return FPTOSINT_PPCF128_I32;

365 if (RetVT == MVT::i64)

366 return FPTOSINT_PPCF128_I64;

367 if (RetVT == MVT::i128)

368 return FPTOSINT_PPCF128_I128;

369 }

370 return UNKNOWN_LIBCALL;

371}

372

373

374

376 if (OpVT == MVT::f16) {

377 if (RetVT == MVT::i32)

378 return FPTOUINT_F16_I32;

379 if (RetVT == MVT::i64)

380 return FPTOUINT_F16_I64;

381 if (RetVT == MVT::i128)

382 return FPTOUINT_F16_I128;

383 } else if (OpVT == MVT::f32) {

384 if (RetVT == MVT::i32)

385 return FPTOUINT_F32_I32;

386 if (RetVT == MVT::i64)

387 return FPTOUINT_F32_I64;

388 if (RetVT == MVT::i128)

389 return FPTOUINT_F32_I128;

390 } else if (OpVT == MVT::f64) {

391 if (RetVT == MVT::i32)

392 return FPTOUINT_F64_I32;

393 if (RetVT == MVT::i64)

394 return FPTOUINT_F64_I64;

395 if (RetVT == MVT::i128)

396 return FPTOUINT_F64_I128;

397 } else if (OpVT == MVT::f80) {

398 if (RetVT == MVT::i32)

399 return FPTOUINT_F80_I32;

400 if (RetVT == MVT::i64)

401 return FPTOUINT_F80_I64;

402 if (RetVT == MVT::i128)

403 return FPTOUINT_F80_I128;

404 } else if (OpVT == MVT::f128) {

405 if (RetVT == MVT::i32)

406 return FPTOUINT_F128_I32;

407 if (RetVT == MVT::i64)

408 return FPTOUINT_F128_I64;

409 if (RetVT == MVT::i128)

410 return FPTOUINT_F128_I128;

411 } else if (OpVT == MVT::ppcf128) {

412 if (RetVT == MVT::i32)

413 return FPTOUINT_PPCF128_I32;

414 if (RetVT == MVT::i64)

415 return FPTOUINT_PPCF128_I64;

416 if (RetVT == MVT::i128)

417 return FPTOUINT_PPCF128_I128;

418 }

419 return UNKNOWN_LIBCALL;

420}

421

422

423

425 if (OpVT == MVT::i32) {

426 if (RetVT == MVT::f16)

427 return SINTTOFP_I32_F16;

428 if (RetVT == MVT::f32)

429 return SINTTOFP_I32_F32;

430 if (RetVT == MVT::f64)

431 return SINTTOFP_I32_F64;

432 if (RetVT == MVT::f80)

433 return SINTTOFP_I32_F80;

434 if (RetVT == MVT::f128)

435 return SINTTOFP_I32_F128;

436 if (RetVT == MVT::ppcf128)

437 return SINTTOFP_I32_PPCF128;

438 } else if (OpVT == MVT::i64) {

439 if (RetVT == MVT::bf16)

440 return SINTTOFP_I64_BF16;

441 if (RetVT == MVT::f16)

442 return SINTTOFP_I64_F16;

443 if (RetVT == MVT::f32)

444 return SINTTOFP_I64_F32;

445 if (RetVT == MVT::f64)

446 return SINTTOFP_I64_F64;

447 if (RetVT == MVT::f80)

448 return SINTTOFP_I64_F80;

449 if (RetVT == MVT::f128)

450 return SINTTOFP_I64_F128;

451 if (RetVT == MVT::ppcf128)

452 return SINTTOFP_I64_PPCF128;

453 } else if (OpVT == MVT::i128) {

454 if (RetVT == MVT::f16)

455 return SINTTOFP_I128_F16;

456 if (RetVT == MVT::f32)

457 return SINTTOFP_I128_F32;

458 if (RetVT == MVT::f64)

459 return SINTTOFP_I128_F64;

460 if (RetVT == MVT::f80)

461 return SINTTOFP_I128_F80;

462 if (RetVT == MVT::f128)

463 return SINTTOFP_I128_F128;

464 if (RetVT == MVT::ppcf128)

465 return SINTTOFP_I128_PPCF128;

466 }

467 return UNKNOWN_LIBCALL;

468}

469

470

471

473 if (OpVT == MVT::i32) {

474 if (RetVT == MVT::f16)

475 return UINTTOFP_I32_F16;

476 if (RetVT == MVT::f32)

477 return UINTTOFP_I32_F32;

478 if (RetVT == MVT::f64)

479 return UINTTOFP_I32_F64;

480 if (RetVT == MVT::f80)

481 return UINTTOFP_I32_F80;

482 if (RetVT == MVT::f128)

483 return UINTTOFP_I32_F128;

484 if (RetVT == MVT::ppcf128)

485 return UINTTOFP_I32_PPCF128;

486 } else if (OpVT == MVT::i64) {

487 if (RetVT == MVT::bf16)

488 return UINTTOFP_I64_BF16;

489 if (RetVT == MVT::f16)

490 return UINTTOFP_I64_F16;

491 if (RetVT == MVT::f32)

492 return UINTTOFP_I64_F32;

493 if (RetVT == MVT::f64)

494 return UINTTOFP_I64_F64;

495 if (RetVT == MVT::f80)

496 return UINTTOFP_I64_F80;

497 if (RetVT == MVT::f128)

498 return UINTTOFP_I64_F128;

499 if (RetVT == MVT::ppcf128)

500 return UINTTOFP_I64_PPCF128;

501 } else if (OpVT == MVT::i128) {

502 if (RetVT == MVT::f16)

503 return UINTTOFP_I128_F16;

504 if (RetVT == MVT::f32)

505 return UINTTOFP_I128_F32;

506 if (RetVT == MVT::f64)

507 return UINTTOFP_I128_F64;

508 if (RetVT == MVT::f80)

509 return UINTTOFP_I128_F80;

510 if (RetVT == MVT::f128)

511 return UINTTOFP_I128_F128;

512 if (RetVT == MVT::ppcf128)

513 return UINTTOFP_I128_PPCF128;

514 }

515 return UNKNOWN_LIBCALL;

516}

517

519 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,

520 POWI_PPCF128);

521}

522

524 return getFPLibCall(RetVT, POW_F32, POW_F64, POW_F80, POW_F128, POW_PPCF128);

525}

526

528 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,

529 LDEXP_PPCF128);

530}

531

533 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,

534 FREXP_PPCF128);

535}

536

538 return getFPLibCall(RetVT, SIN_F32, SIN_F64, SIN_F80, SIN_F128, SIN_PPCF128);

539}

540

542 return getFPLibCall(RetVT, COS_F32, COS_F64, COS_F80, COS_F128, COS_PPCF128);

543}

544

546

549 return RTLIB::UNKNOWN_LIBCALL;

551 case MVT::v4f32:

552 return RTLIB::SINCOS_V4F32;

553 case MVT::v2f64:

554 return RTLIB::SINCOS_V2F64;

555 case MVT::nxv4f32:

556 return RTLIB::SINCOS_NXV4F32;

557 case MVT::nxv2f64:

558 return RTLIB::SINCOS_NXV2F64;

559 default:

560 return RTLIB::UNKNOWN_LIBCALL;

561 }

562 }

563

564 return getFPLibCall(RetVT, SINCOS_F32, SINCOS_F64, SINCOS_F80, SINCOS_F128,

565 SINCOS_PPCF128);

566}

567

569

572 return RTLIB::UNKNOWN_LIBCALL;

574 case MVT::v4f32:

575 return RTLIB::SINCOSPI_V4F32;

576 case MVT::v2f64:

577 return RTLIB::SINCOSPI_V2F64;

578 case MVT::nxv4f32:

579 return RTLIB::SINCOSPI_NXV4F32;

580 case MVT::nxv2f64:

581 return RTLIB::SINCOSPI_NXV2F64;

582 default:

583 return RTLIB::UNKNOWN_LIBCALL;

584 }

585 }

586

587 return getFPLibCall(RetVT, SINCOSPI_F32, SINCOSPI_F64, SINCOSPI_F80,

588 SINCOSPI_F128, SINCOSPI_PPCF128);

589}

590

592 return getFPLibCall(RetVT, SINCOS_STRET_F32, SINCOS_STRET_F64,

593 UNKNOWN_LIBCALL, UNKNOWN_LIBCALL, UNKNOWN_LIBCALL);

594}

595

597

600 return RTLIB::UNKNOWN_LIBCALL;

602 case MVT::v4f32:

603 return RTLIB::MODF_V4F32;

604 case MVT::v2f64:

605 return RTLIB::MODF_V2F64;

606 case MVT::nxv4f32:

607 return RTLIB::MODF_NXV4F32;

608 case MVT::nxv2f64:

609 return RTLIB::MODF_NXV2F64;

610 default:

611 return RTLIB::UNKNOWN_LIBCALL;

612 }

613 }

614

615 return getFPLibCall(RetVT, MODF_F32, MODF_F64, MODF_F80, MODF_F128,

616 MODF_PPCF128);

617}

618

620 if (VT == MVT::f32)

621 return RTLIB::LROUND_F32;

622 if (VT == MVT::f64)

623 return RTLIB::LROUND_F64;

624 if (VT == MVT::f80)

625 return RTLIB::LROUND_F80;

626 if (VT == MVT::f128)

627 return RTLIB::LROUND_F128;

628 if (VT == MVT::ppcf128)

629 return RTLIB::LROUND_PPCF128;

630

631 return RTLIB::UNKNOWN_LIBCALL;

632}

633

635 if (VT == MVT::f32)

636 return RTLIB::LLROUND_F32;

637 if (VT == MVT::f64)

638 return RTLIB::LLROUND_F64;

639 if (VT == MVT::f80)

640 return RTLIB::LLROUND_F80;

641 if (VT == MVT::f128)

642 return RTLIB::LLROUND_F128;

643 if (VT == MVT::ppcf128)

644 return RTLIB::LLROUND_PPCF128;

645

646 return RTLIB::UNKNOWN_LIBCALL;

647}

648

650 if (VT == MVT::f32)

651 return RTLIB::LRINT_F32;

652 if (VT == MVT::f64)

653 return RTLIB::LRINT_F64;

654 if (VT == MVT::f80)

655 return RTLIB::LRINT_F80;

656 if (VT == MVT::f128)

657 return RTLIB::LRINT_F128;

658 if (VT == MVT::ppcf128)

659 return RTLIB::LRINT_PPCF128;

660 return RTLIB::UNKNOWN_LIBCALL;

661}

662

664 if (VT == MVT::f32)

665 return RTLIB::LLRINT_F32;

666 if (VT == MVT::f64)

667 return RTLIB::LLRINT_F64;

668 if (VT == MVT::f80)

669 return RTLIB::LLRINT_F80;

670 if (VT == MVT::f128)

671 return RTLIB::LLRINT_F128;

672 if (VT == MVT::ppcf128)

673 return RTLIB::LLRINT_PPCF128;

674 return RTLIB::UNKNOWN_LIBCALL;

675}

676

680 unsigned ModeN, ModelN;

681 switch (MemSize) {

682 case 1:

683 ModeN = 0;

684 break;

685 case 2:

686 ModeN = 1;

687 break;

688 case 4:

689 ModeN = 2;

690 break;

691 case 8:

692 ModeN = 3;

693 break;

694 case 16:

695 ModeN = 4;

696 break;

697 default:

698 return RTLIB::UNKNOWN_LIBCALL;

699 }

700

701 switch (Order) {

703 ModelN = 0;

704 break;

706 ModelN = 1;

707 break;

709 ModelN = 2;

710 break;

713 ModelN = 3;

714 break;

715 default:

716 return UNKNOWN_LIBCALL;

717 }

718

719 return LC[ModeN][ModelN];

720}

721

723 MVT VT) {

725 return UNKNOWN_LIBCALL;

727

728#define LCALLS(A, B) \

729 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }

730#define LCALL5(A) \

731 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)

732 switch (Opc) {

733 case ISD::ATOMIC_CMP_SWAP: {

734 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};

736 }

737 case ISD::ATOMIC_SWAP: {

738 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};

740 }

741 case ISD::ATOMIC_LOAD_ADD: {

742 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};

744 }

745 case ISD::ATOMIC_LOAD_OR: {

746 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};

748 }

749 case ISD::ATOMIC_LOAD_CLR: {

750 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};

752 }

753 case ISD::ATOMIC_LOAD_XOR: {

754 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};

756 }

757 default:

758 return UNKNOWN_LIBCALL;

759 }

760#undef LCALLS

761#undef LCALL5

762}

763

765#define OP_TO_LIBCALL(Name, Enum) \

766 case Name: \

767 switch (VT.SimpleTy) { \

768 default: \

769 return UNKNOWN_LIBCALL; \

770 case MVT::i8: \

771 return Enum##_1; \

772 case MVT::i16: \

773 return Enum##_2; \

774 case MVT::i32: \

775 return Enum##_4; \

776 case MVT::i64: \

777 return Enum##_8; \

778 case MVT::i128: \

779 return Enum##_16; \

780 }

781

782 switch (Opc) {

783 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)

784 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)

785 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)

786 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)

787 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)

788 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)

789 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)

790 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)

791 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)

792 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)

793 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)

794 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)

795 }

796

797#undef OP_TO_LIBCALL

798

799 return UNKNOWN_LIBCALL;

800}

801

803 switch (ElementSize) {

804 case 1:

805 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;

806 case 2:

807 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;

808 case 4:

809 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;

810 case 8:

811 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;

812 case 16:

813 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;

814 default:

815 return UNKNOWN_LIBCALL;

816 }

817}

818

820 switch (ElementSize) {

821 case 1:

822 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;

823 case 2:

824 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;

825 case 4:

826 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;

827 case 8:

828 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;

829 case 16:

830 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;

831 default:

832 return UNKNOWN_LIBCALL;

833 }

834}

835

837 switch (ElementSize) {

838 case 1:

839 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;

840 case 2:

841 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;

842 case 4:

843 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;

844 case 8:

845 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;

846 case 16:

847 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;

848 default:

849 return UNKNOWN_LIBCALL;

850 }

851}

852

854 RTLIB::LibcallImpl Impl) const {

855 switch (Impl) {

856 case RTLIB::impl___aeabi_dcmpeq__une:

857 case RTLIB::impl___aeabi_fcmpeq__une:

858

860 case RTLIB::impl___aeabi_dcmpeq__oeq:

861 case RTLIB::impl___aeabi_fcmpeq__oeq:

862

864 case RTLIB::impl___aeabi_dcmplt:

865 case RTLIB::impl___aeabi_dcmple:

866 case RTLIB::impl___aeabi_dcmpge:

867 case RTLIB::impl___aeabi_dcmpgt:

868 case RTLIB::impl___aeabi_dcmpun:

869 case RTLIB::impl___aeabi_fcmplt:

870 case RTLIB::impl___aeabi_fcmple:

871 case RTLIB::impl___aeabi_fcmpge:

872 case RTLIB::impl___aeabi_fcmpgt:

873

874

876 default:

877 break;

878 }

879

880

881

882

883

884

885

887 switch (LC) {

888 case RTLIB::OEQ_F32:

889 case RTLIB::OEQ_F64:

890 case RTLIB::OEQ_F128:

891 case RTLIB::OEQ_PPCF128:

893 case RTLIB::UNE_F32:

894 case RTLIB::UNE_F64:

895 case RTLIB::UNE_F128:

896 case RTLIB::UNE_PPCF128:

898 case RTLIB::OGE_F32:

899 case RTLIB::OGE_F64:

900 case RTLIB::OGE_F128:

901 case RTLIB::OGE_PPCF128:

903 case RTLIB::OLT_F32:

904 case RTLIB::OLT_F64:

905 case RTLIB::OLT_F128:

906 case RTLIB::OLT_PPCF128:

908 case RTLIB::OLE_F32:

909 case RTLIB::OLE_F64:

910 case RTLIB::OLE_F128:

911 case RTLIB::OLE_PPCF128:

913 case RTLIB::OGT_F32:

914 case RTLIB::OGT_F64:

915 case RTLIB::OGT_F128:

916 case RTLIB::OGT_PPCF128:

918 case RTLIB::UO_F32:

919 case RTLIB::UO_F64:

920 case RTLIB::UO_F128:

921 case RTLIB::UO_PPCF128:

923 default:

925 }

926}

927

928

931 : TM(tm),

932 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,

934 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),

935 Libcalls(RuntimeLibcallInfo, STI) {

937

938

944 HasExtractBitsInsn = false;

948 StackPointerRegisterToSaveRestore = 0;

955 MaxBytesForAlignment = 0;

956 MaxAtomicSizeInBitsSupported = 0;

957

958

959

960 MaxDivRemBitWidthSupported = 128;

961

963

964 MinCmpXchgSizeInBits = 0;

965 SupportsUnalignedAtomics = false;

966

968}

969

970

971

973

975

976 memset(OpActions, 0, sizeof(OpActions));

977 memset(LoadExtActions, 0, sizeof(LoadExtActions));

978 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));

979 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));

980 memset(CondCodeActions, 0, sizeof(CondCodeActions));

982 llvm::fill(TargetDAGCombineArray, 0);

983

984

989

990

991

994 for (MVT VT : {MVT::i2, MVT::i4})

995 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;

996 }

998 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {

1002 }

1003 }

1006 for (MVT VT : {MVT::i2, MVT::i4}) {

1011 }

1012 }

1013

1019 }

1020 }

1021

1022

1024

1031 }

1032

1033

1035

1036

1038 ISD::FMINNUM, ISD::FMAXNUM,

1039 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,

1040 ISD::FMINIMUM, ISD::FMAXIMUM,

1041 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,

1055 ISD::FLOG, ISD::FLOG2,

1056 ISD::FLOG10, ISD::FEXP,

1057 ISD::FEXP2, ISD::FEXP10,

1058 ISD::FFLOOR, ISD::FNEARBYINT,

1059 ISD::FCEIL, ISD::FRINT,

1060 ISD::FTRUNC, ISD::FROUNDEVEN,

1061 ISD::FTAN, ISD::FACOS,

1062 ISD::FASIN, ISD::FATAN,

1063 ISD::FCOSH, ISD::FSINH,

1064 ISD::FTANH, ISD::FATAN2,

1067

1068

1072

1073

1077

1078

1081

1082

1084

1085

1089

1090

1092

1093

1097

1098

1101

1103

1104

1105 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,

1106 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},

1108

1109

1110 if (VT.isVector())

1115 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},

1117

1118

1119#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \

1120 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);

1121#include "llvm/IR/ConstrainedOps.def"

1122

1123

1125

1126

1128 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,

1129 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,

1130 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,

1131 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,

1132 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,

1133 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},

1135

1136

1138

1139

1141

1142

1143#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \

1144 setOperationAction(ISD::SDOPC, VT, Expand);

1145#include "llvm/IR/VPIntrinsics.def"

1146

1147

1149

1152

1153

1157

1159 }

1160

1161

1163

1164

1166

1167

1169

1170

1171

1172

1174 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},

1176

1177

1179 {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Expand);

1180

1181

1182 setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},

1183 {MVT::f32, MVT::f64, MVT::f128}, LibCall);

1184

1185 setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,

1186 ISD::FSINH, ISD::FTANH, ISD::FATAN2},

1188

1190

1191

1192

1194

1196

1199

1200 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {

1203 }

1205

1206

1207

1209}

1210

1215

1218 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");

1220 return LHSTy;

1222

1223

1225 ShiftVT = MVT::i32;

1227 "ShiftVT is still too small!");

1228 return ShiftVT;

1229}

1230

1233 switch (Op) {

1234 default:

1235 return false;

1240 return true;

1241 }

1242}

1243

1245 unsigned DestAS) const {

1246 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);

1247}

1248

1252

1254 if (EC.isScalable())

1255 CR = CR.umul_sat(*VScaleRange);

1256

1257 if (ZeroIsPoison)

1259

1261 EltWidth = std::min(EltWidth, CR.getActiveBits());

1262 EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8);

1263

1264 return EltWidth;

1265}

1266

1268

1270 JumpIsExpensive = isExpensive;

1271}

1272

1275

1278 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));

1279 MVT NVT = TransformToType[SVT.SimpleTy];

1281

1286 "Promote may not follow Expand or Promote");

1287

1289 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));

1293 }

1294

1295

1299

1302 assert(NVT != VT && "Unable to round integer VT");

1304

1306 return NextStep;

1307

1309 }

1310

1313 }

1314

1315

1318

1319

1322

1323

1324

1325

1327

1328

1333 }

1334

1335

1337

1338

1339

1345 }

1346

1347

1348

1349

1350

1351 EVT OldEltVT = EltVT;

1352 while (true) {

1353

1354

1357

1358

1359

1360

1361

1363 break;

1364

1365

1367

1368 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)

1371 }

1372

1373

1374

1375 EltVT = OldEltVT;

1376 }

1377

1378

1379

1380 while (true) {

1381

1383

1384

1385

1386

1388 break;

1390 if (LargerVector == MVT())

1391 break;

1392

1393

1394 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)

1396 }

1397

1398

1402 }

1403

1406

1407

1411}

1412

1414 unsigned &NumIntermediates,

1415 MVT &RegisterVT,

1417

1420

1421 unsigned NumVectorRegs = 1;

1422

1423

1424

1427 "Splitting or widening of non-power-of-2 MVTs is not implemented.");

1428

1429

1430

1432

1433 NumVectorRegs = EC.getKnownMinValue();

1435 }

1436

1437

1438

1439

1440 while (EC.getKnownMinValue() > 1 &&

1442 EC = EC.divideCoefficientBy(2);

1443 NumVectorRegs <<= 1;

1444 }

1445

1446 NumIntermediates = NumVectorRegs;

1447

1450 NewVT = EltTy;

1451 IntermediateVT = NewVT;

1452

1454

1455

1457

1459 RegisterVT = DestVT;

1460 if (EVT(DestVT).bitsLT(NewVT))

1462

1463

1464

1465 return NumVectorRegs;

1466}

1467

1468

1469

1472 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)

1474 return true;

1475 return false;

1476}

1477

1478

1479

1486

1487

1488

1489

1490

1491

1492

1493

1494

1495

1496

1497

1498

1500 [](MachineOperand &Operand) { return Operand.isFI(); }))

1501 return MBB;

1502

1504

1505

1507

1508 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {

1510 if (!MO.isFI()) {

1511

1512

1513

1514

1515 unsigned TiedTo = i;

1517 TiedTo = MI->findTiedOperandIdx(i);

1518 MIB.add(MO);

1519 if (TiedTo < i)

1521 continue;

1522 }

1523

1524

1525

1527

1528

1530

1531

1532

1533

1534 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");

1535 MIB.addImm(StackMaps::IndirectMemRefOp);

1537 MIB.add(MO);

1539 } else {

1540

1541

1542 MIB.addImm(StackMaps::DirectMemRefOp);

1543 MIB.add(MO);

1545 }

1546

1547 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");

1548

1549

1551

1552

1553

1554 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {

1560 }

1561 }

1563 MI->eraseFromParent();

1564 return MBB;

1565}

1566

1567

1568

1569

1570

1571

1572

1573std::pair<const TargetRegisterClass *, uint8_t>

1575 MVT VT) const {

1577 if (!RC)

1578 return std::make_pair(RC, 0);

1579

1580

1581 BitVector SuperRegRC(TRI->getNumRegClasses());

1584

1585

1587 for (unsigned i : SuperRegRC.set_bits()) {

1589

1590 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))

1591 continue;

1593 continue;

1594 BestRC = SuperRC;

1595 }

1596 return std::make_pair(BestRC, 1);

1597}

1598

1599

1600

1603

1605 NumRegistersForVT[i] = 1;

1607 }

1608

1609 NumRegistersForVT[MVT::isVoid] = 0;

1610

1611

1612 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;

1613 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)

1614 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");

1615

1616

1617

1618 for (unsigned ExpandedReg = LargestIntReg + 1;

1619 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {

1620 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];

1625 }

1626

1627

1628

1629 unsigned LegalIntReg = LargestIntReg;

1630 for (unsigned IntReg = LargestIntReg - 1;

1631 IntReg >= (unsigned)MVT::i1; --IntReg) {

1634 LegalIntReg = IntReg;

1635 } else {

1636 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =

1639 }

1640 }

1641

1642

1645 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];

1646 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;

1647 TransformToType[MVT::ppcf128] = MVT::f64;

1648 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);

1649 } else {

1650 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];

1651 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];

1652 TransformToType[MVT::ppcf128] = MVT::i128;

1653 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);

1654 }

1655 }

1656

1657

1658

1660 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];

1661 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];

1662 TransformToType[MVT::f128] = MVT::i128;

1663 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);

1664 }

1665

1666

1667

1669 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];

1670 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];

1671 TransformToType[MVT::f80] = MVT::i32;

1672 ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);

1673 }

1674

1675

1676

1678 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];

1679 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];

1680 TransformToType[MVT::f64] = MVT::i64;

1681 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);

1682 }

1683

1684

1685

1687 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];

1688 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];

1689 TransformToType[MVT::f32] = MVT::i32;

1690 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);

1691 }

1692

1693

1694

1695

1697

1700

1701 if (!UseFPRegsForHalfType) {

1702 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];

1703 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];

1704 } else {

1705 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];

1706 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];

1707 }

1708 TransformToType[MVT::f16] = MVT::f32;

1709 if (SoftPromoteHalfType) {

1711 } else {

1713 }

1714 }

1715

1716

1717

1718

1720 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];

1721 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];

1722 TransformToType[MVT::bf16] = MVT::f32;

1724 }

1725

1726

1727 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;

1728 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {

1731 continue;

1732

1735 bool IsLegalWiderType = false;

1738 switch (PreferredAction) {

1741 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :

1742 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;

1743

1744

1745 for (unsigned nVT = i + 1;

1748

1749

1752 TransformToType[i] = SVT;

1753 RegisterTypeForVT[i] = SVT;

1754 NumRegistersForVT[i] = 1;

1756 IsLegalWiderType = true;

1757 break;

1758 }

1759 }

1760 if (IsLegalWiderType)

1761 break;

1762 [[fallthrough]];

1763 }

1764

1767

1768 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {

1773 EC.getKnownMinValue() &&

1775 TransformToType[i] = SVT;

1776 RegisterTypeForVT[i] = SVT;

1777 NumRegistersForVT[i] = 1;

1779 IsLegalWiderType = true;

1780 break;

1781 }

1782 }

1783 if (IsLegalWiderType)

1784 break;

1785 } else {

1786

1789 TransformToType[i] = NVT;

1791 RegisterTypeForVT[i] = NVT;

1792 NumRegistersForVT[i] = 1;

1793 break;

1794 }

1795 }

1796 [[fallthrough]];

1797

1800 MVT IntermediateVT;

1801 MVT RegisterVT;

1802 unsigned NumIntermediates;

1804 NumIntermediates, RegisterVT, this);

1805 NumRegistersForVT[i] = NumRegisters;

1806 assert(NumRegistersForVT[i] == NumRegisters &&

1807 "NumRegistersForVT size cannot represent NumRegisters!");

1808 RegisterTypeForVT[i] = RegisterVT;

1809

1811 if (NVT == VT) {

1812

1813 TransformToType[i] = MVT::Other;

1818 else if (EC.getKnownMinValue() > 1)

1820 else

1821 ValueTypeActions.setTypeAction(VT, EC.isScalable()

1824 } else {

1825 TransformToType[i] = NVT;

1827 }

1828 break;

1829 }

1830 default:

1832 }

1833 }

1834

1835

1836

1837

1838

1839

1844 RepRegClassForVT[i] = RRC;

1845 RepRegClassCostForVT[i] = Cost;

1846 }

1847}

1848

1850 EVT VT) const {

1851 assert(!VT.isVector() && "No default SetCC type for vectors!");

1853}

1854

1856 return MVT::i32;

1857}

1858

1859

1860

1861

1862

1863

1864

1865

1866

1868 EVT VT, EVT &IntermediateVT,

1869 unsigned &NumIntermediates,

1870 MVT &RegisterVT) const {

1872

1873

1874

1875

1876

1877

1883 IntermediateVT = RegisterEVT;

1885 NumIntermediates = 1;

1886 return 1;

1887 }

1888 }

1889

1890

1892

1893 unsigned NumVectorRegs = 1;

1894

1895

1896

1899 EVT PartVT = VT;

1900 do {

1901

1903 PartVT = LK.second;

1904 } while (LK.first != TypeLegal);

1905

1908 "Don't know how to legalize this scalable vector type");

1909 }

1910

1911 NumIntermediates =

1914 IntermediateVT = PartVT;

1916 return NumIntermediates;

1917 }

1918

1919

1920

1924 }

1925

1926

1927

1931 NumVectorRegs <<= 1;

1932 }

1933

1934 NumIntermediates = NumVectorRegs;

1935

1938 NewVT = EltTy;

1939 IntermediateVT = NewVT;

1940

1942 RegisterVT = DestVT;

1943

1944 if (EVT(DestVT).bitsLT(NewVT)) {

1946

1949 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());

1950 }

1951

1952

1953

1954 return NumVectorRegs;

1955}

1956

1962

1963

1964

1965

1966

1967 const bool OptForSize =

1971

1972

1973

1974 return (OptForSize || Range <= MaxJumpTableSize) &&

1975 (NumCases * 100 >= Range * MinDensity);

1976}

1977

1979 EVT ConditionVT) const {

1981}

1982

1983

1984

1985

1986

1988 AttributeList attr,

1993 unsigned NumValues = Types.size();

1994 if (NumValues == 0) return;

1995

1996 for (Type *Ty : Types) {

1999

2000 if (attr.hasRetAttr(Attribute::SExt))

2002 else if (attr.hasRetAttr(Attribute::ZExt))

2004

2007

2008 unsigned NumParts =

2010 MVT PartVT =

2012

2013

2015 if (attr.hasRetAttr(Attribute::InReg))

2016 Flags.setInReg();

2017

2018

2019 if (attr.hasRetAttr(Attribute::SExt))

2020 Flags.setSExt();

2021 else if (attr.hasRetAttr(Attribute::ZExt))

2022 Flags.setZExt();

2023

2024 for (unsigned i = 0; i < NumParts; ++i)

2026 }

2027}

2028

2031 return DL.getABITypeAlign(Ty);

2032}

2033

2037

2038

2039

2040

2041

2043 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {

2044

2045 if (Fast != nullptr)

2047 return true;

2048 }

2049

2050

2052}

2053

2060

2063 unsigned AddrSpace, Align Alignment,

2065 unsigned *Fast) const {

2067 Flags, Fast);

2068}

2069

2073 unsigned *Fast) const {

2076}

2077

2081 unsigned *Fast) const {

2085}

2086

2087

2088

2089

2090

2092 enum InstructionOpcodes {

2093#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,

2094#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM

2095#include "llvm/IR/Instruction.def"

2096 };

2097 switch (static_cast<InstructionOpcodes>(Opcode)) {

2098 case Ret: return 0;

2099 case Br: return 0;

2100 case Switch: return 0;

2101 case IndirectBr: return 0;

2102 case Invoke: return 0;

2103 case CallBr: return 0;

2104 case Resume: return 0;

2105 case Unreachable: return 0;

2106 case CleanupRet: return 0;

2107 case CatchRet: return 0;

2108 case CatchPad: return 0;

2109 case CatchSwitch: return 0;

2110 case CleanupPad: return 0;

2111 case FNeg: return ISD::FNEG;

2130 case Alloca: return 0;

2131 case Load: return ISD::LOAD;

2132 case Store: return ISD::STORE;

2133 case GetElementPtr: return 0;

2134 case Fence: return 0;

2135 case AtomicCmpXchg: return 0;

2136 case AtomicRMW: return 0;

2145 case FPExt: return ISD::FP_EXTEND;

2146 case PtrToAddr: return ISD::BITCAST;

2147 case PtrToInt: return ISD::BITCAST;

2148 case IntToPtr: return ISD::BITCAST;

2149 case BitCast: return ISD::BITCAST;

2150 case AddrSpaceCast: return ISD::ADDRSPACECAST;

2153 case PHI: return 0;

2154 case Call: return 0;

2156 case UserOp1: return 0;

2157 case UserOp2: return 0;

2158 case VAArg: return 0;

2164 case LandingPad: return 0;

2166 }

2167

2169}

2170

2172 switch (ID) {

2173 case Intrinsic::exp:

2174 return ISD::FEXP;

2175 case Intrinsic::exp2:

2176 return ISD::FEXP2;

2177 case Intrinsic:🪵

2178 return ISD::FLOG;

2179 default:

2181 }

2182}

2183

2186 bool UseTLS) const {

2187

2188

2190 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";

2191 auto UnsafeStackPtr =

2193

2195 PointerType *StackPtrTy = DL.getAllocaPtrType(M->getContext());

2196

2197 if (!UnsafeStackPtr) {

2201

2202

2203

2206 UnsafeStackPtrVar, nullptr, TLSModel);

2207 } else {

2208

2209

2210

2211 if (UnsafeStackPtr->getValueType() != StackPtrTy)

2213 if (UseTLS != UnsafeStackPtr->isThreadLocal())

2215 (UseTLS ? "" : "not ") + "be thread-local");

2216 }

2217 return UnsafeStackPtr;

2218}

2219

2222

2223

2224 if (!TM.getTargetTriple().isAndroid())

2226

2229

2230 const char *SafestackPointerAddressName =

2232 if (!SafestackPointerAddressName) {

2233 M->getContext().emitError(

2234 "no libcall available for safestack pointer address");

2236 }

2237

2238

2239

2241 M->getOrInsertFunction(SafestackPointerAddressName, PtrTy);

2243}

2244

2245

2246

2247

2248

2249

2250

2254

2255

2256

2257

2259 return false;

2260

2261

2262 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)

2263 return false;

2264

2265

2267 return false;

2268

2269

2270 switch (AM.Scale) {

2271 case 0:

2272 break;

2273 case 1:

2275 return false;

2276

2277 break;

2278 case 2:

2280 return false;

2281

2282 break;

2283 default:

2284 return false;

2285 }

2286

2287 return true;

2288}

2289

2290

2291

2292

2293

2294

2295

2297 RTLIB::LibcallImpl GuardLocalImpl = getLibcallImpl(RTLIB::STACK_CHECK_GUARD);

2298 if (GuardLocalImpl != RTLIB::impl___guard_local)

2299 return nullptr;

2300

2304 PointerType::get(M.getContext(), DL.getDefaultGlobalsAddressSpace());

2308 return G;

2309}

2310

2311

2312

2314 RTLIB::LibcallImpl StackGuardImpl = getLibcallImpl(RTLIB::STACK_CHECK_GUARD);

2315 if (StackGuardImpl == RTLIB::Unsupported)

2316 return;

2317

2319 M.getOrInsertGlobal(

2321 auto *GV = new GlobalVariable(M, PointerType::getUnqual(M.getContext()),

2322 false, GlobalVariable::ExternalLinkage,

2323 nullptr, StackGuardVarName);

2324

2325

2326 if (M.getDirectAccessExternalData() &&

2327 !TM.getTargetTriple().isOSCygMing() &&

2328 !(TM.getTargetTriple().isPPC64() &&

2329 TM.getTargetTriple().isOSFreeBSD()) &&

2330 (!TM.getTargetTriple().isOSDarwin() ||

2331 TM.getRelocationModel() == Reloc::Static))

2332 GV->setDSOLocal(true);

2333

2334 return GV;

2335 });

2336}

2337

2338

2339

2341 RTLIB::LibcallImpl GuardVarImpl = getLibcallImpl(RTLIB::STACK_CHECK_GUARD);

2342 if (GuardVarImpl == RTLIB::Unsupported)

2343 return nullptr;

2345}

2346

2348

2349 RTLIB::LibcallImpl SecurityCheckCookieLibcall =

2351 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)

2352 return M.getFunction(getLibcallImplName(SecurityCheckCookieLibcall));

2353 return nullptr;

2354}

2355

2359

2363

2367

2371

2375

2379

2381 return MinimumBitTestCmps;

2382}

2383

2385 MinimumBitTestCmps = Val;

2386}

2387

2389 if (TM.Options.LoopAlignment)

2390 return Align(TM.Options.LoopAlignment);

2391 return PrefLoopAlignment;

2392}

2393

2396 return MaxBytesForAlignment;

2397}

2398

2399

2400

2401

2402

2403

2404

2407 return F.getFnAttribute("reciprocal-estimates").getValueAsString();

2408}

2409

2410

2411

2412

2413

2415 std::string Name = VT.isVector() ? "vec-" : "";

2416

2417 Name += IsSqrt ? "sqrt" : "div";

2418

2419

2421 Name += "d";

2423 Name += "h";

2424 } else {

2426 "Unexpected FP type for reciprocal estimate");

2427 Name += "f";

2428 }

2429

2430 return Name;

2431}

2432

2433

2434

2435

2438 const char RefStepToken = ':';

2439 Position = In.find(RefStepToken);

2441 return false;

2442

2443 StringRef RefStepString = In.substr(Position + 1);

2444

2445

2446 if (RefStepString.size() == 1) {

2447 char RefStepChar = RefStepString[0];

2448 if (isDigit(RefStepChar)) {

2449 Value = RefStepChar - '0';

2450 return true;

2451 }

2452 }

2454}

2455

2456

2457

2458

2460 if (Override.empty())

2462

2464 Override.split(OverrideVector, ',');

2465 unsigned NumArgs = OverrideVector.size();

2466

2467

2468 if (NumArgs == 1) {

2469

2470

2471 size_t RefPos;

2474

2475 Override = Override.substr(0, RefPos);

2476 }

2477

2478

2479 if (Override == "all")

2481

2482

2483 if (Override == "none")

2485

2486

2487 if (Override == "default")

2489 }

2490

2491

2493 std::string VTNameNoSize = VTName;

2494 VTNameNoSize.pop_back();

2495 static const char DisabledPrefix = '!';

2496

2497 for (StringRef RecipType : OverrideVector) {

2498 size_t RefPos;

2501 RecipType = RecipType.substr(0, RefPos);

2502

2503

2504 bool IsDisabled = RecipType[0] == DisabledPrefix;

2505 if (IsDisabled)

2506 RecipType = RecipType.substr(1);

2507

2508 if (RecipType == VTName || RecipType == VTNameNoSize)

2511 }

2512

2514}

2515

2516

2517

2518

2520 if (Override.empty())

2522

2524 Override.split(OverrideVector, ',');

2525 unsigned NumArgs = OverrideVector.size();

2526

2527

2528 if (NumArgs == 1) {

2529

2530

2531 size_t RefPos;

2535

2536

2537 Override = Override.substr(0, RefPos);

2538 assert(Override != "none" &&

2539 "Disabled reciprocals, but specifed refinement steps?");

2540

2541

2542 if (Override == "all" || Override == "default")

2543 return RefSteps;

2544 }

2545

2546

2548 std::string VTNameNoSize = VTName;

2549 VTNameNoSize.pop_back();

2550

2551 for (StringRef RecipType : OverrideVector) {

2552 size_t RefPos;

2555 continue;

2556

2557 RecipType = RecipType.substr(0, RefPos);

2558 if (RecipType == VTName || RecipType == VTNameNoSize)

2559 return RefSteps;

2560 }

2561

2563}

2564

2569

2574

2579

2584

2588

2589

2592 return false;

2593

2594

2595

2597 return true;

2598

2600

2601

2602

2605 return false;

2606

2607 unsigned Fast = 0;

2609 MMO, &Fast) &&

2611}

2612

2616

2623

2624 if (LI.hasMetadata(LLVMContext::MD_nontemporal))

2626

2627 if (LI.hasMetadata(LLVMContext::MD_invariant_load))

2629

2632 nullptr, LibInfo))

2634

2636 return Flags;

2637}

2638

2643

2644 if (SI.isVolatile())

2646

2647 if (SI.hasMetadata(LLVMContext::MD_nontemporal))

2649

2650

2652 return Flags;

2653}

2654

2659

2661 if (RMW->isVolatile())

2664 if (CmpX->isVolatile())

2666 } else

2668

2669

2671 return Flags;

2672}

2673

2678

2679 switch (IntrinID) {

2680 default:

2681 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "

2682 "for it, but support must be explicitly enabled");

2683 case Intrinsic::vp_load:

2684 case Intrinsic::vp_gather:

2685 case Intrinsic::experimental_vp_strided_load:

2687 break;

2688 case Intrinsic::vp_store:

2689 case Intrinsic::vp_scatter:

2690 case Intrinsic::experimental_vp_strided_store:

2692 break;

2693 }

2694

2695 if (VPIntrin.hasMetadata(LLVMContext::MD_nontemporal))

2697

2699 return Flags;

2700}

2701

2706 return Builder.CreateFence(Ord);

2707 else

2708 return nullptr;

2709}

2710

2715 return Builder.CreateFence(Ord);

2716 else

2717 return nullptr;

2718}

2719

2720

2721

2722

2723

2726 auto &MF = *MI.getMF();

2727 auto &MRI = MF.getRegInfo();

2728

2729

2730

2731

2732

2733

2734 auto maxUses = [](unsigned RematCost) {

2735

2736 if (RematCost == 1)

2737 return std::numeric_limits::max();

2738 if (RematCost == 2)

2739 return 2U;

2740

2741

2742 if (RematCost > 2)

2743 return 1U;

2745 };

2746

2747 switch (MI.getOpcode()) {

2748 default:

2749 return false;

2750

2751

2752 case TargetOpcode::G_CONSTANT:

2753 case TargetOpcode::G_FCONSTANT:

2754 case TargetOpcode::G_FRAME_INDEX:

2755 case TargetOpcode::G_INTTOPTR:

2756 return true;

2757 case TargetOpcode::G_GLOBAL_VALUE: {

2758 unsigned RematCost = TTI->getGISelRematGlobalCost();

2759 Register Reg = MI.getOperand(0).getReg();

2760 unsigned MaxUses = maxUses(RematCost);

2761 if (MaxUses == UINT_MAX)

2762 return true;

2763 return MRI.hasAtMostUserInstrs(Reg, MaxUses);

2764 }

2765 }

2766}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

AMDGPU Register Bank Select

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file contains the simple types necessary to represent the attributes associated with functions a...

This file implements the BitVector class.

This file defines the DenseMap class.

Module.h This file contains the declarations for the Module class.

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

This file defines the SmallVector class.

static cl::opt< unsigned > MinimumBitTestCmpsOverride("min-bit-test-cmps", cl::init(2), cl::Hidden, cl::desc("Set minimum of largest number of comparisons " "to use bit test for switch."))

static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)

#define OP_TO_LIBCALL(Name, Enum)

static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))

static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)

static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)

Return the character position and value (a single numeric character) of a customized refinement opera...

Definition TargetLoweringBase.cpp:2436

static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))

static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))

Minimum jump table density for normal functions.

static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)

Definition TargetLoweringBase.cpp:1413

static std::string getReciprocalOpName(bool IsSqrt, EVT VT)

Construct a string for the given reciprocal operation of the given type.

Definition TargetLoweringBase.cpp:2414

static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return the customized refinement step count for this operation on the...

Definition TargetLoweringBase.cpp:2519

static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...

Definition TargetLoweringBase.cpp:2459

static StringRef getRecipEstimateForFunc(MachineFunction &MF)

Get the reciprocal estimate attribute string for a function that will override the target defaults.

Definition TargetLoweringBase.cpp:2405

static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))

Minimum jump table density for -Os or -Oz functions.

This file describes how to lower LLVM code to machine code.

This pass exposes codegen information to IR-level passes.

Class for arbitrary precision integers.

A cache of @llvm.assume calls within a function.

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

const Function * getParent() const

Return the enclosing method, or null if none.

void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

setBitsInMask - Add '1' bits from Mask to this vector.

iterator_range< const_set_bits_iterator > set_bits() const

BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...

This class represents a range of values.

LLVM_ABI unsigned getActiveBits() const

Compute the maximal number of active bits needed to represent every value in this range.

LLVM_ABI ConstantRange umul_sat(const ConstantRange &Other) const

Perform an unsigned saturating multiplication of two constant ranges.

LLVM_ABI ConstantRange subtract(const APInt &CI) const

Subtract the specified constant from the endpoints of this constant range.

A parsed version of the target data layout string in and methods for querying it.

LLVM_ABI unsigned getPointerSize(unsigned AS=0) const

The pointer representation size in bytes, rounded up to a whole number of bytes.

static constexpr ElementCount getScalable(ScalarTy MinVal)

static constexpr ElementCount getFixed(ScalarTy MinVal)

constexpr bool isScalar() const

Exactly one element.

A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...

Module * getParent()

Get the module that this global value is contained inside of...

@ HiddenVisibility

The GV is hidden.

@ ExternalLinkage

Externally visible function.

Common base class shared among various IRBuilders.

BasicBlock * GetInsertBlock() const

CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args={}, const Twine &Name="", MDNode *FPMathTag=nullptr)

LLVM_ABI bool hasAtomicStore() const LLVM_READONLY

Return true if this atomic instruction stores to memory.

bool hasMetadata() const

Return true if this instruction has any metadata attached to it.

@ MAX_INT_BITS

Maximum number of bits that can be specified.

Intrinsic::ID getIntrinsicID() const

Return the intrinsic ID of this intrinsic.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

Value * getPointerOperand()

bool isVolatile() const

Return true if this is a load from a volatile memory location.

Align getAlign() const

Return the alignment of the access that is being performed.

uint64_t getScalarSizeInBits() const

bool isVector() const

Return true if this is a vector value type.

bool isScalableVector() const

Return true if this is a vector value type where the runtime length is machine dependent.

static auto all_valuetypes()

SimpleValueType Iteration.

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

ElementCount getVectorElementCount() const

bool isScalarInteger() const

Return true if this is an integer, not including vectors.

static MVT getVectorVT(MVT VT, unsigned NumElements)

MVT getVectorElementType() const

bool isValid() const

Return true if this is a valid simple valuetype.

static MVT getIntegerVT(unsigned BitWidth)

static auto fp_valuetypes()

MVT getPow2VectorType() const

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const

Representation of each machine instruction.

unsigned getNumOperands() const

Retuns the total number of operands.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

A description of a memory reference used in the backend.

unsigned getAddrSpace() const

Flags

Flags values. These may be or'd together.

@ MOVolatile

The memory access is volatile.

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

@ MOLoad

The memory access reads data.

@ MONonTemporal

The memory access is non-temporal.

@ MOInvariant

The memory access always returns the same value (or traps).

@ MOStore

The memory access writes data.

Flags getFlags() const

Return the raw flags of the source value,.

LLVM_ABI Align getAlign() const

Return the minimum known alignment in bytes of the actual memory reference.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isFI() const

isFI - Tests if this is a MO_FrameIndex operand.

LLVM_ABI void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

A Module instance is used to store all the information related to an LLVM module.

Class to represent pointers.

static PointerType * getUnqual(Type *ElementType)

This constructs a pointer to an object of the specified type in the default address space (address sp...

static LLVM_ABI PointerType * get(Type *ElementType, unsigned AddressSpace)

This constructs a pointer to an object of the specified type in a numbered address space.

static LLVM_ABI PoisonValue * get(Type *T)

Static factory methods - Return an 'poison' object of the specified type.

Analysis providing profile information.

Wrapper class representing virtual and physical registers.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

const DataLayout & getDataLayout() const

LLVMContext * getContext() const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

static constexpr size_t npos

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

constexpr bool empty() const

empty - Check if the string is empty.

constexpr size_t size() const

size - Get the string size.

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

Provides information about what library functions are available for the current target.

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...

virtual Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const

Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parame...

Definition TargetLoweringBase.cpp:2029

int InstructionOpcodeToISD(unsigned Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition TargetLoweringBase.cpp:2091

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

virtual void finalizeLowering(MachineFunction &MF) const

Execute target specific actions to finalize target lowering.

Definition TargetLoweringBase.cpp:2613

void initActions()

Initialize all of the actions to default values.

Definition TargetLoweringBase.cpp:974

bool PredictableSelectIsExpensive

Tells the code generator that select is more expensive than a branch if the branch is usually predict...

EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

Return the EVT corresponding to this LLVM type.

void setMinimumBitTestCmps(unsigned Val)

Set the minimum of largest of number of comparisons to generate BitTest.

Definition TargetLoweringBase.cpp:2384

unsigned MaxStoresPerMemcpyOptSize

Likewise for functions with the OptSize attribute.

MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...

Definition TargetLoweringBase.cpp:1481

virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const

Returns the target-specific address of the unsafe stack pointer.

Definition TargetLoweringBase.cpp:2221

int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...

Definition TargetLoweringBase.cpp:2565

virtual bool canOpTrap(unsigned Op, EVT VT) const

Returns true if the operation can trap for the value type.

Definition TargetLoweringBase.cpp:1231

virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const

Check whether or not MI needs to be moved close to its uses.

Definition TargetLoweringBase.cpp:2724

virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const

Return the maximum amount of bytes allowed to be emitted when padding for alignment.

Definition TargetLoweringBase.cpp:2394

void setMaximumJumpTableSize(unsigned)

Indicate the maximum number of entries in jump tables.

Definition TargetLoweringBase.cpp:2372

virtual unsigned getMinimumJumpTableEntries() const

Return lower limit for number of blocks in a jump table.

Definition TargetLoweringBase.cpp:2356

const TargetMachine & getTargetMachine() const

unsigned MaxLoadsPerMemcmp

Specify maximum number of load instructions per memcmp call.

virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain targets require unusual breakdowns of certain types.

virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...

unsigned MaxGluedStoresPerMemcpy

Specify max number of store instructions to glue in inlined memcpy.

virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

@ TypeScalarizeScalableVector

virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...

Definition TargetLoweringBase.cpp:1957

void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked load does or does not work with the specified type and ind...

virtual Value * getSDagStackGuard(const Module &M) const

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...

Definition TargetLoweringBase.cpp:2340

unsigned getMinimumBitTestCmps() const

Retuen the minimum of largest number of comparisons in BitTest.

Definition TargetLoweringBase.cpp:2380

virtual bool useFPRegsForHalfType() const

virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...

Definition TargetLoweringBase.cpp:2585

void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed load does or does not work with the specified type and indicate w...

virtual bool softPromoteHalfType() const

unsigned getMaximumJumpTableSize() const

Return upper limit for number of entries in a jump table.

Definition TargetLoweringBase.cpp:2368

virtual MVT::SimpleValueType getCmpLibcallReturnType() const

Return the ValueType for comparison libcalls.

Definition TargetLoweringBase.cpp:1855

unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const

Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...

Definition TargetLoweringBase.cpp:1249

bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const

Return true if the value types that can be represented by the specified register class are all legal.

Definition TargetLoweringBase.cpp:1470

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Let target indicate that an extending atomic load of the specified type is legal.

Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const

Definition TargetLoweringBase.cpp:2185

Function * getSSPStackGuardCheck(const Module &M) const

If the target has a standard stack protection check function that performs validation and error handl...

Definition TargetLoweringBase.cpp:2347

MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const

Definition TargetLoweringBase.cpp:2656

virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const

Determine if the target supports unaligned memory accesses.

unsigned MaxStoresPerMemsetOptSize

Likewise for functions with the OptSize attribute.

EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const

Returns the type for the shift amount of a shift opcode.

Definition TargetLoweringBase.cpp:1216

unsigned MaxStoresPerMemmove

Specify maximum number of store instructions per memmove call.

virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const

Return the preferred loop alignment.

Definition TargetLoweringBase.cpp:2388

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition TargetLoweringBase.cpp:1601

MachineMemOperand::Flags getVPIntrinsicMemOperandFlags(const VPIntrinsic &VPIntrin) const

Definition TargetLoweringBase.cpp:2674

int getDivRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a division of the given type based on the function's attributes.

Definition TargetLoweringBase.cpp:2580

virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const

Return the ValueType of the result of SETCC operations.

Definition TargetLoweringBase.cpp:1849

MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const

Definition TargetLoweringBase.cpp:2617

virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const

For types supported by the target, this is an identity function.

unsigned MaxStoresPerMemmoveOptSize

Likewise for functions with the OptSize attribute.

virtual Value * getIRStackGuard(IRBuilderBase &IRB) const

If the target has a standard location for the stack protector guard, returns the address of that loca...

Definition TargetLoweringBase.cpp:2296

virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const

Returns preferred type for switch condition.

Definition TargetLoweringBase.cpp:1978

bool isTypeLegal(EVT VT) const

Return true if the target has native support for the specified value type.

bool EnableExtLdPromotion

int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...

Definition TargetLoweringBase.cpp:2570

void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed store does or does not work with the specified type and indicate ...

virtual bool isJumpTableRelative() const

Definition TargetLoweringBase.cpp:2376

virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition TargetLoweringBase.cpp:1211

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

Definition TargetLoweringBase.cpp:1244

ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const

Get the comparison predicate that's to be used to test the result of the comparison libcall against z...

Definition TargetLoweringBase.cpp:853

void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked store does or does not work with the specified type and in...

TargetLoweringBase(const TargetMachine &TM, const TargetSubtargetInfo &STI)

NOTE: The TargetMachine owns TLOF.

Definition TargetLoweringBase.cpp:929

unsigned MaxStoresPerMemset

Specify maximum number of store instructions per memset call.

void setMinimumJumpTableEntries(unsigned Val)

Indicate the minimum number of blocks to generate jump tables.

Definition TargetLoweringBase.cpp:2360

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

@ UndefinedBooleanContent

virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

Return true if the target supports a memory access of this type for the given address space and align...

Definition TargetLoweringBase.cpp:2061

unsigned MaxLoadsPerMemcmpOptSize

Likewise for functions with the OptSize attribute.

MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const

Definition TargetLoweringBase.cpp:2640

virtual ~TargetLoweringBase()

void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...

unsigned getMinimumJumpTableDensity(bool OptForSize) const

Return lower limit of the density in a jump table.

Definition TargetLoweringBase.cpp:2364

virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const

Return the largest legal super-reg register class of the register class for the specified type and it...

Definition TargetLoweringBase.cpp:1574

RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const

Get the libcall impl routine name for the specified libcall.

static StringRef getLibcallImplName(RTLIB::LibcallImpl Call)

Get the libcall routine name for the specified libcall implementation.

LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const

Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...

Definition TargetLoweringBase.cpp:1274

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

unsigned GatherAllAliasesMaxDepth

Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...

int IntrinsicIDToISD(Intrinsic::ID ID) const

Get the ISD node that corresponds to the Intrinsic ID.

Definition TargetLoweringBase.cpp:2171

LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...

int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a square root of the given type based on the function's attribut...

Definition TargetLoweringBase.cpp:2575

const char * getLibcallName(RTLIB::Libcall Call) const

Get the libcall routine name for the specified libcall.

bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

This function returns true if the memory access is aligned or if the target allows this specific unal...

Definition TargetLoweringBase.cpp:2034

virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Definition TargetLoweringBase.cpp:2711

virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Inserts in the IR a target-specific intrinsic specifying a fence.

Definition TargetLoweringBase.cpp:2702

unsigned MaxStoresPerMemcpy

Specify maximum number of store instructions per memcpy call.

MVT getRegisterType(MVT VT) const

Return the type of registers that this ValueType will eventually require.

virtual void insertSSPDeclarations(Module &M) const

Inserts necessary declarations for SSP (stack protection) purpose.

Definition TargetLoweringBase.cpp:2313

void setJumpIsExpensive(bool isExpensive=true)

Tells the code generator not to expand logic operations on comparison predicates into separate sequen...

Definition TargetLoweringBase.cpp:1267

LegalizeAction getOperationAction(unsigned Op, EVT VT) const

Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...

MVT getTypeToPromoteTo(unsigned Op, MVT VT) const

If the action for this operation is to promote, this method returns the ValueType to promote to.

virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

Definition TargetLoweringBase.cpp:2251

unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

Vector types are broken down into some number of legal first class types.

Definition TargetLoweringBase.cpp:1867

std::pair< LegalizeTypeAction, EVT > LegalizeKind

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

Primary interface to the complete machine description for the target machine.

bool isPositionIndependent() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM_ABI unsigned getScalarSizeInBits() const LLVM_READONLY

If this is a vector type, return the getPrimitiveSizeInBits value for the element type.

This is the common base class for vector predication intrinsics.

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

constexpr LeafTy coefficientNextPowerOf2() const

constexpr bool isScalable() const

Returns whether the quantity is scaled by a runtime quantity (vscale).

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const

We do not provide the '/' operator here because division for polynomial types does not work in the sa...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ MERGE_VALUES

MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...

@ DELETED_NODE

DELETED_NODE - This is an illegal value that is used to catch errors.

@ LOOP_DEPENDENCE_RAW_MASK

@ FGETSIGN

INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...

@ SMULFIX

RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...

@ ADDC

Carry-setting nodes for multiple precision addition and subtraction.

@ FMAD

FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.

@ ADD

Simple integer binary arithmetic operators.

@ SMULFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ CONCAT_VECTORS

CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...

@ FADD

Simple binary floating point operators.

@ ABS

ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.

@ SIGN_EXTEND_VECTOR_INREG

SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...

@ FMULADD

FMULADD - Performs a * b + c, with, or without, intermediate rounding.

@ SDIVFIX

RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

@ SIGN_EXTEND

Conversion operators.

@ AVGCEILS

AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...

@ CTTZ_ZERO_UNDEF

Bit counting operators with an undefined result for zero inputs.

@ SETCCCARRY

Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...

@ SSUBO

Same for subtraction.

@ FCANONICALIZE

Returns platform specific canonical encoding of a floating point number.

@ IS_FPCLASS

Performs a check of floating point class property, defined by IEEE-754.

@ SSUBSAT

RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ SPLAT_VECTOR

SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.

@ SADDO

RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.

@ SHL

Shift and rotation operations.

@ VECTOR_SHUFFLE

VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SSHLSAT

RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.

@ SMULO

Same for multiplication.

@ ANY_EXTEND_VECTOR_INREG

ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ SDIVFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ UADDO_CARRY

Carry-using nodes for multiple precision addition and subtraction.

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ SCMP

[US]CMP - 3-way comparison of signed or unsigned integers.

@ AVGFLOORS

AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...

@ ADDE

Carry-using nodes for multiple precision addition and subtraction.

@ FREEZE

FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

@ VECTOR_SPLICE

VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...

@ FP_ROUND

X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...

@ VECTOR_COMPRESS

VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....

@ ZERO_EXTEND_VECTOR_INREG

ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...

@ FP_TO_SINT_SAT

FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

@ SADDSAT

RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...

@ TRUNCATE_SSAT_S

TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand [SU] located in middle, prefix for SAT means i...

@ ABDS

ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...

@ SADDO_CARRY

Carry-using overflow-aware nodes for multiple precision addition and subtraction.

@ LOOP_DEPENDENCE_WAR_MASK

Set rounding mode.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

static const int LAST_INDEXED_MODE

LLVM_ABI Libcall getPOWI(EVT RetVT)

getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:518

LLVM_ABI Libcall getSINTTOFP(EVT OpVT, EVT RetVT)

getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:424

LLVM_ABI Libcall getUREM(EVT VT)

Definition TargetLoweringBase.cpp:203

LLVM_ABI Libcall getSHL(EVT VT)

Definition TargetLoweringBase.cpp:106

LLVM_ABI Libcall getSYNC(unsigned Opc, MVT VT)

Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:764

LLVM_ABI Libcall getLDEXP(EVT RetVT)

getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:527

LLVM_ABI Libcall getUINTTOFP(EVT OpVT, EVT RetVT)

getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:472

LLVM_ABI Libcall getFREXP(EVT RetVT)

getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:532

LLVM_ABI Libcall getSINCOSPI(EVT RetVT)

getSINCOSPI - Return the SINCOSPI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:568

LLVM_ABI Libcall getSDIV(EVT VT)

Definition TargetLoweringBase.cpp:167

LLVM_ABI Libcall getSRL(EVT VT)

Definition TargetLoweringBase.cpp:119

LLVM_ABI Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Definition TargetLoweringBase.cpp:802

LLVM_ABI Libcall getSRA(EVT VT)

Definition TargetLoweringBase.cpp:132

LLVM_ABI Libcall getUDIV(EVT VT)

Definition TargetLoweringBase.cpp:179

LLVM_ABI Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)

GetFPLibCall - Helper to return the right libcall for the given floating point type,...

LLVM_ABI Libcall getFPTOUINT(EVT OpVT, EVT RetVT)

getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:375

LLVM_ABI Libcall getLLROUND(EVT VT)

Definition TargetLoweringBase.cpp:634

LLVM_ABI Libcall getCOS(EVT RetVT)

Return the COS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:541

LLVM_ABI Libcall getLROUND(EVT VT)

Definition TargetLoweringBase.cpp:619

LLVM_ABI Libcall getMODF(EVT VT)

getMODF - Return the MODF_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:596

LLVM_ABI Libcall getFPTOSINT(EVT OpVT, EVT RetVT)

getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:326

LLVM_ABI Libcall getLRINT(EVT RetVT)

Definition TargetLoweringBase.cpp:649

LLVM_ABI Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)

Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...

Definition TargetLoweringBase.cpp:722

LLVM_ABI Libcall getLLRINT(EVT RetVT)

Definition TargetLoweringBase.cpp:663

LLVM_ABI Libcall getFPEXT(EVT OpVT, EVT RetVT)

getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:244

LLVM_ABI Libcall getFPROUND(EVT OpVT, EVT RetVT)

getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:279

LLVM_ABI Libcall getSREM(EVT VT)

Definition TargetLoweringBase.cpp:191

LLVM_ABI Libcall getSIN(EVT RetVT)

Return the SIN_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:537

LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Definition TargetLoweringBase.cpp:836

LLVM_ABI Libcall getSINCOS_STRET(EVT RetVT)

Return the SINCOS_STRET_ value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:591

LLVM_ABI Libcall getPOW(EVT RetVT)

getPOW - Return the POW_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:523

LLVM_ABI Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)

Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...

Definition TargetLoweringBase.cpp:677

LLVM_ABI Libcall getMUL(EVT VT)

Definition TargetLoweringBase.cpp:145

LLVM_ABI Libcall getCTPOP(EVT VT)

Definition TargetLoweringBase.cpp:215

LLVM_ABI Libcall getSINCOS(EVT RetVT)

getSINCOS - Return the SINCOS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:545

LLVM_ABI Libcall getMULO(EVT VT)

Definition TargetLoweringBase.cpp:157

LLVM_ABI Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...

Definition TargetLoweringBase.cpp:819

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

unsigned Log2_32_Ceil(uint32_t Value)

Return the ceil log base 2 of the specified value, 32 if the value is zero.

void fill(R &&Range, T &&Value)

Provide wrappers to std::fill which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)

Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...

Definition TargetLoweringBase.cpp:1987

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

auto enum_seq(EnumT Begin, EnumT End)

Iterate over an enum type from Begin up to - but not including - End.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)

Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.

LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum

T bit_ceil(T Value)

Returns the smallest integral power of two no smaller than Value if Value is nonzero.

void ComputeValueTypes(const DataLayout &DL, Type *Ty, SmallVectorImpl< Type * > &Types, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())

Given an LLVM IR type, compute non-aggregate subtypes.

bool isReleaseOrStronger(AtomicOrdering AO)

auto dyn_cast_or_null(const Y &Val)

constexpr bool has_single_bit(T Value) noexcept

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

bool isDigit(char C)

Checks if character C is one of the 10 decimal digits.

AtomicOrdering

Atomic ordering for LLVM's memory model.

LLVM_ABI EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)

constexpr T divideCeil(U Numerator, V Denominator)

Returns the integer ceil(Numerator / Denominator).

@ Mul

Product of integers.

@ Xor

Bitwise or logical XOR of integers.

@ Sub

Subtraction of integers.

DWARFExpression::Operation Op

bool isAcquireOrStronger(AtomicOrdering AO)

This struct is a compact representation of a valid (non-zero power of two) alignment.

EVT getPow2VectorType(LLVMContext &Context) const

Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

ElementCount getVectorElementCount() const

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

bool isPow2VectorType() const

Returns true if the given vector is a power of 2.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)

Returns the EVT that represents an integer with the given number of bits.

bool isFixedLengthVector() const

EVT getRoundIntegerType(LLVMContext &Context) const

Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...

bool isVector() const

Return true if this is a vector value type.

EVT getScalarType() const

If this is a vector type, return the element type, otherwise return this.

LLVM_ABI Type * getTypeForEVT(LLVMContext &Context) const

This method returns an LLVM type corresponding to the specified EVT.

EVT getVectorElementType() const

Given a vector type, return the type of each element.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

bool isZeroSized() const

Test if the given EVT has zero size, this will fail if called on a scalable type.

EVT getHalfNumVectorElementsVT(LLVMContext &Context) const

bool isInteger() const

Return true if this is an integer or a vector integer type.

OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl)

Return the libcall provided by Impl.

This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...