TargetLoweringBase.cpp Source File (original) (raw)

57#include

58#include

59#include

60#include

61#include

62#include

63#include

64#include

66using namespace llvm;

69 "jump-is-expensive", cl::init(false),

70 cl::desc("Do not create extra branches to split comparison logic."),

75 cl::desc("Set minimum number of entries to use a jump table."));

79 cl::desc("Set maximum size of jump tables."));

84 cl::desc("Minimum density for building a jump table in "

85 "a normal function"));

90 cl::desc("Minimum density for building a jump table in "

91 "an optsize function"));

98 cl::desc("Don't mutate strict-float node to a legalize node"),

100

101

102

109 return

110 VT == MVT::f32 ? Call_F32 :

111 VT == MVT::f64 ? Call_F64 :

112 VT == MVT::f80 ? Call_F80 :

113 VT == MVT::f128 ? Call_F128 :

114 VT == MVT::ppcf128 ? Call_PPCF128 :

115 RTLIB::UNKNOWN_LIBCALL;

116}

117

118

119

121 if (OpVT == MVT::f16) {

122 if (RetVT == MVT::f32)

123 return FPEXT_F16_F32;

124 if (RetVT == MVT::f64)

125 return FPEXT_F16_F64;

126 if (RetVT == MVT::f80)

127 return FPEXT_F16_F80;

128 if (RetVT == MVT::f128)

129 return FPEXT_F16_F128;

130 } else if (OpVT == MVT::f32) {

131 if (RetVT == MVT::f64)

132 return FPEXT_F32_F64;

133 if (RetVT == MVT::f128)

134 return FPEXT_F32_F128;

135 if (RetVT == MVT::ppcf128)

136 return FPEXT_F32_PPCF128;

137 } else if (OpVT == MVT::f64) {

138 if (RetVT == MVT::f128)

139 return FPEXT_F64_F128;

140 else if (RetVT == MVT::ppcf128)

141 return FPEXT_F64_PPCF128;

142 } else if (OpVT == MVT::f80) {

143 if (RetVT == MVT::f128)

144 return FPEXT_F80_F128;

145 } else if (OpVT == MVT::bf16) {

146 if (RetVT == MVT::f32)

147 return FPEXT_BF16_F32;

148 }

149

150 return UNKNOWN_LIBCALL;

151}

152

153

154

156 if (RetVT == MVT::f16) {

157 if (OpVT == MVT::f32)

158 return FPROUND_F32_F16;

159 if (OpVT == MVT::f64)

160 return FPROUND_F64_F16;

161 if (OpVT == MVT::f80)

162 return FPROUND_F80_F16;

163 if (OpVT == MVT::f128)

164 return FPROUND_F128_F16;

165 if (OpVT == MVT::ppcf128)

166 return FPROUND_PPCF128_F16;

167 } else if (RetVT == MVT::bf16) {

168 if (OpVT == MVT::f32)

169 return FPROUND_F32_BF16;

170 if (OpVT == MVT::f64)

171 return FPROUND_F64_BF16;

172 if (OpVT == MVT::f80)

173 return FPROUND_F80_BF16;

174 if (OpVT == MVT::f128)

175 return FPROUND_F128_BF16;

176 } else if (RetVT == MVT::f32) {

177 if (OpVT == MVT::f64)

178 return FPROUND_F64_F32;

179 if (OpVT == MVT::f80)

180 return FPROUND_F80_F32;

181 if (OpVT == MVT::f128)

182 return FPROUND_F128_F32;

183 if (OpVT == MVT::ppcf128)

184 return FPROUND_PPCF128_F32;

185 } else if (RetVT == MVT::f64) {

186 if (OpVT == MVT::f80)

187 return FPROUND_F80_F64;

188 if (OpVT == MVT::f128)

189 return FPROUND_F128_F64;

190 if (OpVT == MVT::ppcf128)

191 return FPROUND_PPCF128_F64;

192 } else if (RetVT == MVT::f80) {

193 if (OpVT == MVT::f128)

194 return FPROUND_F128_F80;

195 }

196

197 return UNKNOWN_LIBCALL;

198}

199

200

201

203 if (OpVT == MVT::f16) {

204 if (RetVT == MVT::i32)

205 return FPTOSINT_F16_I32;

206 if (RetVT == MVT::i64)

207 return FPTOSINT_F16_I64;

208 if (RetVT == MVT::i128)

209 return FPTOSINT_F16_I128;

210 } else if (OpVT == MVT::f32) {

211 if (RetVT == MVT::i32)

212 return FPTOSINT_F32_I32;

213 if (RetVT == MVT::i64)

214 return FPTOSINT_F32_I64;

215 if (RetVT == MVT::i128)

216 return FPTOSINT_F32_I128;

217 } else if (OpVT == MVT::f64) {

218 if (RetVT == MVT::i32)

219 return FPTOSINT_F64_I32;

220 if (RetVT == MVT::i64)

221 return FPTOSINT_F64_I64;

222 if (RetVT == MVT::i128)

223 return FPTOSINT_F64_I128;

224 } else if (OpVT == MVT::f80) {

225 if (RetVT == MVT::i32)

226 return FPTOSINT_F80_I32;

227 if (RetVT == MVT::i64)

228 return FPTOSINT_F80_I64;

229 if (RetVT == MVT::i128)

230 return FPTOSINT_F80_I128;

231 } else if (OpVT == MVT::f128) {

232 if (RetVT == MVT::i32)

233 return FPTOSINT_F128_I32;

234 if (RetVT == MVT::i64)

235 return FPTOSINT_F128_I64;

236 if (RetVT == MVT::i128)

237 return FPTOSINT_F128_I128;

238 } else if (OpVT == MVT::ppcf128) {

239 if (RetVT == MVT::i32)

240 return FPTOSINT_PPCF128_I32;

241 if (RetVT == MVT::i64)

242 return FPTOSINT_PPCF128_I64;

243 if (RetVT == MVT::i128)

244 return FPTOSINT_PPCF128_I128;

245 }

246 return UNKNOWN_LIBCALL;

247}

248

249

250

252 if (OpVT == MVT::f16) {

253 if (RetVT == MVT::i32)

254 return FPTOUINT_F16_I32;

255 if (RetVT == MVT::i64)

256 return FPTOUINT_F16_I64;

257 if (RetVT == MVT::i128)

258 return FPTOUINT_F16_I128;

259 } else if (OpVT == MVT::f32) {

260 if (RetVT == MVT::i32)

261 return FPTOUINT_F32_I32;

262 if (RetVT == MVT::i64)

263 return FPTOUINT_F32_I64;

264 if (RetVT == MVT::i128)

265 return FPTOUINT_F32_I128;

266 } else if (OpVT == MVT::f64) {

267 if (RetVT == MVT::i32)

268 return FPTOUINT_F64_I32;

269 if (RetVT == MVT::i64)

270 return FPTOUINT_F64_I64;

271 if (RetVT == MVT::i128)

272 return FPTOUINT_F64_I128;

273 } else if (OpVT == MVT::f80) {

274 if (RetVT == MVT::i32)

275 return FPTOUINT_F80_I32;

276 if (RetVT == MVT::i64)

277 return FPTOUINT_F80_I64;

278 if (RetVT == MVT::i128)

279 return FPTOUINT_F80_I128;

280 } else if (OpVT == MVT::f128) {

281 if (RetVT == MVT::i32)

282 return FPTOUINT_F128_I32;

283 if (RetVT == MVT::i64)

284 return FPTOUINT_F128_I64;

285 if (RetVT == MVT::i128)

286 return FPTOUINT_F128_I128;

287 } else if (OpVT == MVT::ppcf128) {

288 if (RetVT == MVT::i32)

289 return FPTOUINT_PPCF128_I32;

290 if (RetVT == MVT::i64)

291 return FPTOUINT_PPCF128_I64;

292 if (RetVT == MVT::i128)

293 return FPTOUINT_PPCF128_I128;

294 }

295 return UNKNOWN_LIBCALL;

296}

297

298

299

301 if (OpVT == MVT::i32) {

302 if (RetVT == MVT::f16)

303 return SINTTOFP_I32_F16;

304 if (RetVT == MVT::f32)

305 return SINTTOFP_I32_F32;

306 if (RetVT == MVT::f64)

307 return SINTTOFP_I32_F64;

308 if (RetVT == MVT::f80)

309 return SINTTOFP_I32_F80;

310 if (RetVT == MVT::f128)

311 return SINTTOFP_I32_F128;

312 if (RetVT == MVT::ppcf128)

313 return SINTTOFP_I32_PPCF128;

314 } else if (OpVT == MVT::i64) {

315 if (RetVT == MVT::f16)

316 return SINTTOFP_I64_F16;

317 if (RetVT == MVT::f32)

318 return SINTTOFP_I64_F32;

319 if (RetVT == MVT::f64)

320 return SINTTOFP_I64_F64;

321 if (RetVT == MVT::f80)

322 return SINTTOFP_I64_F80;

323 if (RetVT == MVT::f128)

324 return SINTTOFP_I64_F128;

325 if (RetVT == MVT::ppcf128)

326 return SINTTOFP_I64_PPCF128;

327 } else if (OpVT == MVT::i128) {

328 if (RetVT == MVT::f16)

329 return SINTTOFP_I128_F16;

330 if (RetVT == MVT::f32)

331 return SINTTOFP_I128_F32;

332 if (RetVT == MVT::f64)

333 return SINTTOFP_I128_F64;

334 if (RetVT == MVT::f80)

335 return SINTTOFP_I128_F80;

336 if (RetVT == MVT::f128)

337 return SINTTOFP_I128_F128;

338 if (RetVT == MVT::ppcf128)

339 return SINTTOFP_I128_PPCF128;

340 }

341 return UNKNOWN_LIBCALL;

342}

343

344

345

347 if (OpVT == MVT::i32) {

348 if (RetVT == MVT::f16)

349 return UINTTOFP_I32_F16;

350 if (RetVT == MVT::f32)

351 return UINTTOFP_I32_F32;

352 if (RetVT == MVT::f64)

353 return UINTTOFP_I32_F64;

354 if (RetVT == MVT::f80)

355 return UINTTOFP_I32_F80;

356 if (RetVT == MVT::f128)

357 return UINTTOFP_I32_F128;

358 if (RetVT == MVT::ppcf128)

359 return UINTTOFP_I32_PPCF128;

360 } else if (OpVT == MVT::i64) {

361 if (RetVT == MVT::f16)

362 return UINTTOFP_I64_F16;

363 if (RetVT == MVT::f32)

364 return UINTTOFP_I64_F32;

365 if (RetVT == MVT::f64)

366 return UINTTOFP_I64_F64;

367 if (RetVT == MVT::f80)

368 return UINTTOFP_I64_F80;

369 if (RetVT == MVT::f128)

370 return UINTTOFP_I64_F128;

371 if (RetVT == MVT::ppcf128)

372 return UINTTOFP_I64_PPCF128;

373 } else if (OpVT == MVT::i128) {

374 if (RetVT == MVT::f16)

375 return UINTTOFP_I128_F16;

376 if (RetVT == MVT::f32)

377 return UINTTOFP_I128_F32;

378 if (RetVT == MVT::f64)

379 return UINTTOFP_I128_F64;

380 if (RetVT == MVT::f80)

381 return UINTTOFP_I128_F80;

382 if (RetVT == MVT::f128)

383 return UINTTOFP_I128_F128;

384 if (RetVT == MVT::ppcf128)

385 return UINTTOFP_I128_PPCF128;

386 }

387 return UNKNOWN_LIBCALL;

388}

389

391 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,

392 POWI_PPCF128);

393}

394

396 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,

397 LDEXP_PPCF128);

398}

399

401 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,

402 FREXP_PPCF128);

403}

404

406 return getFPLibCall(RetVT, SINCOS_F32, SINCOS_F64, SINCOS_F80, SINCOS_F128,

407 SINCOS_PPCF128);

408}

409

413 unsigned ModeN, ModelN;

414 switch (MemSize) {

415 case 1:

416 ModeN = 0;

417 break;

418 case 2:

419 ModeN = 1;

420 break;

421 case 4:

422 ModeN = 2;

423 break;

424 case 8:

425 ModeN = 3;

426 break;

427 case 16:

428 ModeN = 4;

429 break;

430 default:

431 return RTLIB::UNKNOWN_LIBCALL;

432 }

433

434 switch (Order) {

435 case AtomicOrdering::Monotonic:

436 ModelN = 0;

437 break;

438 case AtomicOrdering::Acquire:

439 ModelN = 1;

440 break;

441 case AtomicOrdering::Release:

442 ModelN = 2;

443 break;

444 case AtomicOrdering::AcquireRelease:

445 case AtomicOrdering::SequentiallyConsistent:

446 ModelN = 3;

447 break;

448 default:

449 return UNKNOWN_LIBCALL;

450 }

451

452 return LC[ModeN][ModelN];

453}

454

456 MVT VT) {

458 return UNKNOWN_LIBCALL;

460

461#define LCALLS(A, B) \

462 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }

463#define LCALL5(A) \

464 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)

465 switch (Opc) {

467 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};

469 }

471 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};

473 }

475 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};

477 }

479 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};

481 }

483 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};

485 }

487 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};

489 }

490 default:

491 return UNKNOWN_LIBCALL;

492 }

493#undef LCALLS

494#undef LCALL5

495}

496

498#define OP_TO_LIBCALL(Name, Enum) \

499 case Name: \

500 switch (VT.SimpleTy) { \

501 default: \

502 return UNKNOWN_LIBCALL; \

503 case MVT::i8: \

504 return Enum##_1; \

505 case MVT::i16: \

506 return Enum##_2; \

507 case MVT::i32: \

508 return Enum##_4; \

509 case MVT::i64: \

510 return Enum##_8; \

511 case MVT::i128: \

512 return Enum##_16; \

513 }

514

515 switch (Opc) {

528 }

529

530#undef OP_TO_LIBCALL

531

532 return UNKNOWN_LIBCALL;

533}

534

536 switch (ElementSize) {

537 case 1:

538 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;

539 case 2:

540 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;

541 case 4:

542 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;

543 case 8:

544 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;

545 case 16:

546 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;

547 default:

548 return UNKNOWN_LIBCALL;

549 }

550}

551

553 switch (ElementSize) {

554 case 1:

555 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;

556 case 2:

557 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;

558 case 4:

559 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;

560 case 8:

561 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;

562 case 16:

563 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;

564 default:

565 return UNKNOWN_LIBCALL;

566 }

567}

568

570 switch (ElementSize) {

571 case 1:

572 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;

573 case 2:

574 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;

575 case 4:

576 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;

577 case 8:

578 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;

579 case 16:

580 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;

581 default:

582 return UNKNOWN_LIBCALL;

583 }

584}

585

587 std::fill(CmpLibcallCCs, CmpLibcallCCs + RTLIB::UNKNOWN_LIBCALL,

589 CmpLibcallCCs[RTLIB::OEQ_F32] = ISD::SETEQ;

590 CmpLibcallCCs[RTLIB::OEQ_F64] = ISD::SETEQ;

591 CmpLibcallCCs[RTLIB::OEQ_F128] = ISD::SETEQ;

592 CmpLibcallCCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;

593 CmpLibcallCCs[RTLIB::UNE_F32] = ISD::SETNE;

594 CmpLibcallCCs[RTLIB::UNE_F64] = ISD::SETNE;

595 CmpLibcallCCs[RTLIB::UNE_F128] = ISD::SETNE;

596 CmpLibcallCCs[RTLIB::UNE_PPCF128] = ISD::SETNE;

597 CmpLibcallCCs[RTLIB::OGE_F32] = ISD::SETGE;

598 CmpLibcallCCs[RTLIB::OGE_F64] = ISD::SETGE;

599 CmpLibcallCCs[RTLIB::OGE_F128] = ISD::SETGE;

600 CmpLibcallCCs[RTLIB::OGE_PPCF128] = ISD::SETGE;

601 CmpLibcallCCs[RTLIB::OLT_F32] = ISD::SETLT;

602 CmpLibcallCCs[RTLIB::OLT_F64] = ISD::SETLT;

603 CmpLibcallCCs[RTLIB::OLT_F128] = ISD::SETLT;

604 CmpLibcallCCs[RTLIB::OLT_PPCF128] = ISD::SETLT;

605 CmpLibcallCCs[RTLIB::OLE_F32] = ISD::SETLE;

606 CmpLibcallCCs[RTLIB::OLE_F64] = ISD::SETLE;

607 CmpLibcallCCs[RTLIB::OLE_F128] = ISD::SETLE;

608 CmpLibcallCCs[RTLIB::OLE_PPCF128] = ISD::SETLE;

609 CmpLibcallCCs[RTLIB::OGT_F32] = ISD::SETGT;

610 CmpLibcallCCs[RTLIB::OGT_F64] = ISD::SETGT;

611 CmpLibcallCCs[RTLIB::OGT_F128] = ISD::SETGT;

612 CmpLibcallCCs[RTLIB::OGT_PPCF128] = ISD::SETGT;

613 CmpLibcallCCs[RTLIB::UO_F32] = ISD::SETNE;

614 CmpLibcallCCs[RTLIB::UO_F64] = ISD::SETNE;

615 CmpLibcallCCs[RTLIB::UO_F128] = ISD::SETNE;

616 CmpLibcallCCs[RTLIB::UO_PPCF128] = ISD::SETNE;

617}

618

619

621 : TM(tm), Libcalls(TM.getTargetTriple()) {

623

624

630 HasMultipleConditionRegisters = false;

631 HasExtractBitsInsn = false;

635 StackPointerRegisterToSaveRestore = 0;

642 MaxBytesForAlignment = 0;

643 MaxAtomicSizeInBitsSupported = 0;

644

645

646

647 MaxDivRemBitWidthSupported = 128;

648

650

651 MinCmpXchgSizeInBits = 0;

652 SupportsUnalignedAtomics = false;

653

655}

656

658

659 memset(OpActions, 0, sizeof(OpActions));

660 memset(LoadExtActions, 0, sizeof(LoadExtActions));

661 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));

662 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));

663 memset(CondCodeActions, 0, sizeof(CondCodeActions));

664 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);

665 std::fill(std::begin(TargetDAGCombineArray),

666 std::end(TargetDAGCombineArray), 0);

667

668

673

674

675

678 for (MVT VT : {MVT::i2, MVT::i4})

679 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;

680 }

682 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {

686 }

687 }

690 for (MVT VT : {MVT::i2, MVT::i4}) {

695 }

696 }

697

703 }

704 }

705

706

708

715 }

716

717

719

720

740

741

745

746

750

751

754

755

757

758

762

763

765

766

770

771

774

776

777

781

782

783 if (VT.isVector())

791

792

793#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \

794 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);

795#include "llvm/IR/ConstrainedOps.def"

796

797

799

800

809

810

812

813

815

816

817#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \

818 setOperationAction(ISD::SDOPC, VT, Expand);

819#include "llvm/IR/VPIntrinsics.def"

820

821

823

824

828 }

829

830

832

833

835

836

838

839

840

841

843 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},

845

846

853 {MVT::f32, MVT::f64, MVT::f128}, Expand);

854

855

857 {MVT::f32, MVT::f64, MVT::f128}, LibCall);

858

862

864

865

866

868

870

873

874 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {

877 }

879

880

881

883}

884

886 EVT) const {

888}

889

892 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");

894 return LHSTy;

896

897

899 ShiftVT = MVT::i32;

901 "ShiftVT is still too small!");

902 return ShiftVT;

903}

904

907 switch (Op) {

908 default:

909 return false;

914 return true;

915 }

916}

917

919 unsigned DestAS) const {

921}

922

926

928 if (EC.isScalable())

929 CR = CR.umul_sat(*VScaleRange);

930

931 if (ZeroIsPoison)

933

934 unsigned EltWidth = RetTy->getScalarSizeInBits();

935 EltWidth = std::min(EltWidth, (unsigned)CR.getActiveBits());

936 EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8);

937

938 return EltWidth;

939}

940

942

944 JumpIsExpensive = isExpensive;

945}

946

949

952 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));

955

960 "Promote may not follow Expand or Promote");

961

963 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));

967 }

968

969

973

976 assert(NVT != VT && "Unable to round integer VT");

978

980 return NextStep;

981

983 }

984

987 }

988

989

992

993

996

997

998

999

1001

1002

1007 }

1008

1009

1011

1012

1013

1019 }

1020

1021

1022

1023

1024

1025 EVT OldEltVT = EltVT;

1026 while (true) {

1027

1028

1031

1032

1033

1034

1035

1037 break;

1038

1039

1041

1045 }

1046

1047

1048

1049 EltVT = OldEltVT;

1050 }

1051

1052

1053

1054 while (true) {

1055

1057

1058

1059

1060

1062 break;

1064 if (LargerVector == MVT())

1065 break;

1066

1067

1070 }

1071

1072

1076 }

1077

1080

1081

1085}

1086

1088 unsigned &NumIntermediates,

1089 MVT &RegisterVT,

1091

1094

1095 unsigned NumVectorRegs = 1;

1096

1097

1098

1101 "Splitting or widening of non-power-of-2 MVTs is not implemented.");

1102

1103

1104

1106

1107 NumVectorRegs = EC.getKnownMinValue();

1109 }

1110

1111

1112

1113

1114 while (EC.getKnownMinValue() > 1 &&

1116 EC = EC.divideCoefficientBy(2);

1117 NumVectorRegs <<= 1;

1118 }

1119

1120 NumIntermediates = NumVectorRegs;

1121

1124 NewVT = EltTy;

1125 IntermediateVT = NewVT;

1126

1128

1129

1131

1133 RegisterVT = DestVT;

1134 if (EVT(DestVT).bitsLT(NewVT))

1136

1137

1138

1139 return NumVectorRegs;

1140}

1141

1142

1143

1146 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)

1148 return true;

1149 return false;

1150}

1151

1152

1153

1160

1161

1162

1163

1164

1165

1166

1167

1168

1169

1170

1171

1172

1174 [](MachineOperand &Operand) { return Operand.isFI(); }))

1175 return MBB;

1176

1178

1179

1181

1182 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {

1184 if (!MO.isFI()) {

1185

1186

1187

1188

1189 unsigned TiedTo = i;

1191 TiedTo = MI->findTiedOperandIdx(i);

1192 MIB.add(MO);

1193 if (TiedTo < i)

1195 continue;

1196 }

1197

1198

1199

1201

1202

1204

1205

1206

1207

1208 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");

1209 MIB.addImm(StackMaps::IndirectMemRefOp);

1211 MIB.add(MO);

1213 } else {

1214

1215

1216 MIB.addImm(StackMaps::DirectMemRefOp);

1217 MIB.add(MO);

1219 }

1220

1221 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");

1222

1223

1225

1226

1227

1228 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {

1234 }

1235 }

1237 MI->eraseFromParent();

1238 return MBB;

1239}

1240

1241

1242

1243

1244

1245

1246

1247std::pair<const TargetRegisterClass *, uint8_t>

1249 MVT VT) const {

1251 if (!RC)

1252 return std::make_pair(RC, 0);

1253

1254

1255 BitVector SuperRegRC(TRI->getNumRegClasses());

1258

1259

1261 for (unsigned i : SuperRegRC.set_bits()) {

1263

1264 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))

1265 continue;

1267 continue;

1268 BestRC = SuperRC;

1269 }

1270 return std::make_pair(BestRC, 1);

1271}

1272

1273

1274

1277

1279 NumRegistersForVT[i] = 1;

1281 }

1282

1283 NumRegistersForVT[MVT::isVoid] = 0;

1284

1285

1286 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;

1287 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)

1288 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");

1289

1290

1291

1292 for (unsigned ExpandedReg = LargestIntReg + 1;

1293 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {

1294 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];

1299 }

1300

1301

1302

1303 unsigned LegalIntReg = LargestIntReg;

1304 for (unsigned IntReg = LargestIntReg - 1;

1305 IntReg >= (unsigned)MVT::i1; --IntReg) {

1308 LegalIntReg = IntReg;

1309 } else {

1310 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =

1313 }

1314 }

1315

1316

1319 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];

1320 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;

1321 TransformToType[MVT::ppcf128] = MVT::f64;

1323 } else {

1324 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];

1325 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];

1326 TransformToType[MVT::ppcf128] = MVT::i128;

1328 }

1329 }

1330

1331

1332

1334 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];

1335 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];

1336 TransformToType[MVT::f128] = MVT::i128;

1338 }

1339

1340

1341

1343 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];

1344 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];

1345 TransformToType[MVT::f80] = MVT::i32;

1347 }

1348

1349

1350

1352 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];

1353 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];

1354 TransformToType[MVT::f64] = MVT::i64;

1356 }

1357

1358

1359

1361 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];

1362 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];

1363 TransformToType[MVT::f32] = MVT::i32;

1365 }

1366

1367

1368

1369

1371

1374

1375 if (!UseFPRegsForHalfType) {

1376 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];

1377 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];

1378 } else {

1379 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];

1380 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];

1381 }

1382 TransformToType[MVT::f16] = MVT::f32;

1383 if (SoftPromoteHalfType) {

1385 } else {

1387 }

1388 }

1389

1390

1391

1392

1394 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];

1395 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];

1396 TransformToType[MVT::bf16] = MVT::f32;

1398 }

1399

1400

1401 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;

1402 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {

1405 continue;

1406

1409 bool IsLegalWiderType = false;

1412 switch (PreferredAction) {

1415 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :

1416 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;

1417

1418

1419 for (unsigned nVT = i + 1;

1422

1423

1426 TransformToType[i] = SVT;

1427 RegisterTypeForVT[i] = SVT;

1428 NumRegistersForVT[i] = 1;

1430 IsLegalWiderType = true;

1431 break;

1432 }

1433 }

1434 if (IsLegalWiderType)

1435 break;

1436 [[fallthrough]];

1437 }

1438

1441

1442 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {

1447 EC.getKnownMinValue() &&

1449 TransformToType[i] = SVT;

1450 RegisterTypeForVT[i] = SVT;

1451 NumRegistersForVT[i] = 1;

1453 IsLegalWiderType = true;

1454 break;

1455 }

1456 }

1457 if (IsLegalWiderType)

1458 break;

1459 } else {

1460

1463 TransformToType[i] = NVT;

1465 RegisterTypeForVT[i] = NVT;

1466 NumRegistersForVT[i] = 1;

1467 break;

1468 }

1469 }

1470 [[fallthrough]];

1471

1474 MVT IntermediateVT;

1475 MVT RegisterVT;

1476 unsigned NumIntermediates;

1478 NumIntermediates, RegisterVT, this);

1479 NumRegistersForVT[i] = NumRegisters;

1480 assert(NumRegistersForVT[i] == NumRegisters &&

1481 "NumRegistersForVT size cannot represent NumRegisters!");

1482 RegisterTypeForVT[i] = RegisterVT;

1483

1485 if (NVT == VT) {

1486

1487 TransformToType[i] = MVT::Other;

1492 else if (EC.getKnownMinValue() > 1)

1494 else

1495 ValueTypeActions.setTypeAction(VT, EC.isScalable()

1498 } else {

1499 TransformToType[i] = NVT;

1501 }

1502 break;

1503 }

1504 default:

1506 }

1507 }

1508

1509

1510

1511

1512

1513

1518 RepRegClassForVT[i] = RRC;

1519 RepRegClassCostForVT[i] = Cost;

1520 }

1521}

1522

1524 EVT VT) const {

1525 assert(!VT.isVector() && "No default SetCC type for vectors!");

1527}

1528

1530 return MVT::i32;

1531}

1532

1533

1534

1535

1536

1537

1538

1539

1540

1542 EVT VT, EVT &IntermediateVT,

1543 unsigned &NumIntermediates,

1544 MVT &RegisterVT) const {

1546

1547

1548

1549

1550

1551

1557 IntermediateVT = RegisterEVT;

1559 NumIntermediates = 1;

1560 return 1;

1561 }

1562 }

1563

1564

1566

1567 unsigned NumVectorRegs = 1;

1568

1569

1570

1573 EVT PartVT = VT;

1574 do {

1575

1577 PartVT = LK.second;

1578 } while (LK.first != TypeLegal);

1579

1582 "Don't know how to legalize this scalable vector type");

1583 }

1584

1585 NumIntermediates =

1588 IntermediateVT = PartVT;

1590 return NumIntermediates;

1591 }

1592

1593

1594

1598 }

1599

1600

1601

1605 NumVectorRegs <<= 1;

1606 }

1607

1608 NumIntermediates = NumVectorRegs;

1609

1612 NewVT = EltTy;

1613 IntermediateVT = NewVT;

1614

1616 RegisterVT = DestVT;

1617

1618 if (EVT(DestVT).bitsLT(NewVT)) {

1620

1621 if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue()))

1623 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());

1624 }

1625

1626

1627

1628 return NumVectorRegs;

1629}

1630

1636

1637

1638

1639

1640

1641 const bool OptForSize =

1645

1646

1647

1648 return (OptForSize || Range <= MaxJumpTableSize) &&

1649 (NumCases * 100 >= Range * MinDensity);

1650}

1651

1653 EVT ConditionVT) const {

1655}

1656

1657

1658

1659

1660

1667 unsigned NumValues = ValueVTs.size();

1668 if (NumValues == 0) return;

1669

1670 for (unsigned j = 0, f = NumValues; j != f; ++j) {

1671 EVT VT = ValueVTs[j];

1673

1674 if (attr.hasRetAttr(Attribute::SExt))

1676 else if (attr.hasRetAttr(Attribute::ZExt))

1678

1681

1682 unsigned NumParts =

1684 MVT PartVT =

1686

1687

1689 if (attr.hasRetAttr(Attribute::InReg))

1690 Flags.setInReg();

1691

1692

1693 if (attr.hasRetAttr(Attribute::SExt))

1694 Flags.setSExt();

1695 else if (attr.hasRetAttr(Attribute::ZExt))

1696 Flags.setZExt();

1697

1698 for (unsigned i = 0; i < NumParts; ++i)

1700 }

1701}

1702

1705 return DL.getABITypeAlign(Ty);

1706}

1707

1711

1712

1713

1714

1715

1717 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {

1718

1719 if (Fast != nullptr)

1721 return true;

1722 }

1723

1724

1726}

1727

1733}

1734

1737 unsigned AddrSpace, Align Alignment,

1739 unsigned *Fast) const {

1741 Flags, Fast);

1742}

1743

1747 unsigned *Fast) const {

1750}

1751

1755 unsigned *Fast) const {

1759}

1760

1761

1762

1763

1764

1766 enum InstructionOpcodes {

1767#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,

1768#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM

1769#include "llvm/IR/Instruction.def"

1770 };

1771 switch (static_cast<InstructionOpcodes>(Opcode)) {

1772 case Ret: return 0;

1773 case Br: return 0;

1774 case Switch: return 0;

1775 case IndirectBr: return 0;

1776 case Invoke: return 0;

1777 case CallBr: return 0;

1778 case Resume: return 0;

1779 case Unreachable: return 0;

1780 case CleanupRet: return 0;

1781 case CatchRet: return 0;

1782 case CatchPad: return 0;

1783 case CatchSwitch: return 0;

1784 case CleanupPad: return 0;

1804 case Alloca: return 0;

1807 case GetElementPtr: return 0;

1808 case Fence: return 0;

1809 case AtomicCmpXchg: return 0;

1810 case AtomicRMW: return 0;

1826 case PHI: return 0;

1827 case Call: return 0;

1829 case UserOp1: return 0;

1830 case UserOp2: return 0;

1831 case VAArg: return 0;

1837 case LandingPad: return 0;

1839 }

1840

1842}

1843

1846 bool UseTLS) const {

1847

1848

1850 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";

1851 auto UnsafeStackPtr =

1852 dyn_cast_or_null(M->getNamedValue(UnsafeStackPtrVar));

1853

1855 PointerType *StackPtrTy = DL.getAllocaPtrType(M->getContext());

1856

1857 if (!UnsafeStackPtr) {

1858 auto TLSModel = UseTLS ?

1861

1862

1863

1866 UnsafeStackPtrVar, nullptr, TLSModel);

1867 } else {

1868

1869

1870

1871 if (UnsafeStackPtr->getValueType() != StackPtrTy)

1873 if (UseTLS != UnsafeStackPtr->isThreadLocal())

1875 (UseTLS ? "" : "not ") + "be thread-local");

1876 }

1877 return UnsafeStackPtr;

1878}

1879

1884

1885

1886

1890 M->getOrInsertFunction("__safestack_pointer_address", PtrTy);

1892}

1893

1894

1895

1896

1897

1898

1899

1903

1904

1905

1906

1908 return false;

1909

1910

1911 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)

1912 return false;

1913

1914

1916 return false;

1917

1918

1919 switch (AM.Scale) {

1920 case 0:

1921 break;

1922 case 1:

1924 return false;

1925

1926 break;

1927 case 2:

1929 return false;

1930

1931 break;

1932 default:

1933 return false;

1934 }

1935

1936 return true;

1937}

1938

1939

1940

1941

1942

1943

1944

1949 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);

1950 if (GlobalVariable *G = dyn_cast_or_null(C))

1952 return C;

1953 }

1954 return nullptr;

1955}

1956

1957

1958

1960 if (!M.getNamedValue("__stack_chk_guard")) {

1963 nullptr, "__stack_chk_guard");

1964

1965

1966 if (M.getDirectAccessExternalData() &&

1972 GV->setDSOLocal(true);

1973 }

1974}

1975

1976

1977

1979 return M.getNamedValue("__stack_chk_guard");

1980}

1981

1983 return nullptr;

1984}

1985

1988}

1989

1992}

1993

1996}

1997

2000}

2001

2004}

2005

2008}

2009

2013 return PrefLoopAlignment;

2014}

2015

2018 return MaxBytesForAlignment;

2019}

2020

2021

2022

2023

2024

2025

2026

2029 return F.getFnAttribute("reciprocal-estimates").getValueAsString();

2030}

2031

2032

2033

2034

2035

2037 std::string Name = VT.isVector() ? "vec-" : "";

2038

2039 Name += IsSqrt ? "sqrt" : "div";

2040

2041

2043 Name += "d";

2045 Name += "h";

2046 } else {

2048 "Unexpected FP type for reciprocal estimate");

2049 Name += "f";

2050 }

2051

2052 return Name;

2053}

2054

2055

2056

2057

2060 const char RefStepToken = ':';

2061 Position = In.find(RefStepToken);

2063 return false;

2064

2065 StringRef RefStepString = In.substr(Position + 1);

2066

2067

2068 if (RefStepString.size() == 1) {

2069 char RefStepChar = RefStepString[0];

2070 if (isDigit(RefStepChar)) {

2071 Value = RefStepChar - '0';

2072 return true;

2073 }

2074 }

2076}

2077

2078

2079

2080

2082 if (Override.empty())

2084

2086 Override.split(OverrideVector, ',');

2087 unsigned NumArgs = OverrideVector.size();

2088

2089

2090 if (NumArgs == 1) {

2091

2092

2093 size_t RefPos;

2096

2097 Override = Override.substr(0, RefPos);

2098 }

2099

2100

2101 if (Override == "all")

2103

2104

2105 if (Override == "none")

2107

2108

2109 if (Override == "default")

2111 }

2112

2113

2115 std::string VTNameNoSize = VTName;

2116 VTNameNoSize.pop_back();

2117 static const char DisabledPrefix = '!';

2118

2119 for (StringRef RecipType : OverrideVector) {

2120 size_t RefPos;

2123 RecipType = RecipType.substr(0, RefPos);

2124

2125

2126 bool IsDisabled = RecipType[0] == DisabledPrefix;

2127 if (IsDisabled)

2128 RecipType = RecipType.substr(1);

2129

2130 if (RecipType == VTName || RecipType == VTNameNoSize)

2133 }

2134

2136}

2137

2138

2139

2140

2142 if (Override.empty())

2144

2146 Override.split(OverrideVector, ',');

2147 unsigned NumArgs = OverrideVector.size();

2148

2149

2150 if (NumArgs == 1) {

2151

2152

2153 size_t RefPos;

2157

2158

2159 Override = Override.substr(0, RefPos);

2160 assert(Override != "none" &&

2161 "Disabled reciprocals, but specifed refinement steps?");

2162

2163

2164 if (Override == "all" || Override == "default")

2165 return RefSteps;

2166 }

2167

2168

2170 std::string VTNameNoSize = VTName;

2171 VTNameNoSize.pop_back();

2172

2173 for (StringRef RecipType : OverrideVector) {

2174 size_t RefPos;

2177 continue;

2178

2179 RecipType = RecipType.substr(0, RefPos);

2180 if (RecipType == VTName || RecipType == VTNameNoSize)

2181 return RefSteps;

2182 }

2183

2185}

2186

2190}

2191

2195}

2196

2200}

2201

2205}

2206

2210

2211

2214 return false;

2215

2216

2217

2219 return true;

2220

2222

2223

2224

2227 return false;

2228

2229 unsigned Fast = 0;

2231 MMO, &Fast) &&

2233}

2234

2237}

2238

2245

2246 if (LI.hasMetadata(LLVMContext::MD_nontemporal))

2248

2249 if (LI.hasMetadata(LLVMContext::MD_invariant_load))

2251

2254 nullptr, LibInfo))

2256

2258 return Flags;

2259}

2260

2265

2266 if (SI.isVolatile())

2268

2269 if (SI.hasMetadata(LLVMContext::MD_nontemporal))

2271

2272

2274 return Flags;

2275}

2276

2281

2282 if (const AtomicRMWInst *RMW = dyn_cast(&AI)) {

2283 if (RMW->isVolatile())

2285 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast(&AI)) {

2286 if (CmpX->isVolatile())

2288 } else

2290

2291

2293 return Flags;

2294}

2295

2301 else

2302 return nullptr;

2303}

2304

2310 else

2311 return nullptr;

2312}

2313

2314

2315

2316

2317

2320 auto &MF = *MI.getMF();

2321 auto &MRI = MF.getRegInfo();

2322

2323

2324

2325

2326

2327

2328 auto maxUses = [](unsigned RematCost) {

2329

2330 if (RematCost == 1)

2331 return std::numeric_limits::max();

2332 if (RematCost == 2)

2333 return 2U;

2334

2335

2336 if (RematCost > 2)

2337 return 1U;

2339 };

2340

2341 switch (MI.getOpcode()) {

2342 default:

2343 return false;

2344

2345

2346 case TargetOpcode::G_CONSTANT:

2347 case TargetOpcode::G_FCONSTANT:

2348 case TargetOpcode::G_FRAME_INDEX:

2349 case TargetOpcode::G_INTTOPTR:

2350 return true;

2351 case TargetOpcode::G_GLOBAL_VALUE: {

2353 Register Reg = MI.getOperand(0).getReg();

2354 unsigned MaxUses = maxUses(RematCost);

2355 if (MaxUses == UINT_MAX)

2356 return true;

2357 return MRI.hasAtMostUserInstrs(Reg, MaxUses);

2358 }

2359 }

2360}

unsigned const MachineRegisterInfo * MRI

AMDGPU Register Bank Select

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file contains the simple types necessary to represent the attributes associated with functions a...

This file implements the BitVector class.

Module.h This file contains the declarations for the Module class.

unsigned const TargetRegisterInfo * TRI

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

static bool isDigit(const char C)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallVector class.

static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)

#define OP_TO_LIBCALL(Name, Enum)

static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))

static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)

static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)

Return the character position and value (a single numeric character) of a customized refinement opera...

static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))

static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))

Minimum jump table density for normal functions.

static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)

static std::string getReciprocalOpName(bool IsSqrt, EVT VT)

Construct a string for the given reciprocal operation of the given type.

static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return the customized refinement step count for this operation on the...

static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...

static StringRef getRecipEstimateForFunc(MachineFunction &MF)

Get the reciprocal estimate attribute string for a function that will override the target defaults.

static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))

Minimum jump table density for -Os or -Oz functions.

This file describes how to lower LLVM code to machine code.

This pass exposes codegen information to IR-level passes.

Class for arbitrary precision integers.

A cache of @llvm.assume calls within a function.

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

bool hasRetAttr(Attribute::AttrKind Kind) const

Return true if the attribute exists for the return value.

const Function * getParent() const

Return the enclosing method, or null if none.

void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

setBitsInMask - Add '1' bits from Mask to this vector.

iterator_range< const_set_bits_iterator > set_bits() const

BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...

This class represents a range of values.

unsigned getActiveBits() const

Compute the maximal number of active bits needed to represent every value in this range.

ConstantRange umul_sat(const ConstantRange &Other) const

Perform an unsigned saturating multiplication of two constant ranges.

ConstantRange subtract(const APInt &CI) const

Subtract the specified constant from the endpoints of this constant range.

This is an important base class in LLVM.

This class represents an Operation in the Expression.

A parsed version of the target data layout string in and methods for querying it.

unsigned getPointerSize(unsigned AS=0) const

Layout pointer size in bytes, rounded up to a whole number of bytes.

static constexpr ElementCount getScalable(ScalarTy MinVal)

static constexpr ElementCount getFixed(ScalarTy MinVal)

constexpr bool isScalar() const

Exactly one element.

A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...

Module * getParent()

Get the module that this global value is contained inside of...

@ HiddenVisibility

The GV is hidden.

@ ExternalLinkage

Externally visible function.

Common base class shared among various IRBuilders.

FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")

BasicBlock * GetInsertBlock() const

CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args={}, const Twine &Name="", MDNode *FPMathTag=nullptr)

bool hasAtomicStore() const LLVM_READONLY

Return true if this atomic instruction stores to memory.

bool hasMetadata() const

Return true if this instruction has any metadata attached to it.

@ MAX_INT_BITS

Maximum number of bits that can be specified.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

Value * getPointerOperand()

bool isVolatile() const

Return true if this is a load from a volatile memory location.

Align getAlign() const

Return the alignment of the access that is being performed.

uint64_t getScalarSizeInBits() const

bool isVector() const

Return true if this is a vector value type.

bool isScalableVector() const

Return true if this is a vector value type where the runtime length is machine dependent.

static auto all_valuetypes()

SimpleValueType Iteration.

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

ElementCount getVectorElementCount() const

bool isScalarInteger() const

Return true if this is an integer, not including vectors.

static MVT getVectorVT(MVT VT, unsigned NumElements)

MVT getVectorElementType() const

bool isValid() const

Return true if this is a valid simple valuetype.

static MVT getIntegerVT(unsigned BitWidth)

static auto fp_valuetypes()

MVT getPow2VectorType() const

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const

Representation of each machine instruction.

unsigned getNumOperands() const

Retuns the total number of operands.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

A description of a memory reference used in the backend.

unsigned getAddrSpace() const

Flags

Flags values. These may be or'd together.

@ MOVolatile

The memory access is volatile.

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

@ MOLoad

The memory access reads data.

@ MONonTemporal

The memory access is non-temporal.

@ MOInvariant

The memory access always returns the same value (or traps).

@ MOStore

The memory access writes data.

Flags getFlags() const

Return the raw flags of the source value,.

Align getAlign() const

Return the minimum known alignment in bytes of the actual memory reference.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isFI() const

isFI - Tests if this is a MO_FrameIndex operand.

void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

A Module instance is used to store all the information related to an LLVM module.

Class to represent pointers.

static PointerType * getUnqual(Type *ElementType)

This constructs a pointer to an object of the specified type in the default address space (address sp...

Analysis providing profile information.

Wrapper class representing virtual and physical registers.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

const DataLayout & getDataLayout() const

LLVMContext * getContext() const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

constexpr bool empty() const

empty - Check if the string is empty.

constexpr size_t size() const

size - Get the string size.

static constexpr size_t npos

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

Provides information about what library functions are available for the current target.

LegalizeTypeAction getTypeAction(MVT VT) const

void setTypeAction(MVT VT, LegalizeTypeAction Action)

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...

virtual Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const

Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parame...

int InstructionOpcodeToISD(unsigned Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

virtual void finalizeLowering(MachineFunction &MF) const

Execute target specific actions to finalize target lowering.

void initActions()

Initialize all of the actions to default values.

bool PredictableSelectIsExpensive

Tells the code generator that select is more expensive than a branch if the branch is usually predict...

unsigned MaxStoresPerMemcpyOptSize

Likewise for functions with the OptSize attribute.

MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...

virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const

Returns the target-specific address of the unsafe stack pointer.

int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...

virtual bool canOpTrap(unsigned Op, EVT VT) const

Returns true if the operation can trap for the value type.

virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const

Check whether or not MI needs to be moved close to its uses.

virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const

Return the maximum amount of bytes allowed to be emitted when padding for alignment.

void setMaximumJumpTableSize(unsigned)

Indicate the maximum number of entries in jump tables.

virtual unsigned getMinimumJumpTableEntries() const

Return lower limit for number of blocks in a jump table.

const TargetMachine & getTargetMachine() const

unsigned MaxLoadsPerMemcmp

Specify maximum number of load instructions per memcmp call.

virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain targets require unusual breakdowns of certain types.

virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...

unsigned MaxGluedStoresPerMemcpy

Specify max number of store instructions to glue in inlined memcpy.

virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

@ TypeScalarizeScalableVector

virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...

void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked load does or does not work with the specified type and ind...

virtual Value * getSDagStackGuard(const Module &M) const

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...

virtual bool useFPRegsForHalfType() const

virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...

void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed load does or does not work with the specified type and indicate w...

virtual bool softPromoteHalfType() const

unsigned getMaximumJumpTableSize() const

Return upper limit for number of entries in a jump table.

virtual MVT::SimpleValueType getCmpLibcallReturnType() const

Return the ValueType for comparison libcalls.

unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const

Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...

bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const

Return true if the value types that can be represented by the specified register class are all legal.

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Let target indicate that an extending atomic load of the specified type is legal.

Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const

virtual Function * getSSPStackGuardCheck(const Module &M) const

If the target has a standard stack protection check function that performs validation and error handl...

MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const

virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const

Determine if the target supports unaligned memory accesses.

unsigned MaxStoresPerMemsetOptSize

Likewise for functions with the OptSize attribute.

EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const

Returns the type for the shift amount of a shift opcode.

unsigned MaxStoresPerMemmove

Specify maximum number of store instructions per memmove call.

virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const

Return the preferred loop alignment.

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

int getDivRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a division of the given type based on the function's attributes.

virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const

Return the ValueType of the result of SETCC operations.

MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const

virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const

For types supported by the target, this is an identity function.

unsigned MaxStoresPerMemmoveOptSize

Likewise for functions with the OptSize attribute.

virtual Value * getIRStackGuard(IRBuilderBase &IRB) const

If the target has a standard location for the stack protector guard, returns the address of that loca...

virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const

Returns preferred type for switch condition.

bool isTypeLegal(EVT VT) const

Return true if the target has native support for the specified value type.

bool EnableExtLdPromotion

int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...

void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed store does or does not work with the specified type and indicate ...

virtual bool isJumpTableRelative() const

virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const

Return the type to use for a scalar shift opcode, given the shifted amount type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked store does or does not work with the specified type and in...

unsigned MaxStoresPerMemset

Specify maximum number of store instructions per memset call.

void setMinimumJumpTableEntries(unsigned Val)

Indicate the minimum number of blocks to generate jump tables.

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

@ UndefinedBooleanContent

virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

Return true if the target supports a memory access of this type for the given address space and align...

unsigned MaxLoadsPerMemcmpOptSize

Likewise for functions with the OptSize attribute.

MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const

void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...

unsigned getMinimumJumpTableDensity(bool OptForSize) const

Return lower limit of the density in a jump table.

virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const

Return the largest legal super-reg register class of the register class for the specified type and it...

TargetLoweringBase(const TargetMachine &TM)

NOTE: The TargetMachine owns TLOF.

LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const

Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

unsigned GatherAllAliasesMaxDepth

Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...

LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...

int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a square root of the given type based on the function's attribut...

bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

This function returns true if the memory access is aligned or if the target allows this specific unal...

virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Inserts in the IR a target-specific intrinsic specifying a fence.

unsigned MaxStoresPerMemcpy

Specify maximum number of store instructions per memcpy call.

MVT getRegisterType(MVT VT) const

Return the type of registers that this ValueType will eventually require.

virtual void insertSSPDeclarations(Module &M) const

Inserts necessary declarations for SSP (stack protection) purpose.

void setJumpIsExpensive(bool isExpensive=true)

Tells the code generator not to expand logic operations on comparison predicates into separate sequen...

LegalizeAction getOperationAction(unsigned Op, EVT VT) const

Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...

MVT getTypeToPromoteTo(unsigned Op, MVT VT) const

If the action for this operation is to promote, this method returns the ValueType to promote to.

virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

Vector types are broken down into some number of legal first class types.

std::pair< LegalizeTypeAction, EVT > LegalizeKind

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

Primary interface to the complete machine description for the target machine.

bool isPositionIndependent() const

virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const

Returns true if a cast between SrcAS and DestAS is a noop.

const Triple & getTargetTriple() const

Reloc::Model getRelocationModel() const

Returns the code generation relocation model.

unsigned LoopAlignment

If greater than 0, override TargetLoweringBase::PrefLoopAlignment.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

unsigned getGISelRematGlobalCost() const

bool isWindowsGNUEnvironment() const

bool isAndroid() const

Tests whether the target is Android.

bool isPPC64() const

Tests whether the target is 64-bit PowerPC (little and big endian).

bool isOSDarwin() const

Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

int getNumOccurrences() const

constexpr LeafTy coefficientNextPowerOf2() const

constexpr bool isScalable() const

Returns whether the quantity is scaled by a runtime quantity (vscale).

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const

We do not provide the '/' operator here because division for polynomial types does not work in the sa...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ MERGE_VALUES

MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...

@ DELETED_NODE

DELETED_NODE - This is an illegal value that is used to catch errors.

@ SET_FPENV

Sets the current floating-point environment.

@ VECREDUCE_SEQ_FADD

Generic reduction nodes.

@ FGETSIGN

INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...

@ SMULFIX

RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...

@ ADDC

Carry-setting nodes for multiple precision addition and subtraction.

@ RESET_FPENV

Set floating-point environment to default state.

@ FMAD

FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.

@ ADD

Simple integer binary arithmetic operators.

@ LOAD

LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...

@ SMULFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ SET_FPMODE

Sets the current dynamic floating-point control modes.

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ VECTOR_FIND_LAST_ACTIVE

@ FATAN2

FATAN2 - atan2, inspired by libm.

@ ATOMIC_CMP_SWAP_WITH_SUCCESS

Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ CONCAT_VECTORS

CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...

@ VECREDUCE_FMAX

FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.

@ FADD

Simple binary floating point operators.

@ VECREDUCE_FMAXIMUM

FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....

@ ABS

ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.

@ RESET_FPMODE

Sets default dynamic floating-point control modes.

@ SIGN_EXTEND_VECTOR_INREG

SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...

@ BITCAST

BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...

@ FLDEXP

FLDEXP - ldexp, inspired by libm (op0 * 2**op1).

@ SDIVFIX

RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

@ SIGN_EXTEND

Conversion operators.

@ AVGCEILS

AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...

@ READSTEADYCOUNTER

READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.

@ VECREDUCE_FADD

These reductions have relaxed evaluation order semantics, and have a single vector operand.

@ CTTZ_ZERO_UNDEF

Bit counting operators with an undefined result for zero inputs.

@ PREFETCH

PREFETCH - This corresponds to a prefetch intrinsic.

@ FSINCOS

FSINCOS - Compute both fsin and fcos as a single operation.

@ SETCCCARRY

Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...

@ FNEG

Perform various unary floating-point operations inspired by libm.

@ SSUBO

Same for subtraction.

@ IS_FPCLASS

Performs a check of floating point class property, defined by IEEE-754.

@ SSUBSAT

RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ SPLAT_VECTOR

SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.

@ SADDO

RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.

@ VECREDUCE_ADD

Integer reductions may have a result type larger than the vector element type.

@ GET_FPMODE

Reads the current dynamic floating-point control modes.

@ GET_FPENV

Gets the current floating-point environment.

@ SHL

Shift and rotation operations.

@ VECTOR_SHUFFLE

VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.

@ FMINNUM_IEEE

FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ DEBUGTRAP

DEBUGTRAP - Trap intended to get the attention of a debugger.

@ ATOMIC_CMP_SWAP

Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...

@ FMINNUM

FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.

@ UBSANTRAP

UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.

@ SSHLSAT

RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.

@ SMULO

Same for multiplication.

@ ANY_EXTEND_VECTOR_INREG

ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ SDIVFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ FP_EXTEND

X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.

@ UADDO_CARRY

Carry-using nodes for multiple precision addition and subtraction.

@ FMINIMUM

FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ READCYCLECOUNTER

READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ TRAP

TRAP - Trapping instruction.

@ GET_FPENV_MEM

Gets the current floating-point environment.

@ SCMP

[US]CMP - 3-way comparison of signed or unsigned integers.

@ AVGFLOORS

AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...

@ ADDE

Carry-using nodes for multiple precision addition and subtraction.

@ FREEZE

FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

@ VECTOR_SPLICE

VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...

@ ATOMIC_SWAP

Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...

@ FFREXP

FFREXP - frexp, extract fractional and exponent component of a floating-point value.

@ FP_ROUND

X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...

@ VECTOR_COMPRESS

VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....

@ ZERO_EXTEND_VECTOR_INREG

ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...

@ ADDRSPACECAST

ADDRSPACECAST - This operator converts between pointers of different address spaces.

@ FP_TO_SINT_SAT

FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

@ SADDSAT

RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...

@ GET_DYNAMIC_AREA_OFFSET

GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.

@ SET_FPENV_MEM

Sets the current floating point environment.

@ FMINIMUMNUM

FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with FMINNUM_IEEE and FMAXNUM_IEEE besid...

@ TRUNCATE_SSAT_S

TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand [SU] located in middle, prefix for SAT means i...

@ ABDS

ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...

@ SADDO_CARRY

Carry-using overflow-aware nodes for multiple precision addition and subtraction.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

static const int LAST_INDEXED_MODE

Libcall getFSINCOS(EVT RetVT)

getFSINCOS - Return the FSINCOS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getPOWI(EVT RetVT)

getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getSINTTOFP(EVT OpVT, EVT RetVT)

getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs)

Initialize the default condition code on the libcalls.

Libcall getSYNC(unsigned Opc, MVT VT)

Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.

Libcall getLDEXP(EVT RetVT)

getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getUINTTOFP(EVT OpVT, EVT RetVT)

getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getFREXP(EVT RetVT)

getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall

RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.

Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Libcall getFPTOUINT(EVT OpVT, EVT RetVT)

getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getFPTOSINT(EVT OpVT, EVT RetVT)

getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)

Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...

Libcall getFPEXT(EVT OpVT, EVT RetVT)

getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getFPROUND(EVT OpVT, EVT RetVT)

getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)

Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...

Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)

GetFPLibCall - Helper to return the right libcall for the given floating point type,...

Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

unsigned Log2_32_Ceil(uint32_t Value)

Return the ceil log base 2 of the specified value, 32 if the value is zero.

void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)

Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

auto enum_seq(EnumT Begin, EnumT End)

Iterate over an enum type from Begin up to - but not including - End.

bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)

Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.

bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum

T bit_ceil(T Value)

Returns the smallest integral power of two no smaller than Value if Value is nonzero.

bool isReleaseOrStronger(AtomicOrdering AO)

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

AtomicOrdering

Atomic ordering for LLVM's memory model.

EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)

constexpr T divideCeil(U Numerator, V Denominator)

Returns the integer ceil(Numerator / Denominator).

@ Or

Bitwise or logical OR of integers.

@ Mul

Product of integers.

@ Xor

Bitwise or logical XOR of integers.

@ And

Bitwise or logical AND of integers.

void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())

ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...

bool isAcquireOrStronger(AtomicOrdering AO)

This struct is a compact representation of a valid (non-zero power of two) alignment.

EVT getPow2VectorType(LLVMContext &Context) const

Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

ElementCount getVectorElementCount() const

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

bool isPow2VectorType() const

Returns true if the given vector is a power of 2.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)

Returns the EVT that represents an integer with the given number of bits.

bool isFixedLengthVector() const

EVT getRoundIntegerType(LLVMContext &Context) const

Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...

bool isVector() const

Return true if this is a vector value type.

EVT getScalarType() const

If this is a vector type, return the element type, otherwise return this.

Type * getTypeForEVT(LLVMContext &Context) const

This method returns an LLVM type corresponding to the specified EVT.

EVT getVectorElementType() const

Given a vector type, return the type of each element.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

bool isZeroSized() const

Test if the given EVT has zero size, this will fail if called on a scalable type.

EVT getHalfNumVectorElementsVT(LLVMContext &Context) const

bool isInteger() const

Return true if this is an integer or a vector integer type.

OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...