Thumb1InstrInfo.cpp Source File (original) (raw)

24using namespace llvm;

45 Register SrcReg, bool KillSrc,

46 bool RenamableDest, bool RenamableSrc) const {

52 "Thumb1 can only copy GPR registers");

54 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) ||

55 !ARM::tGPRRegClass.contains(DestReg))

59 else {

64 auto InstUpToI = MBB.end();

65 while (InstUpToI != I)

70 if (UsedRegs.available(ARM::CPSR)) {

74 return;

75 }

79 BitVector Allocatable = RegInfo->getAllocatableSet(

80 MF, RegInfo->getRegClass(ARM::hGPRRegClassID));

82 Register TmpReg = ARM::NoRegister;

84 if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) {

85 TmpReg = ARM::R12;

86 } else {

89 TmpReg = Reg;

90 break;

91 }

92 }

93 }

95 if (TmpReg) {

102 return;

103 }

104

105

112 }

113}

114

117 Register SrcReg, bool isKill, int FI,

121 assert((RC == &ARM::tGPRRegClass ||

123 "Unknown regclass!");

124

125 if (RC == &ARM::tGPRRegClass ||

128 if (I != MBB.end()) DL = I->getDebugLoc();

129

141 }

142}

143

152 "Unknown regclass!");

153

157 if (I != MBB.end()) DL = I->getDebugLoc();

158

169 }

170}

171

172void Thumb1InstrInfo::expandLoadStackGuard(

176 const auto *GV = cast((*MI->memoperands_begin())->getValue());

177

179 "TLS stack protector not supported for Thumb1 targets");

180

181 unsigned Instr;

182 if (!GV->isDSOLocal())

183 Instr = ARM::tLDRLIT_ga_pcrel;

184 else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())

185 Instr = ARM::t2MOVi32imm;

186 else if (ST.genExecuteOnly())

187 Instr = ARM::tMOVi32imm;

188 else

189 Instr = ARM::tLDRLIT_ga_abs;

191}

192

194

195

196

197

198

199 unsigned Opcode = N->getMachineOpcode();

200 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)

201 return true;

202

203 return false;

204}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file implements the BitVector class.

Module.h This file contains the declarations for the Module class.

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const

ARMBaseInstrInfo(const ARMSubtarget &STI, const ARMBaseRegisterInfo &TRI)

const ARMBaseRegisterInfo * getRegisterInfo() const override

bool test(unsigned Idx) const

iterator_range< const_set_bits_iterator > set_bits() const

Module * getParent()

Get the module that this global value is contained inside of...

A set of register units used to track register liveness.

bool available(MCRegister Reg) const

Returns true if no part of physical register Reg is live.

LLVM_ABI void stepBackward(const MachineInstr &MI)

Updates liveness when stepping backwards over the instruction MI.

LLVM_ABI void addLiveOuts(const MachineBasicBlock &MBB)

Adds registers living out of block MBB.

MCInstBuilder & addReg(MCRegister Reg)

Add a new register operand.

MCInstBuilder & addImm(int64_t Val)

Add a new integer immediate operand.

Instances of this class represent a single low-level machine instruction.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

LLVM_ABI bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

StringRef getStackProtectorGuard() const

Get/set what kind of stack protector guard to use.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Represents one node in the SelectionDAG.

bool hasSuperClassEq(const TargetRegisterClass *RC) const

Returns true if RC is a super-class of or equal to this class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Thumb1InstrInfo(const ARMSubtarget &STI)

Definition Thumb1InstrInfo.cpp:26

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition Thumb1InstrInfo.cpp:144

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition Thumb1InstrInfo.cpp:42

MCInst getNop() const override

Return the noop instruction to use for a noop.

Definition Thumb1InstrInfo.cpp:30

unsigned getUnindexedOpcode(unsigned Opc) const override

Definition Thumb1InstrInfo.cpp:38

bool canCopyGluedNodeDuringSchedule(SDNode *N) const override

Definition Thumb1InstrInfo.cpp:193

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition Thumb1InstrInfo.cpp:115

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static bool isARMLowRegister(MCRegister Reg)

isARMLowRegister - Returns true if the register is a low register (r0-r7).

static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)

Get the operands corresponding to the given Pred value.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getDefRegState(bool B)

unsigned getKillRegState(bool B)

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.