TwoAddressInstructionPass.cpp Source File (original) (raw)

62#include

63#include

64#include

66using namespace llvm;

68#define DEBUG_TYPE "twoaddressinstruction"

70 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");

71 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");

72 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");

73 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");

74 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");

75 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");

80 cl::desc("Coalesce copies by rescheduling (default=true)"),

87 cl::desc("Maximum number of dataflow edges to traverse when evaluating "

88 "the benefit of commuting operands"));

90namespace {

92class TwoAddressInstructionImpl {

102

103

105

106

108

109

111

112

113

114

116

117

118

119

121

123

124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);

125

126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);

127

129 bool &IsSrcPhys, bool &IsDstPhys) const;

130

133 bool isPlainlyKilled(const MachineOperand &MO) const;

134

136

138 bool &IsCopy, Register &DstReg,

139 bool &IsDstPhys) const;

140

142

145

147

149

152

153 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,

154 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);

155

157

160 Register RegB, unsigned &Dist);

161

163

168

171 unsigned SrcIdx, unsigned DstIdx,

172 unsigned &Dist, bool shouldOnlyCommute);

173

175 unsigned DstOpIdx,

176 unsigned BaseOpIdx,

177 bool BaseOpKilled,

178 unsigned Dist);

179 void scanUses(Register DstReg);

180

182

185

186 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);

187 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);

189 bool processStatepoint(MachineInstr *MI, TiedOperandMap &TiedOperands);

190

191public:

195 void setOptLevel(CodeGenOptLevel Level) { OptLevel = Level; }

196 bool run();

197};

198

200public:

201 static char ID;

202

206 }

207

208

210 TwoAddressInstructionImpl Impl(MF, this);

211

212

214 Impl.setOptLevel(CodeGenOptLevel::None);

215 return Impl.run();

216 }

217

228 }

229};

230

231}

232

236

237

238 TwoAddressInstructionImpl Impl(MF, MFAM);

241

243 bool Changed = Impl.run();

244 if (!Changed)

253 return PA;

254}

255

256char TwoAddressInstructionLegacyPass::ID = 0;

257

259

261 "Two-Address instruction pass", false, false)

265

266TwoAddressInstructionImpl::TwoAddressInstructionImpl(

268 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),

269 TRI(Func.getSubtarget().getRegisterInfo()),

270 InstrItins(Func.getSubtarget().getInstrItineraryData()),

271 MRI(&Func.getRegInfo()),

274 OptLevel(Func.getTarget().getOptLevel()) {

276 .getManager();

278}

279

280TwoAddressInstructionImpl::TwoAddressInstructionImpl(MachineFunction &Func,

282 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),

283 TRI(Func.getSubtarget().getRegisterInfo()),

284 InstrItins(Func.getSubtarget().getInstrItineraryData()),

285 MRI(&Func.getRegInfo()), OptLevel(Func.getTarget().getOptLevel()) {

287 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;

289 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;

291 AA = &AAPass->getAAResults();

292 else

293 AA = nullptr;

294}

295

296

298TwoAddressInstructionImpl::getSingleDef(Register Reg,

302 if (DefMI.getParent() != BB || DefMI.isDebugValue())

303 continue;

304 if (!Ret)

306 else if (Ret != &DefMI)

307 return nullptr;

308 }

309 return Ret;

310}

311

312

313

314

315

316

317

318

319bool TwoAddressInstructionImpl::isRevCopyChain(Register FromReg, Register ToReg,

320 int Maxlen) {

322 for (int i = 0; i < Maxlen; i++) {

324 if (!Def || Def ->isCopy())

325 return false;

326

327 TmpReg = Def->getOperand(1).getReg();

328

329 if (TmpReg == ToReg)

330 return true;

331 }

332 return false;

333}

334

335

336

337

338

339bool TwoAddressInstructionImpl::noUseAfterLastDef(Register Reg, unsigned Dist,

340 unsigned &LastDef) {

341 LastDef = 0;

342 unsigned LastUse = Dist;

345 if (MI->getParent() != MBB || MI->isDebugValue())

346 continue;

348 if (DI == DistanceMap.end())

349 continue;

350 if (MO.isUse() && DI->second < LastUse)

351 LastUse = DI->second;

352 if (MO.isDef() && DI->second > LastDef)

353 LastDef = DI->second;

354 }

355

356 return !(LastUse > LastDef && LastUse < Dist);

357}

358

359

360

361

363 Register &DstReg, bool &IsSrcPhys,

364 bool &IsDstPhys) const {

365 SrcReg = 0;

366 DstReg = 0;

367 if (MI.isCopy()) {

368 DstReg = MI.getOperand(0).getReg();

369 SrcReg = MI.getOperand(1).getReg();

370 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {

371 DstReg = MI.getOperand(0).getReg();

372 SrcReg = MI.getOperand(2).getReg();

373 } else {

374 return false;

375 }

376

379 return true;

380}

381

382bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,

384

386 return false;

387

388 SlotIndex useIdx = LIS->getInstructionIndex(*MI);

390 assert(I != LR.end() && "Reg must be live-in to use.");

392}

393

394

395

396bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,

398

399

400

401

402

403

404 if (LIS && !LIS->isNotInMIMap(*MI)) {

405 if (Reg.isVirtual())

406 return isPlainlyKilled(MI, LIS->getInterval(Reg));

407

408 if (MRI->isReserved(Reg))

409 return false;

411 return isPlainlyKilled(MI, LIS->getRegUnit(U));

412 });

413 }

414

415 return MI->killsRegister(Reg, nullptr);

416}

417

418

419

420bool TwoAddressInstructionImpl::isPlainlyKilled(

423}

424

425

426

427

428

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431

432

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434

435

436

437

438

439

440

441

443 bool allowFalsePositives) const {

445 while (true) {

446

447 if (Reg.isPhysical() && (allowFalsePositives || MRI->hasOneUse(Reg)))

448 return true;

449 if (!isPlainlyKilled(DefMI, Reg))

450 return false;

451 if (Reg.isPhysical())

452 return true;

454

455

456 if (std::next(Begin) != MRI->def_end())

457 return true;

459 bool IsSrcPhys, IsDstPhys;

461

462

463 if (!isCopyToReg(*DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))

464 return true;

465 Reg = SrcReg;

466 }

467}

468

469

470

472 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {

475 continue;

476 unsigned ti;

477 if (MI.isRegTiedToDefOperand(i, &ti)) {

478 DstReg = MI.getOperand(ti).getReg();

479 return true;

480 }

481 }

482 return false;

483}

484

485

486

487MachineInstr *TwoAddressInstructionImpl::findOnlyInterestingUse(

489 bool &IsDstPhys) const {

493 if (MI->getParent() != MBB)

494 return nullptr;

495 if (isPlainlyKilled(MI, Reg))

496 UseOp = &MO;

497 }

498 if (!UseOp)

499 return nullptr;

501

503 bool IsSrcPhys;

504 if (isCopyToReg(UseMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {

505 IsCopy = true;

507 }

508 IsDstPhys = false;

512 }

513 if (UseMI.isCommutable()) {

516 if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) {

522 }

523 }

524 }

525 return nullptr;

526}

527

528

529

532 while (Reg.isVirtual()) {

534 if (SI == RegMap.end())

535 return 0;

536 Reg = SI->second;

537 }

538 if (Reg.isPhysical())

539 return Reg;

540 return 0;

541}

542

543

544bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,

546 if (RegA == RegB)

547 return true;

548 if (!RegA || !RegB)

549 return false;

550 return TRI->regsOverlap(RegA, RegB);

551}

552

553

554void TwoAddressInstructionImpl::removeMapRegEntry(

558 "removeMapRegEntry must be called with a register or regmask operand.");

559

561 for (auto SI : RegMap) {

564 continue;

565

566 if (MO.isReg()) {

568 if (TRI->regsOverlap(ToReg, Reg))

572 }

573

574 for (auto SrcReg : Srcs)

575 RegMap.erase(SrcReg);

576}

577

578

579

580

581

582

583

584

585

586void TwoAddressInstructionImpl::removeClobberedSrcRegMap(MachineInstr *MI) {

587 if (MI->isCopy()) {

588

589

590

591

592

593

594

595

596

597

598 Register Dst = MI->getOperand(0).getReg();

599 if (!Dst || Dst.isVirtual())

600 return;

601

602 Register Src = MI->getOperand(1).getReg();

603 if (regsAreCompatible(Dst, getMappedReg(Src, SrcRegMap)))

604 return;

605 }

606

609 removeMapRegEntry(MO, SrcRegMap);

610 continue;

611 }

613 continue;

615 if (!Reg || Reg.isVirtual())

616 continue;

617 removeMapRegEntry(MO, SrcRegMap);

618 }

619}

620

621

622bool TwoAddressInstructionImpl::regOverlapsSet(

624 for (unsigned R : Set)

625 if (TRI->regsOverlap(R, Reg))

626 return true;

627

628 return false;

629}

630

631

632

633bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA,

637 unsigned Dist) {

638 if (OptLevel == CodeGenOptLevel::None)

639 return false;

640

641

642

643

644

645

646

647

648

649

650

651

652

653

654

655

656

657

658

659 if (!isPlainlyKilled(MI, RegC))

660 return false;

661

662

663

664

665

666

667

668

669

670

671

673 if (ToRegA) {

676 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA);

677 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA);

678

679

680

681

682

683 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))

684 return true;

685

686

687

688

689 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))

690 return false;

691 }

692

693

694

695 unsigned LastDefC = 0;

696 if (!noUseAfterLastDef(RegC, Dist, LastDefC))

697 return false;

698

699

700

701 unsigned LastDefB = 0;

702 if (!noUseAfterLastDef(RegB, Dist, LastDefB))

703 return true;

704

705

706

707

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710

711

712

713

714

715

716

717

718

719

721 return true;

722

724 return false;

725

726

727 bool Commute;

728 if (TII->hasCommutePreference(*MI, Commute))

729 return Commute;

730

731

732

733 return LastDefB && LastDefC && LastDefC > LastDefB;

734}

735

736

737

738bool TwoAddressInstructionImpl::commuteInstruction(MachineInstr *MI,

739 unsigned DstIdx,

740 unsigned RegBIdx,

741 unsigned RegCIdx,

742 unsigned Dist) {

743 Register RegC = MI->getOperand(RegCIdx).getReg();

745 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);

746

747 if (NewMI == nullptr) {

749 return false;

750 }

751

752 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);

754 "TargetInstrInfo::commuteInstruction() should not return a new "

755 "instruction unless it was requested.");

756

757

759 if (FromRegC) {

760 Register RegA = MI->getOperand(DstIdx).getReg();

761 SrcRegMap[RegA] = FromRegC;

762 }

763

764 return true;

765}

766

767

768

769bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,

771

772

773

774

775

776

778 if (!FromRegB)

779 return false;

781 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA));

782}

783

784

785

786bool TwoAddressInstructionImpl::convertInstTo3Addr(

790 MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV, LIS);

791 if (!NewMI)

792 return false;

793

794 LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);

795 LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);

796

797

798 if (auto OldInstrNum = mi->peekDebugInstrNum()) {

799 assert(mi->getNumExplicitDefs() == 1);

801

802

803 unsigned OldIdx = mi->defs().begin()->getOperandNo();

804 unsigned NewIdx = NewMI->defs().begin()->getOperandNo();

805

806

809 std::make_pair(NewInstrNum, NewIdx));

810 }

811

812 MBB->erase(mi);

813

815 DistanceMap.insert(std::make_pair(&MI, Dist++));

816 Dist--;

817 mi = NewMI;

818 nmi = std::next(mi);

819

820

821 SrcRegMap.erase(RegA);

822 DstRegMap.erase(RegB);

823 return true;

824}

825

826

827

828void TwoAddressInstructionImpl::scanUses(Register DstReg) {

830 bool IsDstPhys;

831 bool IsCopy = false;

835 findOnlyInterestingUse(Reg, MBB, IsCopy, NewReg, IsDstPhys)) {

836 if (IsCopy && !Processed.insert(UseMI).second)

837 break;

838

840 if (DI != DistanceMap.end())

841

842 break;

843

844 if (IsDstPhys) {

846 break;

847 }

848 SrcRegMap[NewReg] = Reg;

850 Reg = NewReg;

851 }

852

853 if (!VirtRegPairs.empty()) {

854 unsigned ToReg = VirtRegPairs.back();

856 while (!VirtRegPairs.empty()) {

857 unsigned FromReg = VirtRegPairs.pop_back_val();

858 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;

859 if (!isNew)

860 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");

861 ToReg = FromReg;

862 }

863 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;

864 if (!isNew)

865 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");

866 }

867}

868

869

870

871

872

873

874

875

876

877

878

879

880

881void TwoAddressInstructionImpl::processCopy(MachineInstr *MI) {

882 if (Processed.count(MI))

883 return;

884

885 bool IsSrcPhys, IsDstPhys;

887 if (!isCopyToReg(*MI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))

888 return;

889

890 if (IsDstPhys && !IsSrcPhys) {

891 DstRegMap.insert(std::make_pair(SrcReg, DstReg));

892 } else if (!IsDstPhys && IsSrcPhys) {

893 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;

894 if (!isNew)

895 assert(SrcRegMap[DstReg] == SrcReg &&

896 "Can't map to two src physical registers!");

897

898 scanUses(DstReg);

899 }

900

901 Processed.insert(MI);

902}

903

904

905

906

907bool TwoAddressInstructionImpl::rescheduleMIBelowKill(

910

911

912 if (!LV && !LIS)

913 return false;

914

917 if (DI == DistanceMap.end())

918

919 return false;

920

922 if (LIS) {

925 "Reg should not have empty live interval.");

926

927 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();

929 if (I != LI.end() && I->start < MBBEndIdx)

930 return false;

931

932 --I;

933 KillMI = LIS->getInstructionFromIndex(I->end);

934 } else {

935 KillMI = LV->getVarInfo(Reg).findKill(MBB);

936 }

937 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())

938

939 return false;

940

943

944 return false;

945

948 return false;

949

950 bool SeenStore = true;

951 if (->isSafeToMove(SeenStore))

952 return false;

953

955

956 return false;

957

963 continue;

965 if (!MOReg)

966 continue;

969 else {

970 Uses.push_back(MOReg);

971 if (MOReg != Reg && isPlainlyKilled(MO))

973 }

974 }

975

976

982 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg()))

984 else

985 break;

987 }

988

989

990 unsigned NumVisited = 0;

992 ++KillPos;

994

995 if (OtherMI.isDebugOrPseudoInstr())

996 continue;

997 if (NumVisited > 10)

998 return false;

999 ++NumVisited;

1000 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||

1001 OtherMI.isBranch() || OtherMI.isTerminator())

1002

1003 return false;

1004 for (const MachineOperand &MO : OtherMI.operands()) {

1005 if (!MO.isReg())

1006 continue;

1008 if (!MOReg)

1009 continue;

1010 if (MO.isDef()) {

1011 if (regOverlapsSet(Uses, MOReg))

1012

1013 return false;

1014 if (!MO.isDead() && regOverlapsSet(Defs, MOReg))

1015

1016

1017

1018 return false;

1019 } else {

1020 if (regOverlapsSet(Defs, MOReg))

1021 return false;

1022 bool isKill = isPlainlyKilled(MO);

1023 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg)) ||

1024 regOverlapsSet(Kills, MOReg)))

1025

1026 return false;

1027 if (MOReg == Reg && !isKill)

1028

1029 return false;

1030

1031 assert((MOReg != Reg || &OtherMI == KillMI) &&

1032 "Found multiple kills of a register in a basic block");

1033 }

1034 }

1035 }

1036

1037

1038 while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr())

1039 --Begin;

1040

1041 nmi = End;

1043 if (LIS) {

1044

1045

1047 auto CopyMI = MBBI++;

1049 if (!CopyMI->isDebugOrPseudoInstr())

1050 LIS->handleMove(*CopyMI);

1051 InsertPos = CopyMI;

1052 }

1054 }

1055

1056

1058 DistanceMap.erase(DI);

1059

1060

1061 if (LIS) {

1062 LIS->handleMove(*MI);

1063 } else {

1064 LV->removeVirtualRegisterKilled(Reg, *KillMI);

1065 LV->addVirtualRegisterKilled(Reg, *MI);

1066 }

1067

1068 LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);

1069 return true;

1070}

1071

1072

1073

1074bool TwoAddressInstructionImpl::isDefTooClose(Register Reg, unsigned Dist,

1077 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())

1078 continue;

1080 return true;

1082 if (DDI == DistanceMap.end())

1083 return true;

1084 unsigned DefDist = DDI->second;

1085 assert(Dist > DefDist && "Visited def already?");

1087 return true;

1088 }

1089 return false;

1090}

1091

1092

1093

1094

1095bool TwoAddressInstructionImpl::rescheduleKillAboveMI(

1098

1099

1100 if (!LV && !LIS)

1101 return false;

1102

1105 if (DI == DistanceMap.end())

1106

1107 return false;

1108

1110 if (LIS) {

1113 "Reg should not have empty live interval.");

1114

1115 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();

1117 if (I != LI.end() && I->start < MBBEndIdx)

1118 return false;

1119

1120 --I;

1121 KillMI = LIS->getInstructionFromIndex(I->end);

1122 } else {

1123 KillMI = LV->getVarInfo(Reg).findKill(MBB);

1124 }

1125 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())

1126

1127 return false;

1128

1131 return false;

1132

1133 bool SeenStore = true;

1135 return false;

1136

1142 if (!MO.isReg())

1143 continue;

1145 if (MO.isUse()) {

1146 if (!MOReg)

1147 continue;

1148 if (isDefTooClose(MOReg, DI->second, MI))

1149 return false;

1150 bool isKill = isPlainlyKilled(MO);

1151 if (MOReg == Reg && !isKill)

1152 return false;

1153 Uses.push_back(MOReg);

1154 if (isKill && MOReg != Reg)

1160 }

1161 }

1162

1163

1164 unsigned NumVisited = 0;

1167

1168 if (OtherMI.isDebugOrPseudoInstr())

1169 continue;

1170 if (NumVisited > 10)

1171 return false;

1172 ++NumVisited;

1173 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||

1174 OtherMI.isBranch() || OtherMI.isTerminator())

1175

1176 return false;

1178 for (const MachineOperand &MO : OtherMI.operands()) {

1179 if (!MO.isReg())

1180 continue;

1182 if (!MOReg)

1183 continue;

1184 if (MO.isUse()) {

1185 if (regOverlapsSet(Defs, MOReg))

1186

1187

1188 return false;

1189 if (regOverlapsSet(Kills, MOReg))

1190

1191 return false;

1192 if (&OtherMI != MI && MOReg == Reg && !isPlainlyKilled(MO))

1193

1194 return false;

1195 } else {

1197 }

1198 }

1199

1200 for (Register MOReg : OtherDefs) {

1201 if (regOverlapsSet(Uses, MOReg))

1202 return false;

1203 if (MOReg.isPhysical() && regOverlapsSet(LiveDefs, MOReg))

1204 return false;

1205

1207 }

1208 }

1209

1210

1212 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr())

1213 --InsertPos;

1216 while (std::prev(From)->isDebugInstr())

1219

1220 nmi = std::prev(InsertPos);

1221 DistanceMap.erase(DI);

1222

1223

1224 if (LIS) {

1225 LIS->handleMove(*KillMI);

1226 } else {

1227 LV->removeVirtualRegisterKilled(Reg, *KillMI);

1228 LV->addVirtualRegisterKilled(Reg, *MI);

1229 }

1230

1231 LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);

1232 return true;

1233}

1234

1235

1236

1237

1238

1239

1240

1241

1242

1243

1244

1245

1246

1247bool TwoAddressInstructionImpl::tryInstructionCommute(MachineInstr *MI,

1248 unsigned DstOpIdx,

1249 unsigned BaseOpIdx,

1250 bool BaseOpKilled,

1251 unsigned Dist) {

1252 if (->isCommutable())

1253 return false;

1254

1255 bool MadeChange = false;

1256 Register DstOpReg = MI->getOperand(DstOpIdx).getReg();

1257 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();

1258 unsigned OpsNum = MI->getDesc().getNumOperands();

1259 unsigned OtherOpIdx = MI->getDesc().getNumDefs();

1260 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {

1261

1262

1263

1264

1265 if (OtherOpIdx == BaseOpIdx || ->getOperand(OtherOpIdx).isReg() ||

1266 TII ->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))

1267 continue;

1268

1269 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();

1270 bool AggressiveCommute = false;

1271

1272

1273

1274 bool OtherOpKilled = isKilled(*MI, OtherOpReg, false);

1275 bool DoCommute = !BaseOpKilled && OtherOpKilled;

1276

1277 if (!DoCommute &&

1278 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {

1279 DoCommute = true;

1280 AggressiveCommute = true;

1281 }

1282

1283

1284 if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,

1285 Dist)) {

1286 MadeChange = true;

1287 ++NumCommuted;

1288 if (AggressiveCommute)

1289 ++NumAggrCommuted;

1290

1291

1292

1293

1294

1295 BaseOpReg = OtherOpReg;

1296 BaseOpKilled = OtherOpKilled;

1297

1298

1299 OpsNum = MI->getDesc().getNumOperands();

1300 }

1301 }

1302 return MadeChange;

1303}

1304

1305

1306

1307

1308

1309

1310

1311

1312bool TwoAddressInstructionImpl::tryInstructionTransform(

1314 unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) {

1315 if (OptLevel == CodeGenOptLevel::None)

1316 return false;

1317

1319 Register regA = MI.getOperand(DstIdx).getReg();

1320 Register regB = MI.getOperand(SrcIdx).getReg();

1321

1322 assert(regB.isVirtual() && "cannot make instruction into two-address form");

1323 bool regBKilled = isKilled(MI, regB, true);

1324

1326 scanUses(regA);

1327

1328 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);

1329

1330

1331

1332

1333

1334

1335

1336

1337

1338 if (Commuted && .isConvertibleTo3Addr())

1339 return false;

1340

1341 if (shouldOnlyCommute)

1342 return false;

1343

1344

1345

1346 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {

1347 ++NumReSchedDowns;

1348 return true;

1349 }

1350

1351

1352

1353 if (Commuted) {

1354 regB = MI.getOperand(SrcIdx).getReg();

1355 regBKilled = isKilled(MI, regB, true);

1356 }

1357

1358 if (MI.isConvertibleTo3Addr()) {

1359

1360

1361 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {

1362

1363 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {

1364 ++NumConvertedTo3Addr;

1365 return true;

1366 }

1367 }

1368 }

1369

1370

1371 if (Commuted)

1372 return false;

1373

1374

1375

1377 ++NumReSchedUps;

1378 return true;

1379 }

1380

1381

1382

1383

1384

1385

1386

1387

1388

1389 if (MI.mayLoad() && !regBKilled) {

1390

1391 unsigned LoadRegIndex;

1392 unsigned NewOpc =

1393 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),

1394 true,

1395 false,

1396 &LoadRegIndex);

1397 if (NewOpc != 0) {

1400

1403 TRI->getAllocatableClass(

1404 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));

1407 if ( TII ->unfoldMemoryOperand(*MF, MI, Reg,

1408 true,

1409 false, NewMIs)) {

1411 return false;

1412 }

1414 "Unfolded a load into multiple instructions!");

1415

1416 NewMIs[1]->addRegisterKilled(Reg, TRI);

1417

1418

1419

1422 DistanceMap.insert(std::make_pair(NewMIs[0], Dist++));

1423 DistanceMap.insert(std::make_pair(NewMIs[1], Dist));

1424

1425 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]

1426 << "2addr: NEW INST: " << *NewMIs[1]);

1427

1428

1429 unsigned NewDstIdx =

1430 NewMIs[1]->findRegisterDefOperandIdx(regA, nullptr);

1431 unsigned NewSrcIdx =

1432 NewMIs[1]->findRegisterUseOperandIdx(regB, nullptr);

1434 bool TransformResult =

1435 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);

1436 (void)TransformResult;

1437 assert(!TransformResult &&

1438 "tryInstructionTransform() should return false.");

1439 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {

1440

1441

1442 if (LV) {

1445 if (MO.isUse()) {

1447 if (NewMIs[0]->killsRegister(MO.getReg(), nullptr))

1448 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);

1449 else {

1450 assert(NewMIs[1]->killsRegister(MO.getReg(),

1451 nullptr) &&

1452 "Kill missing after load unfold!");

1453 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);

1454 }

1455 }

1456 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {

1457 if (NewMIs[1]->registerDefIsDead(MO.getReg(),

1458 nullptr))

1459 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);

1460 else {

1461 assert(NewMIs[0]->registerDefIsDead(MO.getReg(),

1462 nullptr) &&

1463 "Dead flag missing after load unfold!");

1464 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);

1465 }

1466 }

1467 }

1468 }

1469 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);

1470 }

1471

1473 if (LIS) {

1477 }

1478

1479 LIS->RemoveMachineInstrFromMaps(MI);

1480 }

1481

1482 MI.eraseFromParent();

1483 DistanceMap.erase(&MI);

1484

1485

1486 if (LIS) {

1489 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);

1490 }

1491

1492 mi = NewMIs[1];

1493 } else {

1494

1495

1496

1498 NewMIs[0]->eraseFromParent();

1499 NewMIs[1]->eraseFromParent();

1500 DistanceMap.erase(NewMIs[0]);

1501 DistanceMap.erase(NewMIs[1]);

1502 Dist--;

1503 }

1504 }

1505 }

1506 }

1507

1508 return false;

1509}

1510

1511

1512

1513

1514bool TwoAddressInstructionImpl::collectTiedOperands(

1516 bool AnyOps = false;

1517 unsigned NumOps = MI->getNumOperands();

1518

1519 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {

1520 unsigned DstIdx = 0;

1521 if (->isRegTiedToDefOperand(SrcIdx, &DstIdx))

1522 continue;

1523 AnyOps = true;

1528

1529 if (SrcReg == DstReg)

1530 continue;

1531

1532 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");

1533

1534

1536

1539 MRI->constrainRegClass(DstReg, RC);

1540 }

1541 SrcMO.setReg(DstReg);

1544 continue;

1545 }

1546 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));

1547 }

1548 return AnyOps;

1549}

1550

1551

1552

1553void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,

1554 TiedPairList &TiedPairs,

1555 unsigned &Dist) {

1556 bool IsEarlyClobber = llvm::any_of(TiedPairs, [MI](auto const &TP) {

1557 return MI->getOperand(TP.second).isEarlyClobber();

1558 });

1559

1560 bool RemovedKillFlag = false;

1561 bool AllUsesCopied = true;

1562 unsigned LastCopiedReg = 0;

1565 unsigned SubRegB = 0;

1566 for (auto &TP : TiedPairs) {

1567 unsigned SrcIdx = TP.first;

1568 unsigned DstIdx = TP.second;

1569

1572

1573

1574

1575 RegB = MI->getOperand(SrcIdx).getReg();

1576 SubRegB = MI->getOperand(SrcIdx).getSubReg();

1577

1578 if (RegA == RegB) {

1579

1580

1581

1582 AllUsesCopied = false;

1583 continue;

1584 }

1585 LastCopiedReg = RegA;

1586

1587 assert(RegB.isVirtual() && "cannot make instruction into two-address form");

1588

1589#ifndef NDEBUG

1590

1591

1592

1593 for (unsigned i = 0; i != MI->getNumOperands(); ++i)

1594 assert(i == DstIdx ||

1595 ->getOperand(i).isReg() ||

1596 MI->getOperand(i).getReg() != RegA);

1597#endif

1598

1599

1601 TII->get(TargetOpcode::COPY), RegA);

1602

1603

1604 MIB.addReg(RegB, 0, SubRegB);

1606 if (SubRegB) {

1608 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),

1609 SubRegB) &&

1610 "tied subregister must be a truncation");

1611

1612 RC = nullptr;

1613 } else {

1614 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))

1615 && "tied subregister must be a truncation");

1616 }

1617 }

1618

1619

1621 --PrevMI;

1622 DistanceMap.insert(std::make_pair(&*PrevMI, Dist));

1623 DistanceMap[MI] = ++Dist;

1624

1625 if (LIS) {

1626 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();

1627

1629 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);

1632 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());

1634 for (auto &S : LI.subranges()) {

1635 VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());

1637 }

1638 } else {

1639 for (MCRegUnit Unit : TRI->regunits(RegA)) {

1640 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) {

1642 LR->getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());

1644 }

1645 }

1646 }

1647 }

1648

1650

1653 "inconsistent operand info for 2-reg pass");

1654 if (isPlainlyKilled(MO)) {

1656 RemovedKillFlag = true;

1657 }

1658

1659

1661 MRI->constrainRegClass(RegA, RC);

1663

1664

1665

1667 }

1668

1669 if (AllUsesCopied) {

1671

1673 if (MO.getReg() == RegB) {

1674 if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {

1675 if (isPlainlyKilled(MO)) {

1677 RemovedKillFlag = true;

1678 }

1679 MO.setReg(LastCopiedReg);

1681 } else {

1682 RemainingUses |= TRI->getSubRegIndexLaneMask(MO.getSubReg());

1683 }

1684 }

1685 }

1686

1687

1688 if (RemovedKillFlag && RemainingUses.none() && LV &&

1689 LV->getVarInfo(RegB).removeKill(*MI)) {

1691 --PrevMI;

1692 LV->addVirtualRegisterKilled(RegB, *PrevMI);

1693 }

1694

1695 if (RemovedKillFlag && RemainingUses.none())

1696 SrcRegMap[LastCopiedReg] = RegB;

1697

1698

1699 if (LIS) {

1700 SlotIndex UseIdx = LIS->getInstructionIndex(*MI);

1703 if (!S)

1704 return true;

1705 if ((LaneMask & RemainingUses).any())

1706 return false;

1708 return false;

1709 S->end = LastCopyIdx;

1710 return true;

1711 };

1712

1714 bool ShrinkLI = true;

1716 ShrinkLI &= Shrink(S, S.LaneMask);

1717 if (ShrinkLI)

1719 }

1720 } else if (RemovedKillFlag) {

1721

1722

1723

1724

1726 if (MO.getReg() == RegB) {

1728 break;

1729 }

1730 }

1731 }

1732}

1733

1734

1735

1736

1737

1738

1739

1740

1741bool TwoAddressInstructionImpl::processStatepoint(

1743

1744 bool NeedCopy = false;

1745 for (auto &TO : TiedOperands) {

1747 if (TO.second.size() != 1) {

1748 NeedCopy = true;

1749 continue;

1750 }

1751

1752 unsigned SrcIdx = TO.second[0].first;

1753 unsigned DstIdx = TO.second[0].second;

1754

1757

1758 assert(RegB == MI->getOperand(SrcIdx).getReg());

1759

1760 if (RegA == RegB)

1761 continue;

1762

1763

1764

1765

1766

1767

1768 if (LIS) {

1769 const auto &UseLI = LIS->getInterval(RegB);

1770 const auto &DefLI = LIS->getInterval(RegA);

1771 if (DefLI.overlaps(UseLI)) {

1773 << " UseLI overlaps with DefLI\n");

1774 NeedCopy = true;

1775 continue;

1776 }

1777 } else if (LV && LV->getVarInfo(RegB).findKill(MI->getParent()) != MI) {

1778

1779

1780

1782 << " not killed by statepoint\n");

1783 NeedCopy = true;

1784 continue;

1785 }

1786

1787 if ( MRI ->constrainRegClass(RegB, MRI->getRegClass(RegA))) {

1789 << " to register class of " << printReg(RegA, TRI, 0)

1790 << '\n');

1791 NeedCopy = true;

1792 continue;

1793 }

1794 MRI->replaceRegWith(RegA, RegB);

1795

1796 if (LIS) {

1801 for (const VNInfo *VNI : Other.valnos) {

1802 assert(VNI->id == NewVNIs.size() && "assumed");

1804 }

1805 for (auto &S : Other) {

1809 }

1810 LIS->removeInterval(RegA);

1811 }

1812

1813 if (LV) {

1814 if (MI->getOperand(SrcIdx).isKill())

1815 LV->removeVirtualRegisterKilled(RegB, *MI);

1820 for (auto *KillMI : DstInfo.Kills)

1821 LV->addVirtualRegisterKilled(RegB, *KillMI, false);

1822 }

1823 }

1824 return !NeedCopy;

1825}

1826

1827

1828bool TwoAddressInstructionImpl::run() {

1829 bool MadeChange = false;

1830

1831 LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");

1833

1834

1835 MRI->leaveSSA();

1836

1837

1839 .set(MachineFunctionProperties::Property::TiedOpsRewritten);

1840

1841 TiedOperandMap TiedOperands;

1844 unsigned Dist = 0;

1845 DistanceMap.clear();

1846 SrcRegMap.clear();

1847 DstRegMap.clear();

1848 Processed.clear();

1850 mi != me; ) {

1852

1853 if (mi->isDebugInstr()) {

1854 mi = nmi;

1855 continue;

1856 }

1857

1858

1859

1860 if (mi->isRegSequence())

1861 eliminateRegSequence(mi);

1862

1863 DistanceMap.insert(std::make_pair(&*mi, ++Dist));

1864

1865 processCopy(&*mi);

1866

1867

1868

1869 if (!collectTiedOperands(&*mi, TiedOperands)) {

1870 removeClobberedSrcRegMap(&*mi);

1871 mi = nmi;

1872 continue;

1873 }

1874

1875 ++NumTwoAddressInstrs;

1876 MadeChange = true;

1878

1879

1880

1881

1882 if (TiedOperands.size() == 1) {

1884 = TiedOperands.begin()->second;

1885 if (TiedPairs.size() == 1) {

1886 unsigned SrcIdx = TiedPairs[0].first;

1887 unsigned DstIdx = TiedPairs[0].second;

1888 Register SrcReg = mi->getOperand(SrcIdx).getReg();

1889 Register DstReg = mi->getOperand(DstIdx).getReg();

1890 if (SrcReg != DstReg &&

1891 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {

1892

1893

1894 TiedOperands.clear();

1895 removeClobberedSrcRegMap(&*mi);

1896 mi = nmi;

1897 continue;

1898 }

1899 }

1900 }

1901

1902 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&

1903 processStatepoint(&*mi, TiedOperands)) {

1904 TiedOperands.clear();

1906 mi = nmi;

1907 continue;

1908 }

1909

1910

1911 for (auto &TO : TiedOperands) {

1912 processTiedPairs(&*mi, TO.second, Dist);

1914 }

1915

1916

1917 if (mi->isInsertSubreg()) {

1918

1919

1920 unsigned SubIdx = mi->getOperand(3).getImm();

1921 mi->removeOperand(3);

1922 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");

1923 mi->getOperand(0).setSubReg(SubIdx);

1924 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());

1925 mi->removeOperand(1);

1926 mi->setDesc(TII->get(TargetOpcode::COPY));

1928

1929

1930 if (LIS) {

1931 Register Reg = mi->getOperand(0).getReg();

1934

1935

1937 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg());

1938 SlotIndex Idx = LIS->getInstructionIndex(*mi).getRegSlot();

1939 for (auto &S : LI.subranges()) {

1940 if ((S.LaneMask & LaneMask).none()) {

1942 if (mi->getOperand(0).isUndef()) {

1943 S.removeValNo(DefSeg->valno);

1944 } else {

1946 S.MergeValueNumberInto(DefSeg->valno, UseSeg->valno);

1947 }

1948 }

1949 }

1950

1951

1952 LIS->shrinkToUses(&LI);

1953 } else {

1954

1955

1956 LIS->removeInterval(Reg);

1957 LIS->createAndComputeVirtRegInterval(Reg);

1958 }

1959 }

1960 }

1961

1962

1963

1964 TiedOperands.clear();

1965 removeClobberedSrcRegMap(&*mi);

1966 mi = nmi;

1967 }

1968 }

1969

1970 return MadeChange;

1971}

1972

1973

1974

1975

1976

1977

1978

1979

1980

1981

1982

1983void TwoAddressInstructionImpl::eliminateRegSequence(

1986 Register DstReg = MI.getOperand(0).getReg();

1987

1989 VNInfo *DefVN = nullptr;

1990 if (LIS) {

1991 OrigRegs.push_back(MI.getOperand(0).getReg());

1992 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)

1993 OrigRegs.push_back(MI.getOperand(i).getReg());

1994 if (LIS->hasInterval(DstReg)) {

1995 DefVN = LIS->getInterval(DstReg)

1996 .Query(LIS->getInstructionIndex(MI))

1997 .valueOut();

1998 }

1999 }

2000

2002 bool DefEmitted = false;

2003 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {

2006 unsigned SubIdx = MI.getOperand(i+1).getImm();

2007

2009 UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);

2010 continue;

2011 }

2012

2013

2014

2015 bool isKill = UseMO.isKill();

2016 if (isKill)

2017 for (unsigned j = i + 2; j < e; j += 2)

2018 if (MI.getOperand(j).getReg() == SrcReg) {

2019 MI.getOperand(j).setIsKill();

2021 isKill = false;

2022 break;

2023 }

2024

2025

2027 TII->get(TargetOpcode::COPY))

2029 .add(UseMO);

2030

2031

2032

2033 if (!DefEmitted) {

2035

2036 MBBI = CopyMI;

2037 }

2038 DefEmitted = true;

2039

2040

2041 if (LV && isKill && !SrcReg.isPhysical())

2042 LV->replaceKillInstruction(SrcReg, MI, *CopyMI);

2043

2045 }

2046

2049

2050 if (!DefEmitted) {

2051 LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");

2052 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));

2053 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)

2054 MI.removeOperand(j);

2055 } else {

2056 if (LIS) {

2057

2058

2059

2060 if (UndefLanes.any() && DefVN && MRI->shouldTrackSubRegLiveness(DstReg)) {

2061 auto &LI = LIS->getInterval(DstReg);

2065 continue;

2066 auto *VN =

2068 if (DefVN != VN)

2069 continue;

2071 if ((UndefLanes & LaneMask).any())

2073 }

2074 LIS->removeInterval(DstReg);

2075 }

2076 LIS->RemoveMachineInstrFromMaps(MI);

2077 }

2078

2080 MI.eraseFromParent();

2081 }

2082

2083

2084 if (LIS)

2085 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);

2086}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator MBBI

BlockVerifier::State From

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

This file defines the DenseMap class.

std::optional< std::vector< StOtherPiece > > Other

global merge Global merge function pass

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

FunctionAnalysisManager FAM

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

Remove Loads Into Fake Uses

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg)

Return true if the specified MI uses the specified register as a two-address use.

static MCRegister getMappedReg(Register Reg, DenseMap< Register, Register > &RegMap)

Return the physical register the specified virtual register might be mapped to.

static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)

static cl::opt< unsigned > MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))

A manager for alias analyses.

A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.

A container for analyses that lazily runs them and caches their results.

PassT::Result * getCachedResult(IRUnitT &IR) const

Get the cached result of an analysis pass for a given IR unit.

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addUsedIfAvailable()

Add the specified Pass class to the set of analyses used by this pass.

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

void setPreservesCFG()

This function should be called by the pass, iff they do not:

Allocate memory in an ever growing pool, as if by bump-pointer.

Represents analyses that only rely on functions' control flow.

iterator find(const_arg_type_t< KeyT > Val)

bool skipFunction(const Function &F) const

Optional passes call this function to check whether the pass should be skipped.

bool hasOptNone() const

Do not optimize this function (-O0).

unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override

Compute the instruction latency of a given instruction.

Itinerary data supplied by a subtarget to be used by a target.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

This class represents the liveness of a register, stack slot, etc.

iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

VNInfo * createValueCopy(const VNInfo *orig, VNInfo::Allocator &VNInfoAllocator)

Create a copy of the given value.

bool hasAtLeastOneValue() const

VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)

getNextValue - Create a new value number and return it.

VNInfo * getVNInfoAt(SlotIndex Idx) const

getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.

iterator find(SlotIndex Pos)

find - Return an iterator pointing to the first segment that ends after Pos, or end().

Describe properties that are true of each instruction in the target description file.

unsigned getNumDefs() const

Return the number of MachineOperands that are register definitions.

Wrapper class representing physical registers. Should be passed by value.

An RAII based helper class to modify MachineFunctionProperties when running pass.

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

MachineFunctionProperties & set(Property P)

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)

Create a substitution between one <instr,operand> value to a different, new value.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...

Representation of each machine instruction.

bool isTerminator(QueryType Type=AnyInBundle) const

Returns true if this instruction part of the terminator for a basic block.

bool isCopyLike() const

Return true if the instruction behaves like a copy.

bool isCall(QueryType Type=AnyInBundle) const

bool isSafeToMove(bool &SawStore) const

Return true if it is safe to move this instruction.

bool isBranch(QueryType Type=AnyInBundle) const

Returns true if this is a conditional, unconditional, or indirect branch.

bool hasUnmodeledSideEffects() const

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...

unsigned getNumExplicitDefs() const

Returns the number of non-implicit definitions.

iterator_range< mop_iterator > operands()

iterator_range< mop_iterator > defs()

Returns a range over all explicit operands that are register definitions.

unsigned getDebugInstrNum()

Fetch the instruction number of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

Analysis pass that exposes the MachineLoopInfo for a machine function.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsKill(bool Val=true)

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

void setIsUndef(bool Val=true)

getReg - Returns the register number.

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

SlotIndex - An opaque wrapper around machine indexes.

static bool isSameInstr(SlotIndex A, SlotIndex B)

isSameInstr - Return true if A and B refer to the same instruction.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

iterator erase(const_iterator CI)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

static const unsigned CommuteAnyOperandIndex

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

VNInfo - Value Number Information.

unsigned id

The ID number of this value.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

constexpr bool any(E Val)

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Define

Reg

All possible values of the reg field in the ModR/M byte.

initializer< Ty > init(const Ty &Val)

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

NodeAddr< DefNode * > Def

NodeAddr< FuncNode * > Func

This is an optimization pass for GlobalISel generic memory operations.

void initializeTwoAddressInstructionLegacyPassPass(PassRegistry &)

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It until it points to a non-debug instruction or to End and return the resulting iterator.

void erase(Container &C, ValueType V)

Wrapper function to remove a value from a container:

char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

CodeGenOptLevel

Code generation optimization level.

char & TwoAddressInstructionPassID

TwoAddressInstruction - This pass reduces two-address instructions to use two operands.

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

static constexpr LaneBitmask getAll()

constexpr bool none() const

constexpr bool any() const

static constexpr LaneBitmask getNone()

This represents a simple continuous liveness interval for a value.

VarInfo - This represents the regions where a virtual register is live in the program.

std::vector< MachineInstr * > Kills

Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...

SparseBitVector AliveBlocks

AliveBlocks - Set of blocks in which this value is alive completely through.