TwoAddressInstructionPass.cpp Source File (original) (raw)

62#include

63#include

64#include

66using namespace llvm;

68#define DEBUG_TYPE "twoaddressinstruction"

70 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");

71 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");

72 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");

73 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");

74 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");

75 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");

80 cl::desc("Coalesce copies by rescheduling (default=true)"),

87 cl::desc("Maximum number of dataflow edges to traverse when evaluating "

88 "the benefit of commuting operands"));

90namespace {

92class TwoAddressInstructionImpl {

102

103

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106

108

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111

112

113

114

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117

118

119

121

123

124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);

125

126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);

127

129 bool &IsSrcPhys, bool &IsDstPhys) const;

130

133 bool isPlainlyKilled(const MachineOperand &MO) const;

134

136

138 bool &IsCopy, Register &DstReg,

139 bool &IsDstPhys) const;

140

142

145

147

149

152

153 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,

154 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);

155

157

160 Register RegB, unsigned &Dist);

161

163

168

171 unsigned SrcIdx, unsigned DstIdx,

172 unsigned &Dist, bool shouldOnlyCommute);

173

175 unsigned DstOpIdx,

176 unsigned BaseOpIdx,

177 bool BaseOpKilled,

178 unsigned Dist);

179 void scanUses(Register DstReg);

180

182

185

186 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);

187 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);

189 bool processStatepoint(MachineInstr *MI, TiedOperandMap &TiedOperands);

190

191public:

195 void setOptLevel(CodeGenOptLevel Level) { OptLevel = Level; }

196 bool run();

197};

198

200public:

201 static char ID;

202

203 TwoAddressInstructionLegacyPass() : MachineFunctionPass(ID) {

206 }

207

208

209 bool runOnMachineFunction(MachineFunction &MF) override {

210 TwoAddressInstructionImpl Impl(MF, this);

211

212

214 Impl.setOptLevel(CodeGenOptLevel::None);

215 return Impl.run();

216 }

217

218 void getAnalysisUsage(AnalysisUsage &AU) const override {

228 }

229};

230

231}

232

236

237

238 TwoAddressInstructionImpl Impl(MF, MFAM);

241

243 bool Changed = Impl.run();

253 return PA;

254}

255

256char TwoAddressInstructionLegacyPass::ID = 0;

257

259

261 "Two-Address instruction pass", false, false)

265

266TwoAddressInstructionImpl::TwoAddressInstructionImpl(

268 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),

269 TRI(Func.getSubtarget().getRegisterInfo()),

270 InstrItins(Func.getSubtarget().getInstrItineraryData()),

271 MRI(&Func.getRegInfo()),

274 OptLevel(Func.getTarget().getOptLevel()) {

276 .getManager();

277 AA = FAM.getCachedResult<AAManager>(Func.getFunction());

278}

279

280TwoAddressInstructionImpl::TwoAddressInstructionImpl(MachineFunction &Func,

282 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),

283 TRI(Func.getSubtarget().getRegisterInfo()),

284 InstrItins(Func.getSubtarget().getInstrItineraryData()),

285 MRI(&Func.getRegInfo()), OptLevel(Func.getTarget().getOptLevel()) {

287 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;

289 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;

291 AA = &AAPass->getAAResults();

292 else

293 AA = nullptr;

294}

295

296

298TwoAddressInstructionImpl::getSingleDef(Register Reg,

300 MachineInstr *Ret = nullptr;

301 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {

302 if (DefMI.getParent() != BB || DefMI.isDebugValue())

303 continue;

304 if (!Ret)

306 else if (Ret != &DefMI)

307 return nullptr;

308 }

309 return Ret;

310}

311

312

313

314

315

316

317

318

319bool TwoAddressInstructionImpl::isRevCopyChain(Register FromReg, Register ToReg,

320 int Maxlen) {

322 for (int i = 0; i < Maxlen; i++) {

323 MachineInstr *Def = getSingleDef(TmpReg, MBB);

324 if (!Def || Def ->isCopy())

325 return false;

326

327 TmpReg = Def->getOperand(1).getReg();

328

329 if (TmpReg == ToReg)

330 return true;

331 }

332 return false;

333}

334

335

336

337

338

339bool TwoAddressInstructionImpl::noUseAfterLastDef(Register Reg, unsigned Dist,

340 unsigned &LastDef) {

341 LastDef = 0;

342 unsigned LastUse = Dist;

343 for (MachineOperand &MO : MRI->reg_operands(Reg)) {

344 MachineInstr *MI = MO.getParent();

345 if (MI->getParent() != MBB || MI->isDebugValue())

346 continue;

347 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);

348 if (DI == DistanceMap.end())

349 continue;

350 if (MO.isUse() && DI->second < LastUse)

351 LastUse = DI->second;

352 if (MO.isDef() && DI->second > LastDef)

353 LastDef = DI->second;

354 }

355

356 return !(LastUse > LastDef && LastUse < Dist);

357}

358

359

360

361

362bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg,

363 Register &DstReg, bool &IsSrcPhys,

364 bool &IsDstPhys) const {

365 SrcReg = 0;

366 DstReg = 0;

367 if (MI.isCopy()) {

368 DstReg = MI.getOperand(0).getReg();

369 SrcReg = MI.getOperand(1).getReg();

370 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {

371 DstReg = MI.getOperand(0).getReg();

372 SrcReg = MI.getOperand(2).getReg();

373 } else {

374 return false;

375 }

376

379 return true;

380}

381

382bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,

384

386 return false;

387

389 LiveInterval::const_iterator I = LR.find(useIdx);

390 assert(I != LR.end() && "Reg must be live-in to use.");

392}

393

394

395

396bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,

398

399

400

401

402

403

407

408 if (MRI->isReserved(Reg))

409 return false;

410 return all_of(TRI->regunits(Reg), [&](MCRegUnit U) {

411 return isPlainlyKilled(MI, LIS->getRegUnit(U));

412 });

413 }

414

415 return MI->killsRegister(Reg, nullptr);

416}

417

418

419

420bool TwoAddressInstructionImpl::isPlainlyKilled(

421 const MachineOperand &MO) const {

423}

424

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428

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440

441

442bool TwoAddressInstructionImpl::isKilled(MachineInstr &MI, Register Reg,

443 bool allowFalsePositives) const {

444 MachineInstr *DefMI = &MI;

445 while (true) {

446

448 return true;

449 if (!isPlainlyKilled(DefMI, Reg))

450 return false;

452 return true;

454

455

456 if (std::next(Begin) != MRI->def_end())

457 return true;

459 bool IsSrcPhys, IsDstPhys;

461

462

463 if (!isCopyToReg(*DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))

464 return true;

465 Reg = SrcReg;

466 }

467}

468

469

470

472 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {

475 continue;

476 unsigned ti;

477 if (MI.isRegTiedToDefOperand(i, &ti)) {

478 DstReg = MI.getOperand(ti).getReg();

479 return true;

480 }

481 }

482 return false;

483}

484

485

486

487MachineInstr *TwoAddressInstructionImpl::findOnlyInterestingUse(

489 bool &IsDstPhys) const {

490 MachineOperand *UseOp = nullptr;

491 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {

493 continue;

494

496 if (MI->getParent() != MBB)

497 return nullptr;

498 if (isPlainlyKilled(MI, Reg))

499 UseOp = &MO;

500 }

501 if (!UseOp)

502 return nullptr;

504

506 bool IsSrcPhys;

507 if (isCopyToReg(UseMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {

508 IsCopy = true;

510 }

511 IsDstPhys = false;

515 }

516 if (UseMI.isCommutable()) {

520 MachineOperand &MO = UseMI.getOperand(Src1);

525 }

526 }

527 }

528 return nullptr;

529}

530

531

532

535 while (Reg.isVirtual()) {

537 if (SI == RegMap.end())

538 return 0;

539 Reg = SI->second;

540 }

541 if (Reg.isPhysical())

542 return Reg;

543 return 0;

544}

545

546

547bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,

549 if (RegA == RegB)

550 return true;

551 if (!RegA || !RegB)

552 return false;

553 return TRI->regsOverlap(RegA, RegB);

554}

555

556

557void TwoAddressInstructionImpl::removeMapRegEntry(

558 const MachineOperand &MO, DenseMap<Register, Register> &RegMap) const {

561 "removeMapRegEntry must be called with a register or regmask operand.");

562

564 for (auto SI : RegMap) {

567 continue;

568

569 if (MO.isReg()) {

571 if (TRI->regsOverlap(ToReg, Reg))

575 }

576

577 for (auto SrcReg : Srcs)

578 RegMap.erase(SrcReg);

579}

580

581

582

583

584

585

586

587

588

589void TwoAddressInstructionImpl::removeClobberedSrcRegMap(MachineInstr *MI) {

590 if (MI->isCopy()) {

591

592

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595

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597

598

599

600

601 Register Dst = MI->getOperand(0).getReg();

602 if (!Dst || Dst.isVirtual())

603 return;

604

605 Register Src = MI->getOperand(1).getReg();

606 if (regsAreCompatible(Dst, getMappedReg(Src, SrcRegMap)))

607 return;

608 }

609

610 for (const MachineOperand &MO : MI->operands()) {

612 removeMapRegEntry(MO, SrcRegMap);

613 continue;

614 }

616 continue;

619 continue;

620 removeMapRegEntry(MO, SrcRegMap);

621 }

622}

623

624

625bool TwoAddressInstructionImpl::regOverlapsSet(

626 const SmallVectorImpl &Set, Register Reg) const {

628 if (TRI->regsOverlap(R, Reg))

629 return true;

630

631 return false;

632}

633

634

635

636bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA,

639 MachineInstr *MI,

640 unsigned Dist) {

641 if (OptLevel == CodeGenOptLevel::None)

642 return false;

643

644

645

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649

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660

661

662 if (!isPlainlyKilled(MI, RegC))

663 return false;

664

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672

673

674

675 MCRegister ToRegA = getMappedReg(RegA, DstRegMap);

676 if (ToRegA) {

677 MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);

678 MCRegister FromRegC = getMappedReg(RegC, SrcRegMap);

679 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA);

680 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA);

681

682

683

684

685

686 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))

687 return true;

688

689

690

691

692 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))

693 return false;

694 }

695

696

697

698 unsigned LastDefC = 0;

699 if (!noUseAfterLastDef(RegC, Dist, LastDefC))

700 return false;

701

702

703

704 unsigned LastDefB = 0;

705 if (!noUseAfterLastDef(RegB, Dist, LastDefB))

706 return true;

707

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711

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718

719

720

721

722

724 return true;

725

727 return false;

728

729

730 bool Commute;

732 return Commute;

733

734

735

736 return LastDefB && LastDefC && LastDefC > LastDefB;

737}

738

739

740

741bool TwoAddressInstructionImpl::commuteInstruction(MachineInstr *MI,

742 unsigned DstIdx,

743 unsigned RegBIdx,

744 unsigned RegCIdx,

745 unsigned Dist) {

746 Register RegC = MI->getOperand(RegCIdx).getReg();

749

750 if (NewMI == nullptr) {

752 return false;

753 }

754

755 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);

757 "TargetInstrInfo::commuteInstruction() should not return a new "

758 "instruction unless it was requested.");

759

760

761 MCRegister FromRegC = getMappedReg(RegC, SrcRegMap);

762 if (FromRegC) {

763 Register RegA = MI->getOperand(DstIdx).getReg();

764 SrcRegMap[RegA] = FromRegC;

765 }

766

767 return true;

768}

769

770

771

772bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,

774

775

776

777

778

779

780 MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);

781 if (!FromRegB)

782 return false;

783 MCRegister ToRegA = getMappedReg(RegA, DstRegMap);

784 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA));

785}

786

787

788

789bool TwoAddressInstructionImpl::convertInstTo3Addr(

792 MachineInstrSpan MIS(mi, MBB);

794 if (!NewMI)

795 return false;

796

797 for (MachineInstr &MI : MIS)

798 DistanceMap.insert(std::make_pair(&MI, Dist++));

799

800 if (&*mi == NewMI) {

801 LLVM_DEBUG(dbgs() << "2addr: CONVERTED IN-PLACE TO 3-ADDR: " << *mi);

802 } else {

804 dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi;

805 dbgs() << "2addr: TO 3-ADDR: " << *NewMI;

806 });

807

808

809 if (auto OldInstrNum = mi->peekDebugInstrNum()) {

810 assert(mi->getNumExplicitDefs() == 1);

812

813

814 unsigned OldIdx = mi->defs().begin()->getOperandNo();

815 unsigned NewIdx = NewMI->defs().begin()->getOperandNo();

816

817

820 std::make_pair(NewInstrNum, NewIdx));

821 }

822

823 MBB->erase(mi);

824 Dist--;

825 }

826

827 mi = NewMI;

828 nmi = std::next(mi);

829

830

831 SrcRegMap.erase(RegA);

832 DstRegMap.erase(RegB);

833 return true;

834}

835

836

837

838void TwoAddressInstructionImpl::scanUses(Register DstReg) {

840 bool IsDstPhys;

841 bool IsCopy = false;

844 while (MachineInstr *UseMI =

845 findOnlyInterestingUse(Reg, MBB, IsCopy, NewReg, IsDstPhys)) {

846 if (IsCopy && !Processed.insert(UseMI).second)

847 break;

848

849 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);

850 if (DI != DistanceMap.end())

851

852 break;

853

854 if (IsDstPhys) {

856 break;

857 }

858 SrcRegMap[NewReg] = Reg;

860 Reg = NewReg;

861 }

862

863 if (!VirtRegPairs.empty()) {

865 while (!VirtRegPairs.empty()) {

867 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;

868 if (!isNew)

869 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");

870 ToReg = FromReg;

871 }

872 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;

873 if (!isNew)

874 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");

875 }

876}

877

878

879

880

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882

883

884

885

886

887

888

889

890void TwoAddressInstructionImpl::processCopy(MachineInstr *MI) {

891 if (Processed.count(MI))

892 return;

893

894 bool IsSrcPhys, IsDstPhys;

896 if (!isCopyToReg(*MI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))

897 return;

898

899 if (IsDstPhys && !IsSrcPhys) {

900 DstRegMap.insert(std::make_pair(SrcReg, DstReg));

901 } else if (!IsDstPhys && IsSrcPhys) {

902 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;

903 if (!isNew)

904 assert(SrcRegMap[DstReg] == SrcReg &&

905 "Can't map to two src physical registers!");

906

907 scanUses(DstReg);

908 }

909

910 Processed.insert(MI);

911}

912

913

914

915

916bool TwoAddressInstructionImpl::rescheduleMIBelowKill(

919

920

921 if (!LV && !LIS)

922 return false;

923

924 MachineInstr *MI = &*mi;

925 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);

926 if (DI == DistanceMap.end())

927

928 return false;

929

930 MachineInstr *KillMI = nullptr;

931 if (LIS) {

934 "Reg should not have empty live interval.");

935

937 LiveInterval::const_iterator I = LI.find(MBBEndIdx);

938 if (I != LI.end() && I->start < MBBEndIdx)

939 return false;

940

941 --I;

943 } else {

945 }

946 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())

947

948 return false;

949

952

953 return false;

954

957 return false;

958

959 bool SeenStore = true;

960 if (->isSafeToMove(SeenStore))

961 return false;

962

964

965 return false;

966

970 for (const MachineOperand &MO : MI->operands()) {

972 continue;

974 if (!MOReg)

975 continue;

978 else {

979 Uses.push_back(MOReg);

980 if (MOReg != Reg && isPlainlyKilled(MO))

982 }

983 }

984

985

989 while (End != MBB->end()) {

991 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg()))

992 Defs.push_back(End->getOperand(0).getReg());

993 else

994 break;

995 ++End;

996 }

997

998

999 unsigned NumVisited = 0;

1001 ++KillPos;

1002 for (MachineInstr &OtherMI : make_range(End, KillPos)) {

1003

1004 if (OtherMI.isDebugOrPseudoInstr())

1005 continue;

1006 if (NumVisited > 10)

1007 return false;

1008 ++NumVisited;

1009 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||

1010 OtherMI.isBranch() || OtherMI.isTerminator())

1011

1012 return false;

1013 for (const MachineOperand &MO : OtherMI.operands()) {

1014 if (!MO.isReg())

1015 continue;

1017 if (!MOReg)

1018 continue;

1019 if (MO.isDef()) {

1020 if (regOverlapsSet(Uses, MOReg))

1021

1022 return false;

1023 if (!MO.isDead() && regOverlapsSet(Defs, MOReg))

1024

1025

1026

1027 return false;

1028 } else {

1029 if (regOverlapsSet(Defs, MOReg))

1030 return false;

1031 bool isKill = isPlainlyKilled(MO);

1032 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg)) ||

1033 regOverlapsSet(Kills, MOReg)))

1034

1035 return false;

1036 if (MOReg == Reg && !isKill)

1037

1038 return false;

1039

1040 assert((MOReg != Reg || &OtherMI == KillMI) &&

1041 "Found multiple kills of a register in a basic block");

1042 }

1043 }

1044 }

1045

1046

1047 while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr())

1048 --Begin;

1049

1050 nmi = End;

1052 if (LIS) {

1053

1054

1056 auto CopyMI = MBBI++;

1058 if (!CopyMI->isDebugOrPseudoInstr())

1060 InsertPos = CopyMI;

1061 }

1063 }

1064

1065

1067 DistanceMap.erase(DI);

1068

1069

1070 if (LIS) {

1072 } else {

1075 }

1076

1077 LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);

1078 return true;

1079}

1080

1081

1082

1083bool TwoAddressInstructionImpl::isDefTooClose(Register Reg, unsigned Dist,

1084 MachineInstr *MI) {

1085 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {

1086 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())

1087 continue;

1089 return true;

1090 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);

1091 if (DDI == DistanceMap.end())

1092 return true;

1093 unsigned DefDist = DDI->second;

1094 assert(Dist > DefDist && "Visited def already?");

1096 return true;

1097 }

1098 return false;

1099}

1100

1101

1102

1103

1104bool TwoAddressInstructionImpl::rescheduleKillAboveMI(

1107

1108

1109 if (!LV && !LIS)

1110 return false;

1111

1112 MachineInstr *MI = &*mi;

1113 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);

1114 if (DI == DistanceMap.end())

1115

1116 return false;

1117

1118 MachineInstr *KillMI = nullptr;

1119 if (LIS) {

1122 "Reg should not have empty live interval.");

1123

1125 LiveInterval::const_iterator I = LI.find(MBBEndIdx);

1126 if (I != LI.end() && I->start < MBBEndIdx)

1127 return false;

1128

1129 --I;

1131 } else {

1133 }

1134 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())

1135

1136 return false;

1137

1140 return false;

1141

1142 bool SeenStore = true;

1144 return false;

1145

1150 for (const MachineOperand &MO : KillMI->operands()) {

1151 if (!MO.isReg())

1152 continue;

1154 if (MO.isUse()) {

1155 if (!MOReg)

1156 continue;

1157 if (isDefTooClose(MOReg, DI->second, MI))

1158 return false;

1159 bool isKill = isPlainlyKilled(MO);

1160 if (MOReg == Reg && !isKill)

1161 return false;

1162 Uses.push_back(MOReg);

1163 if (isKill && MOReg != Reg)

1169 }

1170 }

1171

1172

1173 unsigned NumVisited = 0;

1174 for (MachineInstr &OtherMI :

1176

1177 if (OtherMI.isDebugOrPseudoInstr())

1178 continue;

1179 if (NumVisited > 10)

1180 return false;

1181 ++NumVisited;

1182 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||

1183 OtherMI.isBranch() || OtherMI.isTerminator())

1184

1185 return false;

1187 for (const MachineOperand &MO : OtherMI.operands()) {

1188 if (!MO.isReg())

1189 continue;

1191 if (!MOReg)

1192 continue;

1193 if (MO.isUse()) {

1194 if (regOverlapsSet(Defs, MOReg))

1195

1196

1197 return false;

1198 if (regOverlapsSet(Kills, MOReg))

1199

1200 return false;

1201 if (&OtherMI != MI && MOReg == Reg && !isPlainlyKilled(MO))

1202

1203 return false;

1204 } else {

1206 }

1207 }

1208

1209 for (Register MOReg : OtherDefs) {

1210 if (regOverlapsSet(Uses, MOReg))

1211 return false;

1212 if (MOReg.isPhysical() && regOverlapsSet(LiveDefs, MOReg))

1213 return false;

1214

1216 }

1217 }

1218

1219

1221 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr())

1222 --InsertPos;

1225 while (std::prev(From)->isDebugInstr())

1226 --From;

1228

1229 nmi = std::prev(InsertPos);

1230 DistanceMap.erase(DI);

1231

1232

1233 if (LIS) {

1235 } else {

1238 }

1239

1240 LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);

1241 return true;

1242}

1243

1244

1245

1246

1247

1248

1249

1250

1251

1252

1253

1254

1255

1256bool TwoAddressInstructionImpl::tryInstructionCommute(MachineInstr *MI,

1257 unsigned DstOpIdx,

1258 unsigned BaseOpIdx,

1259 bool BaseOpKilled,

1260 unsigned Dist) {

1261 if (->isCommutable())

1262 return false;

1263

1264 bool MadeChange = false;

1265 Register DstOpReg = MI->getOperand(DstOpIdx).getReg();

1266 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();

1267 unsigned OpsNum = MI->getDesc().getNumOperands();

1268 unsigned OtherOpIdx = MI->getDesc().getNumDefs();

1269 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {

1270

1271

1272

1273

1274 if (OtherOpIdx == BaseOpIdx || ->getOperand(OtherOpIdx).isReg() ||

1276 continue;

1277

1278 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();

1279 bool AggressiveCommute = false;

1280

1281

1282

1283 bool OtherOpKilled = isKilled(*MI, OtherOpReg, false);

1284 bool DoCommute = !BaseOpKilled && OtherOpKilled;

1285

1286 if (!DoCommute &&

1287 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {

1288 DoCommute = true;

1289 AggressiveCommute = true;

1290 }

1291

1292

1293 if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,

1294 Dist)) {

1295 MadeChange = true;

1296 ++NumCommuted;

1297 if (AggressiveCommute)

1298 ++NumAggrCommuted;

1299

1300

1301

1302

1303

1304 BaseOpReg = OtherOpReg;

1305 BaseOpKilled = OtherOpKilled;

1306

1307

1308 OpsNum = MI->getDesc().getNumOperands();

1309 }

1310 }

1311 return MadeChange;

1312}

1313

1314

1315

1316

1317

1318

1319

1320

1321bool TwoAddressInstructionImpl::tryInstructionTransform(

1323 unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) {

1324 if (OptLevel == CodeGenOptLevel::None)

1325 return false;

1326

1327 MachineInstr &MI = *mi;

1328 Register regA = MI.getOperand(DstIdx).getReg();

1329 Register regB = MI.getOperand(SrcIdx).getReg();

1330

1331 assert(regB.isVirtual() && "cannot make instruction into two-address form");

1332 bool regBKilled = isKilled(MI, regB, true);

1333

1335 scanUses(regA);

1336

1337 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);

1338

1339

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350 if (Commuted && !ConvertibleTo3Addr)

1351 return false;

1352

1353 if (shouldOnlyCommute)

1354 return false;

1355

1356

1357

1358 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {

1359 ++NumReSchedDowns;

1360 return true;

1361 }

1362

1363

1364

1365 if (Commuted) {

1366 regB = MI.getOperand(SrcIdx).getReg();

1367 regBKilled = isKilled(MI, regB, true);

1368 }

1369

1370 if (ConvertibleTo3Addr) {

1371

1372

1373 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {

1374

1375 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {

1376 ++NumConvertedTo3Addr;

1377 return true;

1378 }

1379 }

1380 }

1381

1382

1383 if (Commuted)

1384 return false;

1385

1386

1387

1389 ++NumReSchedUps;

1390 return true;

1391 }

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401 if (MI.mayLoad() && !regBKilled) {

1402

1403 unsigned LoadRegIndex;

1404 unsigned NewOpc =

1406 true,

1407 false,

1408 &LoadRegIndex);

1409 if (NewOpc != 0) {

1410 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);

1412

1414 const TargetRegisterClass *RC = TRI->getAllocatableClass(

1417 SmallVector<MachineInstr *, 2> NewMIs;

1419 true,

1420 false, NewMIs)) {

1422 return false;

1423 }

1425 "Unfolded a load into multiple instructions!");

1426

1427 NewMIs[1]->addRegisterKilled(Reg, TRI);

1428

1429

1430

1433 DistanceMap.insert(std::make_pair(NewMIs[0], Dist++));

1434 DistanceMap.insert(std::make_pair(NewMIs[1], Dist));

1435

1436 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]

1437 << "2addr: NEW INST: " << *NewMIs[1]);

1438

1439

1440 unsigned NewDstIdx =

1441 NewMIs[1]->findRegisterDefOperandIdx(regA, nullptr);

1442 unsigned NewSrcIdx =

1443 NewMIs[1]->findRegisterUseOperandIdx(regB, nullptr);

1445 bool TransformResult =

1446 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);

1447 (void)TransformResult;

1448 assert(!TransformResult &&

1449 "tryInstructionTransform() should return false.");

1450 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {

1451

1452

1453 if (LV) {

1454 for (const MachineOperand &MO : MI.operands()) {

1456 if (MO.isUse()) {

1458 if (NewMIs[0]->killsRegister(MO.getReg(), nullptr))

1460 else {

1461 assert(NewMIs[1]->killsRegister(MO.getReg(),

1462 nullptr) &&

1463 "Kill missing after load unfold!");

1465 }

1466 }

1468 if (NewMIs[1]->registerDefIsDead(MO.getReg(),

1469 nullptr))

1471 else {

1472 assert(NewMIs[0]->registerDefIsDead(MO.getReg(),

1473 nullptr) &&

1474 "Dead flag missing after load unfold!");

1476 }

1477 }

1478 }

1479 }

1481 }

1482

1484 if (LIS) {

1485 for (const MachineOperand &MO : MI.operands()) {

1488 }

1489

1491 }

1492

1493 MI.eraseFromParent();

1495

1496

1497 if (LIS) {

1501 }

1502

1503 mi = NewMIs[1];

1504 } else {

1505

1506

1507

1509 NewMIs[0]->eraseFromParent();

1510 NewMIs[1]->eraseFromParent();

1511 DistanceMap.erase(NewMIs[0]);

1512 DistanceMap.erase(NewMIs[1]);

1513 Dist--;

1514 }

1515 }

1516 }

1517 }

1518

1519 return false;

1520}

1521

1522

1523

1524

1525bool TwoAddressInstructionImpl::collectTiedOperands(

1526 MachineInstr *MI, TiedOperandMap &TiedOperands) {

1527 bool AnyOps = false;

1528 unsigned NumOps = MI->getNumOperands();

1529

1530 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {

1531 unsigned DstIdx = 0;

1532 if (->isRegTiedToDefOperand(SrcIdx, &DstIdx))

1533 continue;

1534 AnyOps = true;

1535 MachineOperand &SrcMO = MI->getOperand(SrcIdx);

1536 MachineOperand &DstMO = MI->getOperand(DstIdx);

1539

1540 if (SrcReg == DstReg)

1541 continue;

1542

1543 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");

1544

1545

1547

1549 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);

1550 MRI->constrainRegClass(DstReg, RC);

1551 }

1552 SrcMO.setReg(DstReg);

1555 continue;

1556 }

1557 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));

1558 }

1559 return AnyOps;

1560}

1561

1562

1563

1564void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,

1565 TiedPairList &TiedPairs,

1566 unsigned &Dist) {

1567 bool IsEarlyClobber = llvm::any_of(TiedPairs, [MI](auto const &TP) {

1568 return MI->getOperand(TP.second).isEarlyClobber();

1569 });

1570

1571 bool RemovedKillFlag = false;

1572 bool AllUsesCopied = true;

1574 SlotIndex LastCopyIdx;

1576 unsigned SubRegB = 0;

1577 for (auto &TP : TiedPairs) {

1578 unsigned SrcIdx = TP.first;

1579 unsigned DstIdx = TP.second;

1580

1581 const MachineOperand &DstMO = MI->getOperand(DstIdx);

1583

1584

1585

1586 RegB = MI->getOperand(SrcIdx).getReg();

1587 SubRegB = MI->getOperand(SrcIdx).getSubReg();

1588

1589 if (RegA == RegB) {

1590

1591

1592

1593 AllUsesCopied = false;

1594 continue;

1595 }

1596 LastCopiedReg = RegA;

1597

1598 assert(RegB.isVirtual() && "cannot make instruction into two-address form");

1599

1600#ifndef NDEBUG

1601

1602

1603

1604 for (unsigned i = 0; i != MI->getNumOperands(); ++i)

1605 assert(i == DstIdx ||

1606 ->getOperand(i).isReg() ||

1607 MI->getOperand(i).getReg() != RegA);

1608#endif

1609

1610

1611 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),

1612 TII->get(TargetOpcode::COPY), RegA);

1613

1614

1615 MIB.addReg(RegB, 0, SubRegB);

1616 const TargetRegisterClass *RC = MRI->getRegClass(RegB);

1617 if (SubRegB) {

1619 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),

1620 SubRegB) &&

1621 "tied subregister must be a truncation");

1622

1623 RC = nullptr;

1624 } else {

1625 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))

1626 && "tied subregister must be a truncation");

1627 }

1628 }

1629

1630

1632 --PrevMI;

1633 DistanceMap.insert(std::make_pair(&*PrevMI, Dist));

1634 DistanceMap[MI] = ++Dist;

1635

1636 if (LIS) {

1638

1639 SlotIndex endIdx =

1642 LiveInterval &LI = LIS->getInterval(RegA);

1644 LI.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));

1645 for (auto &S : LI.subranges()) {

1647 S.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));

1648 }

1649 } else {

1650 for (MCRegUnit Unit : TRI->regunits(RegA)) {

1652 VNInfo *VNI =

1654 LR->addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));

1655 }

1656 }

1657 }

1658 }

1659

1661

1662 MachineOperand &MO = MI->getOperand(SrcIdx);

1664 "inconsistent operand info for 2-reg pass");

1665 if (isPlainlyKilled(MO)) {

1667 RemovedKillFlag = true;

1668 }

1669

1670

1672 MRI->constrainRegClass(RegA, RC);

1674

1675

1676

1678

1679

1680 if (MI->isBundle()) {

1682 if (MO.isReg() && MO.getReg() == RegB) {

1684 "tied subregister uses in bundled instructions not supported");

1686 }

1687 }

1688 }

1689 }

1690

1691 if (AllUsesCopied) {

1693

1694 for (MachineOperand &MO : MI->all_uses()) {

1695 if (MO.getReg() == RegB) {

1696 if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {

1697 if (isPlainlyKilled(MO)) {

1699 RemovedKillFlag = true;

1700 }

1701 MO.setReg(LastCopiedReg);

1703 } else {

1704 RemainingUses |= TRI->getSubRegIndexLaneMask(MO.getSubReg());

1705 }

1706 }

1707 }

1708

1709

1710 if (RemovedKillFlag && RemainingUses.none() && LV &&

1713 --PrevMI;

1715 }

1716

1717 if (RemovedKillFlag && RemainingUses.none())

1718 SrcRegMap[LastCopiedReg] = RegB;

1719

1720

1721 if (LIS) {

1723 auto Shrink = [=](LiveRange &LR, LaneBitmask LaneMask) {

1725 if (!S)

1726 return true;

1727 if ((LaneMask & RemainingUses).any())

1728 return false;

1730 return false;

1731 S->end = LastCopyIdx;

1732 return true;

1733 };

1734

1735 LiveInterval &LI = LIS->getInterval(RegB);

1736 bool ShrinkLI = true;

1738 ShrinkLI &= Shrink(S, S.LaneMask);

1739 if (ShrinkLI)

1741 }

1742 } else if (RemovedKillFlag) {

1743

1744

1745

1746

1747 for (MachineOperand &MO : MI->all_uses()) {

1748 if (MO.getReg() == RegB) {

1750 break;

1751 }

1752 }

1753 }

1754}

1755

1756

1757

1758

1759

1760

1761

1762

1763bool TwoAddressInstructionImpl::processStatepoint(

1764 MachineInstr *MI, TiedOperandMap &TiedOperands) {

1765

1766 bool NeedCopy = false;

1767 for (auto &TO : TiedOperands) {

1769 if (TO.second.size() != 1) {

1770 NeedCopy = true;

1771 continue;

1772 }

1773

1774 unsigned SrcIdx = TO.second[0].first;

1775 unsigned DstIdx = TO.second[0].second;

1776

1777 MachineOperand &DstMO = MI->getOperand(DstIdx);

1779

1780 assert(RegB == MI->getOperand(SrcIdx).getReg());

1781

1782 if (RegA == RegB)

1783 continue;

1784

1785

1786

1787

1788

1789

1790 if (LIS) {

1791 const auto &UseLI = LIS->getInterval(RegB);

1792 const auto &DefLI = LIS->getInterval(RegA);

1793 if (DefLI.overlaps(UseLI)) {

1795 << " UseLI overlaps with DefLI\n");

1796 NeedCopy = true;

1797 continue;

1798 }

1800

1801

1802

1804 << " not killed by statepoint\n");

1805 NeedCopy = true;

1806 continue;

1807 }

1808

1809 if ( MRI ->constrainRegClass(RegB, MRI->getRegClass(RegA))) {

1811 << " to register class of " << printReg(RegA, TRI, 0)

1812 << '\n');

1813 NeedCopy = true;

1814 continue;

1815 }

1816 MRI->replaceRegWith(RegA, RegB);

1817

1818 if (LIS) {

1820 LiveInterval &LI = LIS->getInterval(RegB);

1823 for (const VNInfo *VNI : Other.valnos) {

1824 assert(VNI->id == NewVNIs.size() && "assumed");

1826 }

1827 for (auto &S : Other) {

1828 VNInfo *VNI = NewVNIs[S.valno->id];

1829 LiveRange::Segment NewSeg(S.start, S.end, VNI);

1831 }

1833 }

1834

1835 if (LV) {

1836 if (MI->getOperand(SrcIdx).isKill())

1838 LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(RegB);

1839 LiveVariables::VarInfo &DstInfo = LV->getVarInfo(RegA);

1842 for (auto *KillMI : DstInfo.Kills)

1844 }

1845 }

1846 return !NeedCopy;

1847}

1848

1849

1850bool TwoAddressInstructionImpl::run() {

1851 bool MadeChange = false;

1852

1853 LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");

1855

1856

1857 MRI->leaveSSA();

1858

1859

1861

1862 TiedOperandMap TiedOperands;

1863 for (MachineBasicBlock &MBBI : *MF) {

1865 unsigned Dist = 0;

1866 DistanceMap.clear();

1867 SrcRegMap.clear();

1868 DstRegMap.clear();

1869 Processed.clear();

1871 mi != me; ) {

1873

1874 if (mi->isDebugInstr()) {

1875 mi = nmi;

1876 continue;

1877 }

1878

1879

1880

1881 if (mi->isRegSequence())

1882 eliminateRegSequence(mi);

1883

1884 DistanceMap.insert(std::make_pair(&*mi, ++Dist));

1885

1886 processCopy(&*mi);

1887

1888

1889

1890 if (!collectTiedOperands(&*mi, TiedOperands)) {

1891 removeClobberedSrcRegMap(&*mi);

1892 mi = nmi;

1893 continue;

1894 }

1895

1896 ++NumTwoAddressInstrs;

1897 MadeChange = true;

1899

1900

1901

1902

1903 if (TiedOperands.size() == 1) {

1904 SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs

1905 = TiedOperands.begin()->second;

1906 if (TiedPairs.size() == 1) {

1907 unsigned SrcIdx = TiedPairs[0].first;

1908 unsigned DstIdx = TiedPairs[0].second;

1909 Register SrcReg = mi->getOperand(SrcIdx).getReg();

1910 Register DstReg = mi->getOperand(DstIdx).getReg();

1911 if (SrcReg != DstReg &&

1912 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {

1913

1914

1915 TiedOperands.clear();

1916 removeClobberedSrcRegMap(&*mi);

1917 mi = nmi;

1918 continue;

1919 }

1920 }

1921 }

1922

1923 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&

1924 processStatepoint(&*mi, TiedOperands)) {

1925 TiedOperands.clear();

1927 mi = nmi;

1928 continue;

1929 }

1930

1931

1932 for (auto &TO : TiedOperands) {

1933 processTiedPairs(&*mi, TO.second, Dist);

1935 }

1936

1937

1938 if (mi->isInsertSubreg()) {

1939

1940

1941 unsigned SubIdx = mi->getOperand(3).getImm();

1942 mi->removeOperand(3);

1943 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");

1944 mi->getOperand(0).setSubReg(SubIdx);

1945 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());

1946 mi->removeOperand(1);

1947 mi->setDesc(TII->get(TargetOpcode::COPY));

1949

1950

1951 if (LIS) {

1952 Register Reg = mi->getOperand(0).getReg();

1955

1956

1957 LaneBitmask LaneMask =

1958 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg());

1960 for (auto &S : LI.subranges()) {

1961 if ((S.LaneMask & LaneMask).none()) {

1962 LiveRange::iterator DefSeg = S.FindSegmentContaining(Idx);

1963 if (mi->getOperand(0).isUndef()) {

1964 S.removeValNo(DefSeg->valno);

1965 } else {

1966 LiveRange::iterator UseSeg = std::prev(DefSeg);

1967 S.MergeValueNumberInto(DefSeg->valno, UseSeg->valno);

1968 }

1969 }

1970 }

1971

1972

1974 } else {

1975

1976

1979 }

1980 }

1981 }

1982

1983

1984

1985 TiedOperands.clear();

1986 removeClobberedSrcRegMap(&*mi);

1987 mi = nmi;

1988 }

1989 }

1990

1991 return MadeChange;

1992}

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004void TwoAddressInstructionImpl::eliminateRegSequence(

2006 MachineInstr &MI = *MBBI;

2007 Register DstReg = MI.getOperand(0).getReg();

2008

2010 VNInfo *DefVN = nullptr;

2011 if (LIS) {

2012 OrigRegs.push_back(MI.getOperand(0).getReg());

2013 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)

2014 OrigRegs.push_back(MI.getOperand(i).getReg());

2019 }

2020 }

2021

2023 bool DefEmitted = false;

2024 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {

2025 MachineOperand &UseMO = MI.getOperand(i);

2027 unsigned SubIdx = MI.getOperand(i+1).getImm();

2028

2030 UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);

2031 continue;

2032 }

2033

2034

2035

2036 bool isKill = UseMO.isKill();

2037 if (isKill)

2038 for (unsigned j = i + 2; j < e; j += 2)

2039 if (MI.getOperand(j).getReg() == SrcReg) {

2040 MI.getOperand(j).setIsKill();

2042 isKill = false;

2043 break;

2044 }

2045

2046

2047 MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),

2048 TII->get(TargetOpcode::COPY))

2050 .add(UseMO);

2051

2052

2053

2054 if (!DefEmitted) {

2056

2057 MBBI = CopyMI;

2058 }

2059 DefEmitted = true;

2060

2061

2062 if (LV && isKill && !SrcReg.isPhysical())

2064

2066 }

2067

2070

2071 if (!DefEmitted) {

2072 LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");

2073 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));

2074 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)

2075 MI.removeOperand(j);

2076 } else {

2077 if (LIS) {

2078

2079

2080

2081 if (UndefLanes.any() && DefVN && MRI->shouldTrackSubRegLiveness(DstReg)) {

2083 for (MachineOperand &UseOp : MRI->use_operands(DstReg)) {

2086 continue;

2087 auto *VN =

2089 if (DefVN != VN)

2090 continue;

2091 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);

2092 if ((UndefLanes & LaneMask).any())

2094 }

2096 }

2098 }

2099

2101 MI.eraseFromParent();

2102 }

2103

2104

2105 if (LIS)

2107}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator MBBI

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

This file defines the DenseMap class.

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

Promote Memory to Register

FunctionAnalysisManager FAM

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

Remove Loads Into Fake Uses

SI Optimize VGPR LiveRange

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg)

Return true if the specified MI uses the specified register as a two-address use.

Definition TwoAddressInstructionPass.cpp:471

static MCRegister getMappedReg(Register Reg, DenseMap< Register, Register > &RegMap)

Return the physical register the specified virtual register might be mapped to.

Definition TwoAddressInstructionPass.cpp:533

static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)

static cl::opt< unsigned > MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))

A manager for alias analyses.

A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addUsedIfAvailable()

Add the specified Pass class to the set of analyses used by this pass.

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

Represents analyses that only rely on functions' control flow.

iterator find(const_arg_type_t< KeyT > Val)

bool erase(const KeyT &Val)

std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)

bool hasOptNone() const

Do not optimize this function (-O0).

Itinerary data supplied by a subtarget to be used by a target.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

LLVM_ABI void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)

Update live intervals for instructions in a range of iterators.

bool hasInterval(Register Reg) const

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction associated with the given index.

SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)

LLVM_ABI void handleMove(MachineInstr &MI, bool UpdateFlags=false)

Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

void RemoveMachineInstrFromMaps(MachineInstr &MI)

VNInfo::Allocator & getVNInfoAllocator()

SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const

Return the last index in the given basic block.

LiveInterval & getInterval(Register Reg)

void removeInterval(Register Reg)

Interval removal.

bool isNotInMIMap(const MachineInstr &Instr) const

Returns true if the specified machine instr has been removed or was never entered in the map.

LiveRange * getCachedRegUnit(MCRegUnit Unit)

Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...

LLVM_ABI bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)

After removing some uses of a register, shrink its live range to just the remaining uses.

LiveInterval & createAndComputeVirtRegInterval(Register Reg)

VNInfo * valueOut() const

Return the value leaving the instruction, if any.

This class represents the liveness of a register, stack slot, etc.

LLVM_ABI iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

VNInfo * createValueCopy(const VNInfo *orig, VNInfo::Allocator &VNInfoAllocator)

Create a copy of the given value.

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

bool hasAtLeastOneValue() const

VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)

getNextValue - Create a new value number and return it.

VNInfo * getVNInfoAt(SlotIndex Idx) const

getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.

LLVM_ABI iterator find(SlotIndex Pos)

find - Return an iterator pointing to the first segment that ends after Pos, or end().

LLVM_ABI void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)

replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.

bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI)

removeVirtualRegisterDead - Remove the specified kill of the virtual register from the live variable ...

bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI)

removeVirtualRegisterKilled - Remove the specified kill of the virtual register from the live variabl...

void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)

addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...

void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)

addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...

LLVM_ABI VarInfo & getVarInfo(Register Reg)

getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.

unsigned getNumDefs() const

Return the number of MachineOperands that are register definitions.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Wrapper class representing physical registers. Should be passed by value.

An RAII based helper class to modify MachineFunctionProperties when running pass.

LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

LLVM_ABI instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)

Create a substitution between one <instr,operand> value to a different, new value.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

mop_range defs()

Returns all explicit operands that are register definitions.

bool isTerminator(QueryType Type=AnyInBundle) const

Returns true if this instruction part of the terminator for a basic block.

bool isCopyLike() const

Return true if the instruction behaves like a copy.

bool isCall(QueryType Type=AnyInBundle) const

LLVM_ABI bool isSafeToMove(bool &SawStore) const

Return true if it is safe to move this instruction.

bool isBranch(QueryType Type=AnyInBundle) const

Returns true if this is a conditional, unconditional, or indirect branch.

LLVM_ABI bool hasUnmodeledSideEffects() const

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...

LLVM_ABI unsigned getNumExplicitDefs() const

Returns the number of non-implicit definitions.

LLVM_ABI unsigned getDebugInstrNum()

Fetch the instruction number of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

Analysis pass that exposes the MachineLoopInfo for a machine function.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

LLVM_ABI unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsKill(bool Val=true)

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

void setIsUndef(bool Val=true)

getReg - Returns the register number.

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

defusechain_iterator< false, true, false, true, false > def_iterator

def_iterator/def_begin/def_end - Walk all defs of the specified register.

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

static bool isSameInstr(SlotIndex A, SlotIndex B)

isSameInstr - Return true if A and B refer to the same instruction.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getPrevSlot() const

Returns the previous slot in the index list.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum) const

Given a machine instruction descriptor, returns the register class constraint for OpNum,...

virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const

Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...

virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const

Returns true iff the routine could find two commutable operands in the given machine instruction.

MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const

This method commutes the operands of the given machine instruction MI.

virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...

virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const

Compute the instruction latency of a given instruction.

virtual MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const

This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const

Returns true if the target has a preference on the operands order of the given machine instruction.

static const unsigned CommuteAnyOperandIndex

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition TwoAddressInstructionPass.cpp:234

BumpPtrAllocator Allocator

unsigned id

The ID number of this value.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

Abstract Attribute helper functions.

constexpr bool any(E Val)

@ Define

initializer< Ty > init(const Ty &Val)

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

NodeAddr< DefNode * > Def

NodeAddr< FuncNode * > Func

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It until it points to a non-debug instruction or to End and return the resulting iterator.

void erase(Container &C, ValueType V)

Wrapper function to remove a value from a container:

LLVM_ABI char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

CodeGenOptLevel

Code generation optimization level.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

iterator_range< MIBundleOperands > mi_bundle_ops(MachineInstr &MI)

LLVM_ABI void initializeTwoAddressInstructionLegacyPassPass(PassRegistry &)

LLVM_ABI char & TwoAddressInstructionPassID

TwoAddressInstruction - This pass reduces two-address instructions to use two operands.

Definition TwoAddressInstructionPass.cpp:258

AAResults AliasAnalysis

Temporary typedef for legacy code that uses a generic AliasAnalysis pointer or reference.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

static constexpr LaneBitmask getAll()

constexpr bool none() const

constexpr bool any() const

static constexpr LaneBitmask getNone()

bool removeKill(MachineInstr &MI)

removeKill - Delete a kill corresponding to the specified machine instruction.

std::vector< MachineInstr * > Kills

Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...

SparseBitVector AliveBlocks

AliveBlocks - Set of blocks in which this value is alive completely through.

LLVM_ABI MachineInstr * findKill(const MachineBasicBlock *MBB) const

findKill - Find a kill instruction in MBB. Return NULL if none is found.