LLVM: lib/Target/VE/VEISelLowering.cpp Source File (original) (raw)
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37using namespace llvm;
38
39#define DEBUG_TYPE "ve-lower"
40
41
42
43
44
45#include "VEGenCallingConv.inc"
46
48 switch (CallConv) {
49 default:
50 return RetCC_VE_C;
52 return RetCC_VE_Fast;
53 }
54}
55
57 if (IsVarArg)
58 return CC_VE2;
59 switch (CallConv) {
60 default:
61 return CC_VE_C;
63 return CC_VE_Fast;
64 }
65}
66
70 const Type *RetTy) const {
73 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
75}
76
77static const MVT AllVectorVTs[] = {MVT::v256i32, MVT::v512i32, MVT::v256i64,
78 MVT::v256f32, MVT::v512f32, MVT::v256f64};
79
80static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};
81
83
84void VETargetLowering::initRegisterClasses() {
85
91
92 if (Subtarget->enableVPU()) {
97 }
98}
99
100void VETargetLowering::initSPUActions() {
102
103
104
110 }
111
112
117 }
118 }
119
120
123
124
125
126
133
134
136
138
141
142
143
146
147
150
151
152
153
154
156
157
159
160
161
162
163 for (MVT IntVT : {MVT::i32, MVT::i64}) {
164
169
170
174
175
176
181
182
186
187
188
189
191
192
193
199
200
201
205
206
209 }
210
211
212
213
218
219
223 }
224
225
226
227
228
229
230
234 }
235
236
238
239 for (MVT FPVT : {MVT::f32, MVT::f64}) {
240
242 }
243
244
245
246
247
256 }
257
258
259 for (MVT VT : {MVT::f32, MVT::f64}) {
261 }
262
263
264
265
266
270
271
273
274
276
278
279
284
285
294 }
295
296
297
298
302
303
304
306}
307
308void VETargetLowering::initVPUActions() {
311
314
319
320
321
322
323
324#define HANDLE_VP_TO_VVP(VP_OPC, VVP_NAME) \
325 setOperationAction(ISD::VP_OPC, LegalVecVT, Custom);
326#define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
327 setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
330#include "VVPNodes.def"
331 }
332
336 }
337
338
340 MVT ElemVT = VT.getVectorElementType();
342 if (ElemBits != 32 && ElemBits != 64)
343 continue;
344
345 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE})
347
349 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND,
350 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN,
351 ISD::VECREDUCE_SMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_UMAX};
352
353 for (unsigned IntRedOpc : IntReductionOCs)
355 }
356
357
359
362 }
363}
364
367 bool IsVarArg,
371
373
374
377
378
380
383
384
385 for (unsigned i = 0; i != RVLocs.size(); ++i) {
387 assert(VA.isRegLoc() && "Can only return in registers!");
389 SDValue OutVal = OutVals[i];
390
391
394 break;
397 break;
400 break;
403 break;
405
406
407
408
409
413 DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
416 MVT::i64, Undef, OutVal, Sub_f32),
417 0);
418 break;
419 }
420 default:
422 }
423
425
426
429 }
430
431 RetOps[0] = Chain;
432
433
436
437 return DAG.getNode(VEISD::RET_GLUE, DL, MVT::Other, RetOps);
438}
439
445
446
447 unsigned ArgsBaseOffset = Subtarget->getRsaSize();
448
449 unsigned ArgsPreserved = 64;
450
451
455
457
458
460
462 assert(!VA.needsCustom() && "Unexpected custom lowering");
463 if (VA.isRegLoc()) {
464
465
466
467
471
472
473
474 switch (VA.getLocInfo()) {
478 break;
482 break;
484
485
486
487
488
489 assert(VA.getLocVT() == MVT::i64);
490 assert(VA.getValVT() == MVT::f32);
493 MVT::f32, Arg, Sub_f32),
494 0);
495 break;
496 }
497 default:
498 break;
499 }
500
501
502 if (VA.isExtInLoc())
504
506 continue;
507 }
508
509
510 assert(VA.isMemLoc());
511
512
513 unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;
514 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
515
516
517
518
519
520
521
522
523
524
525
526 if (VA.getValVT() == MVT::f32)
528
531 DAG.getLoad(VA.getValVT(), DL, Chain,
534 }
535
536 if (!IsVarArg)
537 return Chain;
538
539
540
541
542
543
544
545 unsigned ArgOffset = ArgLocs.size() * 8;
547
549
550 return Chain;
551}
552
553
554
558 .Case("sp", VE::SX11)
559 .Case("fp", VE::SX9)
560 .Case("sl", VE::SX8)
561 .Case("lr", VE::SX10)
562 .Case("tp", VE::SX14)
563 .Case("outer", VE::SX12)
564 .Case("info", VE::SX17)
565 .Case("got", VE::SX15)
566 .Case("plt", VE::SX16)
568 return Reg;
569}
570
571
572
573
574
581
582
584
585
586 unsigned ArgsBaseOffset = Subtarget->getRsaSize();
587
588 unsigned ArgsPreserved = 8 * 8u;
589
590
594
596
597
599
600
601
603
604
608 if (UseBoth)
610
611
613
614
615 ArgsSize = alignTo(ArgsSize, 16);
616
617
618
619
621
622
623
624
626
627
628
629
631
632
633
634
635
636
637
639
641
642
643
647 if (CalleeG)
648 GV = CalleeG->getGlobal();
649 bool Local = TM.shouldAssumeDSOLocal(GV);
650 bool UsePlt = ;
652
653
654
655 if (CalleeG) {
656 if (IsPICCall) {
657 if (UsePlt)
658 Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
660 Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee);
661 } else {
663 }
665 if (IsPICCall) {
666 if (UsePlt)
667 Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
669 Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee);
670 } else {
672 }
673 }
674
675 RegsToPass.push_back(std::make_pair(VE::SX12, Callee));
676
677 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
680
681
683 default:
686 break;
689 break;
692 break;
695 break;
697
698
699
700
701
705 DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
708 MVT::i64, Undef, Arg, Sub_f32),
709 0);
710 break;
711 }
712 }
713
716 if (!UseBoth)
717 continue;
718 VA = ArgLocs2[i];
719 }
720
722
723
725
731 }
732
733
734 if (!MemOpChains.empty())
736
737
738
739
740
742 for (const auto &[Reg, N] : RegsToPass) {
745 }
746
747
749 Ops.push_back(Chain);
750 for (const auto &[Reg, N] : RegsToPass)
752
753
757 assert(Mask && "Missing call preserved mask for calling convention");
759
760
761
763 Ops.push_back(InGlue);
764
765
767 Chain = DAG.getNode(VEISD::CALL, DL, NodeTys, Ops);
769
770
773
774
775
776
777
781
782
783
784 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
785 CLI.Ins[0].Flags.setInReg();
786
788
789
790 for (unsigned i = 0; i != RVLocs.size(); ++i) {
794
795
796
797
802
803
805 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
808 }
809
810
811
816 break;
820 break;
822
823
824
825
826
831 MVT::f32, RV, Sub_f32),
832 0);
833 break;
834 }
835 default:
836 break;
837 }
838
839
842
844 }
845
846 return Chain;
847}
848
851
852
853
854
855 return false;
856}
857
858
859
860
862 bool ForCodeSize) const {
863 return VT == MVT::f32 || VT == MVT::f64;
864}
865
866
867
868
869
870
871
872
873
874
876 unsigned AddrSpace,
879 unsigned *Fast) const {
881
883 }
884 return true;
885}
886
890
891
892
893
894
897
898 initRegisterClasses();
899 initSPUActions();
900 initVPUActions();
901
903
904
908
909
911
912
914
916}
917
919 EVT VT) const {
922 return MVT::i32;
923}
924
925
930 GA->getValueType(0), GA->getOffset(), TF);
931
934 0, TF);
935
938 CP->getAlign(), CP->getOffset(), TF);
939
942 TF);
943
945 return DAG.getTargetJumpTable(JT->getIndex(), JT->getValueType(0), TF);
946
948}
949
950
951
955 EVT VT = Op.getValueType();
959}
960
961
962
965 EVT PtrVT = Op.getValueType();
966
967
970
972 (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
973
974
975
976
981 }
982
983
984
985
986
992 }
993
994
996 default:
1001
1003 }
1004}
1005
1006
1007
1008
1009
1013 switch (Ord) {
1019 return nullptr;
1025 return nullptr;
1027 }
1028 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
1029}
1030
1034 switch (Ord) {
1040 return nullptr;
1046 }
1047 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
1048}
1049
1056 static_cast<SyncScope::ID>(Op.getConstantOperandVal(2));
1057
1058
1059
1061 switch (FenceOrdering) {
1065
1066 break;
1068
1071 Op.getOperand(0)),
1072 0);
1074
1077 Op.getOperand(0)),
1078 0);
1081
1082
1083
1086 Op.getOperand(0)),
1087 0);
1088 }
1089 }
1090
1091
1092 return DAG.getNode(ISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
1093}
1094
1097
1100 }
1101
1102
1103
1104
1106}
1107
1112 SDValue Ptr = N->getOperand(1);
1113 SDValue Val = N->getOperand(2);
1115 bool Byte = N->getMemoryVT() == MVT::i8;
1116
1117
1118
1119
1120
1128}
1129
1133 EVT VT = Data.getValueType();
1135
1136
1137
1138
1141 {NewData, DAG.getConstant(Byte ? 0xff : 0xffff, DL, VT)});
1142}
1143
1148
1149 if (N->getMemoryVT() == MVT::i8) {
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1168
1169 SDValue Ptr = N->getOperand(1);
1172 {Ptr, DAG.getSignedConstant(-4, DL, MVT::i64)});
1174 DAG.getVTList(Op.getNode()->getValueType(0),
1175 Op.getNode()->getValueType(1)),
1176 {N->getChain(), Aligned, Flag, NewVal},
1177 N->getMemOperand());
1178
1182 }
1183 if (N->getMemoryVT() == MVT::i16) {
1184
1188
1189 SDValue Ptr = N->getOperand(1);
1192 {Ptr, DAG.getSignedConstant(-4, DL, MVT::i64)});
1194 DAG.getVTList(Op.getNode()->getValueType(0),
1195 Op.getNode()->getValueType(1)),
1196 {N->getChain(), Aligned, Flag, NewVal},
1197 N->getMemOperand());
1198
1202 }
1203
1204 return Op;
1205}
1206
1211
1216
1221
1226
1227
1228
1229
1230
1231
1233 EVT PtrVT = Op.getValueType();
1234
1235
1236
1239 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1243 Chain = DAG.getNode(VEISD::GETTLSADDR, DL, NodeTys, Args);
1246
1247
1250
1251
1254 Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
1255 }
1256
1257 return Chain;
1258}
1259
1262
1263
1264
1265
1266
1268}
1269
1273
1274
1280 if (Alignment > 8)
1281 Alignment = Align(8);
1282
1296
1299
1300
1302 DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f128);
1303 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128,
1304 SDValue(InFP128, 0), Hi64, SubRegEven);
1305 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128,
1306 SDValue(InFP128, 0), Lo64, SubRegOdd);
1312}
1313
1314
1315
1316
1317
1318
1319
1324
1327 if (Alignment > 8)
1328 Alignment = Align(8);
1329
1330 EVT AddrVT = BasePtr.getValueType();
1332 if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) {
1335 for (int i = 0; i < 4; ++i) {
1336
1345
1349 }
1353 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) {
1356 for (int i = 0; i < 8; ++i) {
1357
1366
1370 }
1374 } else {
1375
1377 }
1378}
1379
1383
1384
1385 if (Subtarget->enableVPU() && MemVT.isVector() && (MemVT))
1387
1390
1391
1392 return Op;
1393 }
1394
1395 if (MemVT == MVT::f128)
1399
1400 return Op;
1401}
1402
1403
1408
1411
1413 StNode->getValue(), SubRegEven);
1415 StNode->getValue(), SubRegOdd);
1416
1418 if (Alignment > 8)
1419 Alignment = Align(8);
1420
1421
1423 OutChains[0] =
1431 OutChains[1] =
1437}
1438
1439
1440
1441
1442
1443
1444
1449
1452 if (Alignment > 8)
1453 Alignment = Align(8);
1454 EVT AddrVT = BasePtr.getValueType();
1456 if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) {
1458 for (int i = 0; i < 4; ++i) {
1464 OutChains[i] =
1469 }
1471 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) {
1473 for (int i = 0; i < 8; ++i) {
1479 OutChains[i] =
1484 }
1486 } else {
1487
1489 }
1490}
1491
1496
1497
1498 if (Subtarget->enableVPU() && MemVT.isVector() && (MemVT))
1500
1503
1504
1505 return Op;
1506 }
1507
1508 if (MemVT == MVT::f128)
1512
1513
1515}
1516
1521
1522
1524
1525
1526
1534}
1535
1538 EVT VT = Node->getValueType(0);
1540 SDValue VAListPtr = Node->getOperand(1);
1548
1549 if (VT == MVT::f128) {
1550
1551
1552
1558
1559 NextPtr =
1561 } else if (VT == MVT::f32) {
1562
1563
1564
1565
1566
1567
1568 NextPtr =
1570
1571 unsigned InternalOffset = 4;
1574 } else {
1575
1576 NextPtr =
1578 }
1579
1580
1582
1583
1584
1588}
1589
1592
1593
1594
1596
1597
1599 SDValue Chain = Op.getOperand(0);
1601 MaybeAlign Alignment(Op.getConstantOperandVal(2));
1602 EVT VT = Node->getValueType(0);
1603
1604
1605
1607
1610 bool NeedsAlign = Alignment.valueOrOne() > StackAlign;
1611
1612
1614 Args.emplace_back(Size, Size.getValueType().getTypeForEVT(*DAG.getContext()));
1615 if (NeedsAlign) {
1617 Args.emplace_back(Align,
1619 }
1621
1622 EVT PtrVT = Op.getValueType();
1624 if (NeedsAlign) {
1626 } else {
1628 }
1629
1635 std::pair<SDValue, SDValue> pair = LowerCallTo(CLI);
1636 Chain = pair.second;
1637 SDValue Result = DAG.getNode(VEISD::GETSTACKTOP, DL, VT, Chain);
1638 if (NeedsAlign) {
1640 DAG.getConstant((Alignment->value() - 1ULL), DL, VT));
1642 DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT));
1643 }
1644
1646
1649}
1650
1654 return DAG.getNode(VEISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0),
1655 Op.getOperand(1));
1656}
1657
1661 return DAG.getNode(VEISD::EH_SJLJ_SETJMP, DL,
1662 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
1663 Op.getOperand(1));
1664}
1665
1669 return DAG.getNode(VEISD::EH_SJLJ_SETUP_DISPATCH, DL, MVT::Other,
1670 Op.getOperand(0));
1671}
1672
1679
1682
1683 unsigned Depth = Op.getConstantOperandVal(0);
1691 return FrameAddr;
1692}
1693
1700
1702
1704 EVT VT = Op.getValueType();
1709}
1710
1714 unsigned IntNo = Op.getConstantOperandVal(0);
1715 switch (IntNo) {
1716 default:
1718 case Intrinsic::eh_sjlj_lsda: {
1720 MVT VT = Op.getSimpleValueType();
1723
1724
1725
1726
1727 TM->getStrList()->push_back(std::string(
1735 }
1737 }
1738 }
1739}
1740
1743 return false;
1745
1746
1747 unsigned Idx;
1748 for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) {
1749 auto ElemV = BVN->getOperand(Idx);
1750 if (!ElemV->isUndef())
1751 break;
1752 }
1753
1754 if (Idx == BVN->getNumOperands())
1755 return false;
1756
1757 UniqueIdx = Idx++;
1758
1759 for (; Idx < BVN->getNumOperands(); ++Idx) {
1760 auto ElemV = BVN->getOperand(Idx);
1761 if (!ElemV->isUndef())
1762 return false;
1763 }
1764 return true;
1765}
1766
1769 return BuildVec->getSplatValue();
1770 }
1772}
1773
1777 MVT ResultVT = Op.getSimpleValueType();
1778
1779
1780 unsigned UniqueIdx;
1783 auto ElemV = Op->getOperand(UniqueIdx);
1786 }
1787
1788
1791 auto AVL = CDAG.getConstant(NumEls, MVT::i32);
1792 return CDAG.getBroadcast(ResultVT, ScalarV, AVL);
1793 }
1794
1795
1797}
1798
1801
1802
1803
1804
1805
1806
1809
1810
1814}
1815
1818 unsigned Opcode = Op.getOpcode();
1819
1820
1821 switch (Opcode) {
1822 case ISD::ATOMIC_FENCE:
1824 case ISD::ATOMIC_SWAP:
1830 case ISD::DYNAMIC_STACKALLOC:
1848 case ISD::LOAD:
1854 case ISD::STORE:
1856 case ISD::VASTART:
1858 case ISD::VAARG:
1860
1865 }
1866
1867
1870
1871 switch (Opcode) {
1872 default:
1874
1875
1876 case VEISD::VEC_BROADCAST:
1877#define ADD_VVP_OP(VVP_NAME, ...) case VEISD::VVP_NAME:
1878#include "VVPNodes.def"
1879
1881 return Op;
1883
1884
1885 case ISD::MLOAD:
1886 case ISD::MSTORE:
1887#define ADD_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1888#include "VVPNodes.def"
1892 }
1893}
1894
1895
1899 switch (N->getOpcode()) {
1900 case ISD::ATOMIC_SWAP:
1901
1902 return;
1903 default:
1905 llvm_unreachable("Do not know how to custom type legalize this operation!");
1906 }
1907}
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1927
1930 unsigned Uid, MCContext &Ctx) const {
1932
1933
1934
1936 MCSymbol *Sym = Ctx.getOrCreateSymbol(MBB->getParent()->getName().data());
1939}
1940
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1963}
1964
1972
1974 Register Tmp1 = MRI.createVirtualRegister(RC);
1975 Register Tmp2 = MRI.createVirtualRegister(RC);
1976 Register Result = MRI.createVirtualRegister(RC);
1977
1979
1980
1981
1982
1994 } else {
1995
1996
1997
1998
2010 }
2011 return Result;
2012}
2013
2017 bool IsLocal = false,
2018 bool IsCall = false) const {
2022
2024 Register Result = MRI.createVirtualRegister(RC);
2025
2027 if (IsCall && !IsLocal) {
2028
2029
2030
2031
2032
2033
2034
2037 } else if (IsLocal) {
2038 Register Tmp1 = MRI.createVirtualRegister(RC);
2039 Register Tmp2 = MRI.createVirtualRegister(RC);
2040
2041
2042
2043
2055 } else {
2056 Register Tmp1 = MRI.createVirtualRegister(RC);
2057 Register Tmp2 = MRI.createVirtualRegister(RC);
2058
2059
2060
2061
2062
2063 Register Tmp3 = MRI.createVirtualRegister(RC);
2079 }
2080 } else {
2081 Register Tmp1 = MRI.createVirtualRegister(RC);
2082 Register Tmp2 = MRI.createVirtualRegister(RC);
2083
2084
2085
2086
2098 }
2099 return Result;
2100}
2101
2105 int FI, int Offset) const {
2108
2111
2112
2113
2117}
2118
2127
2130
2131
2133 Register BufReg = MI.getOperand(1).getReg();
2134
2136
2137 DstReg = MI.getOperand(0).getReg();
2139 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!");
2140 (void)TRI;
2141 Register MainDestReg = MRI.createVirtualRegister(RC);
2142 Register RestoreDestReg = MRI.createVirtualRegister(RC);
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2172
2173
2177
2178
2181
2182
2183 const VEFrameLowering *TFI = Subtarget->getFrameLowering();
2184 if (TFI->hasBP(*MF)) {
2189 MIB.addReg(VE::SX17);
2191 }
2192
2193
2195 MIB.add(MI.getOperand(1));
2200
2201
2202
2203
2204 MIB =
2206
2207 const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2208 MIB.addRegMask(RegInfo->getNoPreservedMask());
2211
2212
2213 BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg)
2218
2219
2220 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg)
2221 .addReg(MainDestReg)
2223 .addReg(RestoreDestReg)
2224 .addMBB(RestoreMBB);
2225
2226
2227
2228
2229
2230 if (TFI->hasBP(*MF)) {
2232 BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17);
2233 MIB.addReg(VE::SX10);
2237 }
2238 BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg)
2244
2245 MI.eraseFromParent();
2246 return SinkMBB;
2247}
2248
2256
2257
2259 Register BufReg = MI.getOperand(0).getReg();
2260
2261 Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass);
2262
2265
2267
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2285
2286
2287 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp);
2292
2293
2294
2295 BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10)
2298
2299
2300 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP);
2301 MIB.add(MI.getOperand(0));
2305
2306
2310
2311 MI.eraseFromParent();
2312 return ThisMBB;
2313}
2314
2324
2325
2326
2328 unsigned MaxCSNum = 0;
2329 for (auto &MBB : *MF) {
2330 if (.isEHPad())
2331 continue;
2332
2334 for (const auto &MI : MBB) {
2335 if (MI.isDebugInstr())
2336 continue;
2337
2338 assert(MI.isEHLabel() && "expected EH_LABEL");
2339 Sym = MI.getOperand(0).getMCSymbol();
2340 break;
2341 }
2342
2344 continue;
2345
2347 CallSiteNumToLPad[CSI].push_back(&MBB);
2348 MaxCSNum = std::max(MaxCSNum, CSI);
2349 }
2350 }
2351
2352
2353 std::vector<MachineBasicBlock *> LPadList;
2355 LPadList.reserve(CallSiteNumToLPad.size());
2356
2357 for (unsigned CSI = 1; CSI <= MaxCSNum; ++CSI) {
2358 for (auto &LP : CallSiteNumToLPad[CSI]) {
2359 LPadList.push_back(LP);
2361 }
2362 }
2363
2364 assert(!LPadList.empty() &&
2365 "No landing pad destinations for the dispatch jump table!");
2366
2367
2368
2369
2370
2371
2372 static const int OffsetIC = 72;
2373 static const int OffsetCS = 8;
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2397
2398
2401
2404
2405
2409
2410
2412 false, true);
2413 BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10)
2417
2418
2419
2421
2422
2426
2428
2429
2432
2434
2435
2436 BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15);
2437 }
2438
2439
2441 Register IReg = MRI.createVirtualRegister(RC);
2443 OffsetCS);
2444 if (LPadList.size() < 64) {
2445 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t))
2447 .addImm(LPadList.size())
2450 } else {
2451 assert(LPadList.size() <= 0x7FFFFFFF && "Too large Landing Pad!");
2452 Register TmpReg = MRI.createVirtualRegister(RC);
2453 BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg)
2456 .addImm(LPadList.size());
2457 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t))
2462 }
2463
2464 Register BReg = MRI.createVirtualRegister(RC);
2465 Register Tmp1 = MRI.createVirtualRegister(RC);
2466 Register Tmp2 = MRI.createVirtualRegister(RC);
2467
2469
2470
2471
2472
2473 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1)
2477 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2)
2480 BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg)
2484 } else {
2485
2486
2487
2488
2489 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1)
2493 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2)
2496 BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg)
2500 }
2501
2502 switch (JTE) {
2504
2505
2506
2507
2508
2509 Register TReg = MRI.createVirtualRegister(RC);
2510 Register Tmp1 = MRI.createVirtualRegister(RC);
2511
2512 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1)
2515 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg)
2519 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t))
2522 break;
2523 }
2525
2526
2527
2528
2529
2530
2531
2532
2534 Register OReg = MRI.createVirtualRegister(RC);
2535 Register TReg = MRI.createVirtualRegister(RC);
2536 Register Tmp1 = MRI.createVirtualRegister(RC);
2537
2538 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1)
2541 BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg)
2548 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg)
2551 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t))
2554 break;
2555 }
2556 default:
2558 }
2559
2560
2562 for (auto &LP : LPadList)
2563 if (SeenMBBs.insert(LP).second)
2565
2566
2570
2571
2572
2574 MBB->succ_rend());
2575
2576 for (auto *MBBS : Successors) {
2577 if (MBBS->isEHPad()) {
2578 MBB->removeSuccessor(MBBS);
2580 }
2581 }
2582
2583 MBB->addSuccessor(DispatchBB);
2584
2585
2586
2587
2588
2590 if (.isCall())
2591 continue;
2592
2594 for (auto &MOp : II.operands())
2595 if (MOp.isReg())
2596 DefRegs.insert(MOp.getReg());
2597
2599 for (unsigned RI = 0; SavedRegs[RI]; ++RI) {
2600 Register Reg = SavedRegs[RI];
2603 }
2604
2605 break;
2606 }
2607 }
2608
2609
2610
2611 for (auto &LP : MBBLPads)
2612 LP->setIsEHPad(false);
2613
2614
2615 MI.eraseFromParent();
2616 return BB;
2617}
2618
2622 switch (MI.getOpcode()) {
2623 default:
2625 case VE::EH_SjLj_LongJmp:
2627 case VE::EH_SjLj_SetJmp:
2629 case VE::EH_SjLj_Setup_Dispatch:
2631 }
2632}
2633
2635 EVT VT = V.getValueType();
2637 return false;
2638
2641 return isInt<7>(C->getSExtValue());
2644 if (VT == MVT::f32 || VT == MVT::f64) {
2645 const APInt &Imm = C->getValueAPF().bitcastToAPInt();
2646 uint64_t Val = Imm.getSExtValue();
2647 if (Imm.getBitWidth() == 32)
2648 Val <<= 32;
2650 }
2651 }
2652 }
2653 return false;
2654}
2655
2657 EVT VT = V.getValueType();
2659 return false;
2660
2666 if (VT == MVT::f32) {
2667
2669 } else if (VT == MVT::f64) {
2671 }
2672 }
2673 }
2674 return false;
2675}
2676
2679 if (SrcVT == MVT::f128)
2680 return VEISD::CMPQ;
2681 return VEISD::CMPF;
2682 }
2683 return isSignedIntSetCC(CC) ? VEISD::CMPI : VEISD::CMPU;
2684}
2685
2687 if (SrcVT == MVT::f128)
2688 return MVT::f64;
2689 return SrcVT;
2690}
2691
2693 bool WithCMov) {
2695
2696
2697
2698
2699 return SrcVT != MVT::f128;
2700 }
2701 if (isIntEqualitySetCC(CC)) {
2702
2703 return true;
2704 }
2705 if (WithCMov) {
2706
2707
2708 return isSignedIntSetCC(CC);
2709 }
2710
2711
2712
2713
2714 return isSignedIntSetCC(CC) && SrcVT == MVT::i64;
2715}
2716
2720
2721
2725 return LHS;
2726 }
2728}
2729
2733 "Should be called with a SELECT node");
2736 SDValue True = N->getOperand(1);
2737 SDValue False = N->getOperand(2);
2738
2739
2740 EVT VT = N->getValueType(0);
2743
2744
2747
2748 EVT VT0 = Cond.getValueType();
2750
2751 } else if (isMImm(False)) {
2752
2753
2755 CC = getSetCCInverse(CC, VT0);
2756 }
2757
2763 } else {
2765 }
2768 return DAG.getNode(VEISD::CMOV, DL, VT, Ops);
2769}
2770
2774 "Should be called with a SELECT_CC node");
2776 SDValue LHS = N->getOperand(0);
2777 SDValue RHS = N->getOperand(1);
2778 SDValue True = N->getOperand(2);
2779 SDValue False = N->getOperand(3);
2780
2781
2782 EVT VT = N->getValueType(0);
2785
2786
2789
2790
2791 EVT LHSVT = LHS.getValueType();
2792 assert(LHSVT == RHS.getValueType());
2794 case MVT::i32:
2795 case MVT::i64:
2796 case MVT::f32:
2797 case MVT::f64:
2798 case MVT::f128:
2799 break;
2800 default:
2801
2803 }
2804
2806
2807 } else if (isSimm7(RHS)) {
2808
2809
2811 CC = getSetCCSwappedOperands(CC);
2812 }
2814
2815 } else if (isMImm(False)) {
2816
2817
2819 CC = getSetCCInverse(CC, LHSVT);
2820 }
2821
2824
2825 bool WithCMov = true;
2827
2831 } else {
2833 }
2834 SDValue Ops[] = {CompNode, True, False,
2836 return DAG.getNode(VEISD::CMOV, DL, VT, Ops);
2837}
2838
2841 switch (User->getOpcode()) {
2842 default:
2843 return false;
2857 case ISD::BR_CC:
2858 case ISD::BITCAST:
2859 case ISD::ATOMIC_CMP_SWAP:
2860 case ISD::ATOMIC_SWAP:
2861 case VEISD::CMPU:
2862 case VEISD::CMPI:
2863 return true;
2865 if (N->getOperand(0).getOpcode() != ISD::SRL)
2866 return true;
2867
2868
2869 return false;
2873 return true;
2875 case VEISD::CMOV:
2876
2877
2884 }
2885 [[fallthrough]];
2891
2892
2894 }
2895}
2896
2898
2899
2901 switch (U->getOpcode()) {
2902 default:
2903
2904
2906 continue;
2907 break;
2911
2912
2913
2914
2915 assert(N->getValueType(0) == MVT::i32 &&
2916 "find truncate to not i32 integer");
2919 continue;
2920 break;
2921 }
2922 }
2923 return false;
2924 }
2925 return true;
2926}
2927
2928
2929
2930
2934 "Should be called with a TRUNCATE node");
2935
2938 EVT VT = N->getValueType(0);
2939
2940
2943
2944
2949
2950
2952
2953
2954
2955
2956
2957
2959 continue;
2960
2962 }
2963
2966 N->getOperand(0), SubI32),
2967 0);
2968}
2969
2972 switch (N->getOpcode()) {
2973 default:
2974 break;
2981 }
2982
2984}
2985
2986
2987
2988
2989
2992 if (Constraint.size() == 1) {
2993 switch (Constraint[0]) {
2994 default:
2995 break;
2996 case 'v':
2998 }
2999 }
3001}
3002
3003std::pair<unsigned, const TargetRegisterClass *>
3006 MVT VT) const {
3008 if (Constraint.size() == 1) {
3009 switch (Constraint[0]) {
3010 default:
3012 case 'r':
3013 RC = &VE::I64RegClass;
3014 break;
3015 case 'v':
3016 RC = &VE::V64RegClass;
3017 break;
3018 }
3019 return std::make_pair(0U, RC);
3020 }
3021
3023}
3024
3025
3026
3027
3028
3030
3032 return 8;
3033
3035}
3036
3038 EVT VT = Y.getValueType();
3039
3040
3042 return false;
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3055 return false;
3056
3057
3058 return true;
3059}
3060
3064 MVT VT = Op.getOperand(0).getSimpleValueType();
3065
3066
3067 assert(VT == MVT::v512i32 || VT == MVT::v512f32);
3068 (void)VT;
3069
3070
3071
3072
3073
3078 if (false ) {
3079
3080 } else {
3089 PackedElt = DAG.getNode(ISD::SRL, DL, MVT::i64, {PackedElt, Shift});
3091 PackedElt = DAG.getNode(ISD::AND, DL, MVT::i64, {PackedElt, Mask});
3094 MVT::i32, PackedElt, SubI32),
3095 0);
3096
3097 if (Op.getSimpleValueType() == MVT::f32) {
3098 Result = DAG.getBitcast(MVT::f32, Result);
3099 } else {
3100 assert(Op.getSimpleValueType() == MVT::i32);
3101 }
3102 }
3103 return Result;
3104}
3105
3109 MVT VT = Op.getOperand(0).getSimpleValueType();
3110
3111
3112 assert(VT == MVT::v512i32 || VT == MVT::v512f32);
3113 (void)VT;
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3131 Val = DAG.getBitcast(MVT::i32, Val);
3134
3136 if (false ) {
3137
3138 } else {
3149 PackedElt = DAG.getNode(ISD::AND, DL, MVT::i64, {PackedElt, Mask});
3151 PackedElt = DAG.getNode(ISD::OR, DL, MVT::i64, {PackedElt, Val});
3152 Result =
3154 {HalfIdx, PackedElt, Vec}),
3155 0);
3156 }
3157 return Result;
3158}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Module.h This file contains the declarations for the Module class.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Register const TargetRegisterInfo * TRI
Promote Memory to Register
uint64_t IntrinsicInst * II
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
const SmallVectorImpl< MachineOperand > & Cond
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static unsigned decideComp(EVT SrcVT, ISD::CondCode CC)
Definition VEISelLowering.cpp:2677
static bool isSimm7(SDValue V)
Definition VEISelLowering.cpp:2634
CCAssignFn * getParamCC(CallingConv::ID CallConv, bool IsVarArg)
Definition VEISelLowering.cpp:56
static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG)
Definition VEISelLowering.cpp:1275
static bool isMImm(SDValue V)
Definition VEISelLowering.cpp:2656
static SDValue prepareTS1AM(SDValue Op, SelectionDAG &DAG, SDValue &Flag, SDValue &Bits)
Definition VEISelLowering.cpp:1108
CCAssignFn * getReturnCC(CallingConv::ID CallConv)
Definition VEISelLowering.cpp:47
static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, bool WithCMov)
Definition VEISelLowering.cpp:2692
static bool isI32InsnAllUses(const SDNode *User, const SDNode *N)
Definition VEISelLowering.cpp:2897
static SDValue lowerLoadI1(SDValue Op, SelectionDAG &DAG)
Definition VEISelLowering.cpp:1320
static SDValue generateComparison(EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode CC, bool WithCMov, const SDLoc &DL, SelectionDAG &DAG)
Definition VEISelLowering.cpp:2717
static EVT decideCompType(EVT SrcVT)
Definition VEISelLowering.cpp:2686
static bool isI32Insn(const SDNode *User, const SDNode *N)
Definition VEISelLowering.cpp:2840
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition VEISelLowering.cpp:1673
static const MVT AllMaskVTs[]
Definition VEISelLowering.cpp:80
static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx)
Definition VEISelLowering.cpp:1741
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition VEISelLowering.cpp:1694
static const MVT AllVectorVTs[]
Definition VEISelLowering.cpp:77
static const MVT AllPackedVTs[]
Definition VEISelLowering.cpp:82
static SDValue finalizeTS1AM(SDValue Op, SelectionDAG &DAG, SDValue Data, SDValue Bits)
Definition VEISelLowering.cpp:1130
static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG)
Definition VEISelLowering.cpp:1404
static SDValue lowerStoreI1(SDValue Op, SelectionDAG &DAG)
Definition VEISelLowering.cpp:1445
Class for arbitrary precision integers.
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
This is an SDNode representing atomic operations.
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
LLVM_ABI void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
LLVM_ABI bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
LLVM_ABI void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVM_ABI void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
LLVM_ABI void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
A parsed version of the target data layout string in and methods for querying it.
Implements a dense probed hash-table based set.
unsigned getAddressSpace() const
Common base class shared among various IRBuilders.
LLVM_ABI bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
uint64_t getScalarSizeInBits() const
unsigned getVectorNumElements() const
static auto integer_valuetypes()
static auto vector_valuetypes()
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
LLVM_ABI void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setReturnAddressIsTaken(bool s)
int getFunctionContextIndex() const
Return the index for the function context object.
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
MachineJumpTableInfo * getOrCreateJumpTableInfo(unsigned JTEntryKind)
getOrCreateJumpTableInfo - Get the JumpTableInfo for this function, if it does already exist,...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void push_back(MachineBasicBlock *MBB)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
BasicBlockListType::iterator iterator
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasCallSiteLandingPad(MCSymbol *Sym)
Return true if the landing pad Eh symbol has an associated call site.
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SmallVectorImpl< unsigned > & getCallSiteLandingPad(MCSymbol *Sym)
Get the call site indexes for a landing pad EH symbol.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
LLVM_ABI unsigned createJumpTableIndex(const std::vector< MachineBasicBlock * > &DestBBs)
createJumpTableIndex - Create a new jump table.
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
@ EK_BlockAddress
EK_BlockAddress - Each entry is a plain address of block, e.g.: .word LBB123.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_ABI const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
LLVM_ABI SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_ABI MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
LLVM_ABI SDValue getRegister(Register Reg, EVT VT)
LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
LLVM_ABI SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
LLVM_ABI SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
const DataLayout & getDataLayout() const
LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
LLVM_ABI SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
LLVM_ABI SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
const TargetMachine & getTarget() const
LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
LLVM_ABI SDValue getValueType(EVT)
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM_ABI SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
void insert_range(Range &&R)
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
virtual bool isJumpTableRelative() const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
TargetLowering(const TargetLowering &)=delete
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
static LLVM_ABI Type * getVoidTy(LLVMContext &C)
Value * getOperand(unsigned i) const
SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
SDValue getNode(unsigned OC, SDVTList VTL, ArrayRef< SDValue > OpV, std::optional< SDNodeFlags > Flags=std::nullopt) const
getNode {
SDValue getUNDEF(EVT VT) const
SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget=false, bool IsOpaque=false) const
bool hasBP(const MachineFunction &MF) const
void setVarArgsFrameOffset(int Offset)
int getVarArgsFrameOffset() const
const VERegisterInfo * getRegisterInfo() const override
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1590
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition VEISelLowering.cpp:3004
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition VEISelLowering.cpp:849
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1270
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition VEISelLowering.cpp:1941
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition VEISelLowering.cpp:918
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1260
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition VEISelLowering.cpp:3037
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1536
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const
Definition VEISelLowering.cpp:2730
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition VEISelLowering.cpp:861
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Definition VEISelLowering.cpp:887
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
Definition VEISelLowering.cpp:1010
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1050
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition VEISelLowering.cpp:1816
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1380
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition VEISelLowering.cpp:2250
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
Definition VEISelLowering.cpp:2970
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition VEISelLowering.cpp:1096
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:3106
SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const
Definition VEISelLowering.cpp:2771
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1666
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Definition VEISelLowering.cpp:3029
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1658
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition VEISelLowering.cpp:366
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition VEISelLowering.cpp:2316
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition VEISelLowering.cpp:1031
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
Definition VEISelLowering.cpp:1965
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Definition VEISelLowering.cpp:2102
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1207
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
Definition VEISelLowering.cpp:2620
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition VEISelLowering.cpp:2120
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition VEISelLowering.cpp:875
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1651
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1492
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
Definition VEISelLowering.cpp:1800
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:963
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1217
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1774
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
Definition VEISelLowering.cpp:2014
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition VEISelLowering.cpp:440
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
Definition VEISelLowering.cpp:1896
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:3061
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition VEISelLowering.cpp:575
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
Definition VEISelLowering.cpp:926
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
Definition VEISelLowering.cpp:2931
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
Definition VEISelLowering.cpp:1928
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context, const Type *RetTy) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition VEISelLowering.cpp:67
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1517
unsigned getJumpTableEncoding() const override
JumpTable for VE.
Definition VEISelLowering.cpp:1919
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1144
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1212
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition VEISelLowering.cpp:555
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:952
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
Definition VEISelLowering.cpp:2991
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1711
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
Definition VEISelLowering.cpp:1223
std::list< std::string > * getStrList() const
LLVM Value Representation.
iterator_range< user_iterator > users()
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ ADD
Simple integer binary arithmetic operators.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ SIGN_EXTEND
Conversion operators.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LLVM_ABI bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
@ System
Synchronized with respect to all concurrently executing threads.
This is an optimization pass for GlobalISel generic memory operations.
static uint64_t getFpImmVal(const ConstantFPSDNode *N)
getFpImmVal - get immediate representation of floating point value
bool isPackedVectorType(EVT SomeVT)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
LLVM_ABI bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
static bool isIntVECondCode(VECC::CondCode CC)
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
static uint64_t getImmVal(const ConstantSDNode *N)
getImmVal - get immediate representation of integer value
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
auto reverse(ContainerTy &&C)
bool isMaskArithmetic(SDValue Op)
static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC)
Convert a DAG floating point condition code to a VE FCC condition.
bool isMaskType(EVT SomeVT)
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isa(const From &Val)
isa - Return true if the parameter to the template is an instance of one of the template type argu...
AtomicOrdering
Atomic ordering for LLVM's memory model.
FunctionAddr VTableAddr uintptr_t uintptr_t Data
bool isVVPOrVEC(unsigned Opcode)
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool isPackingSupportOpcode(unsigned Opc)
std::pair< SDValue, bool > getAnnotatedNodeAVL(SDValue Op)
DWARFExpression::Operation Op
unsigned M0(unsigned Val)
static VECC::CondCode intCondCode2Icc(ISD::CondCode CC)
Convert a DAG integer condition code to a VE ICC condition.
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
LLVM_ABI bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
static bool isMImmVal(uint64_t Val)
static bool isMImm32Val(uint32_t Val)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isVector() const
Return true if this is a vector value type.
EVT changeVectorElementType(EVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class contains a discriminated union of information about pointers in memory operands,...
static LLVM_ABI MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
bool isAfterLegalizeDAG() const
const uint32_t * getNoPreservedMask() const override