VEISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H

15#define LLVM_LIB_TARGET_VE_VEISELLOWERING_H

17#include "VE.h"

20namespace llvm {

25 switch (CC) {

26 default:

48 }

49}

53 switch (CC) {

54 default:

94 }

95}

99 return N->getSExtValue();

100}

101

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104 const APInt &Imm = N->getValueAPF().bitcastToAPInt();

105 uint64_t Val = Imm.getZExtValue();

106 if (Imm.getBitWidth() == 32) {

107

108 Val <<= 32;

109 }

110 return Val;

111}

112

113class VECustomDAG;

114

117

118 void initRegisterClasses();

119 void initSPUActions();

120 void initVPUActions();

121

122public:

124

126 return MVT::i32;

127 }

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134 EVT VT) const override;

135

137 bool isVarArg,

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146 bool isVarArg,

149 const Type *RetTy) const override;

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158 return true;

159 }

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178 unsigned Uid,

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234 bool IsCall) const;

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265 bool ForCodeSize) const override;

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270 unsigned *Fast) const override;

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275 std::pair<unsigned, const TargetRegisterClass *>

277 StringRef Constraint, MVT VT) const override;

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293 bool isCtlzFast() const override { return true; }

294

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298};

299}

300

301#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

This file describes how to lower LLVM code to machine code.

Class for arbitrary precision integers.

an instruction that atomically reads a memory location, combines it with another value,...

A parsed version of the target data layout string in and methods for querying it.

Common base class shared among various IRBuilders.

This is an important class for using LLVM in a threaded context.

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

LegalizeAction

This enum indicates whether operations are valid for a target, and if not, what action should be used...

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const

SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

SDValue lowerVVP_GATHER_SCATTER(SDValue Op, VECustomDAG &) const

bool isCheapToSpeculateCtlz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition VEISelLowering.h:291

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const

} Custom Inserter

SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition VEISelLowering.h:125

SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override

Returns relocation base for the given PIC jumptable.

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

getSetCCResultType - Return the ISD::SETCC ValueType

SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const

SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Helper functions for atomic operations.

Definition VEISelLowering.h:156

bool hasAndNot(SDValue Y) const override

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...

SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const

SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.

VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)

Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Custom Lower {.

SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const

MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const

SDValue legalizePackedAVL(SDValue Op, VECustomDAG &CDAG) const

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

} VVPLowering

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const

SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const

SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const

unsigned getMinimumJumpTableEntries() const override

} Inline Assembly

SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const

Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const

void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const

SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

Custom Inserter {.

MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override

Returns true if the target allows unaligned memory accesses of the specified type.

SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const

bool hasStandaloneRem(EVT) const override

Return true if the target can handle a standalone remainder operation.

Definition VEISelLowering.h:289

SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const

TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override

Custom Lower {.

ISD::NodeType getExtendForAtomicOps() const override

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...

Definition VEISelLowering.h:166

SDValue splitPackedLoadStore(SDValue Op, VECustomDAG &CDAG) const

SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const

SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const

SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const

SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const

Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

} Custom Lower

SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const

SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const

SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const

} Custom DAGCombine

SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const

bool isCtlzFast() const override

Return true if ctlz instruction is fast.

Definition VEISelLowering.h:293

SDValue legalizeInternalLoadStoreOp(SDValue Op, VECustomDAG &CDAG) const

const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const

unsigned getJumpTableEncoding() const override

JumpTable for VE.

SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const

bool isIntDivCheap(EVT, AttributeList) const override

Return true if integer divide is usually cheaper than a sequence of several shifts,...

Definition VEISelLowering.h:287

SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const

Return the register ID of the name passed in.

SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const

ConstraintType getConstraintType(StringRef Constraint) const override

Inline Assembly {.

SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const

SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

This is an optimization pass for GlobalISel generic memory operations.

static uint64_t getFpImmVal(const ConstantFPSDNode *N)

getFpImmVal - get immediate representation of floating point value

Definition VEISelLowering.h:103

static uint64_t getImmVal(const ConstantSDNode *N)

getImmVal - get immediate representation of integer value

Definition VEISelLowering.h:98

static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC)

Convert a DAG floating point condition code to a VE FCC condition.

Definition VEISelLowering.h:52

AtomicOrdering

Atomic ordering for LLVM's memory model.

DWARFExpression::Operation Op

static VECC::CondCode intCondCode2Icc(ISD::CondCode CC)

Convert a DAG integer condition code to a VE ICC condition.

Definition VEISelLowering.h:24

This struct is a compact representation of a valid (non-zero power of two) alignment.

This structure contains all information that is necessary for lowering calls.