LLVM: lib/Target/VE/MCTargetDesc/VEMCCodeEmitter.cpp Source File (original) (raw)
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14#include "VE.h"
28#include
29#include
30
31using namespace llvm;
32
33#define DEBUG_TYPE "mccodeemitter"
34
35STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36
37namespace {
38
41
42public:
44 : Ctx(ctx) {}
45 VEMCCodeEmitter(const VEMCCodeEmitter &) = delete;
46 VEMCCodeEmitter &operator=(const VEMCCodeEmitter &) = delete;
47 ~VEMCCodeEmitter() override = default;
48
49 void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB,
50 SmallVectorImpl &Fixups,
51 const MCSubtargetInfo &STI) const override;
52
53
54
55 uint64_t getBinaryCodeForInstr(const MCInst &MI,
56 SmallVectorImpl &Fixups,
57 const MCSubtargetInfo &STI) const;
58
59
60
61 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
62 SmallVectorImpl &Fixups,
63 const MCSubtargetInfo &STI) const;
64
66 SmallVectorImpl &Fixups,
67 const MCSubtargetInfo &STI) const;
68 uint64_t getCCOpValue(const MCInst &MI, unsigned OpNo,
69 SmallVectorImpl &Fixups,
70 const MCSubtargetInfo &STI) const;
71 uint64_t getRDOpValue(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl &Fixups,
73 const MCSubtargetInfo &STI) const;
74};
75
76}
77
80 bool PCRel = false;
81 switch (Kind) {
85 PCRel = true;
86 }
88}
89
90void VEMCCodeEmitter::encodeInstruction(const MCInst &MI,
94 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
96
97 ++MCNumEmitted;
98}
99
100unsigned VEMCCodeEmitter::getMachineOpValue(const MCInst &MI,
101 const MCOperand &MO,
102 SmallVectorImpl &Fixups,
103 const MCSubtargetInfo &STI) const {
107 return static_cast<unsigned>(MO.getImm());
108
110
111 const MCExpr *Expr = MO.getExpr();
114 addFixup(Fixups, 0, Expr, Kind);
115 return 0;
116 }
117
118 int64_t Res;
119 if (Expr->evaluateAsAbsolute(Res))
120 return Res;
121
123 return 0;
124}
125
126uint64_t
127VEMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
128 SmallVectorImpl &Fixups,
129 const MCSubtargetInfo &STI) const {
130 const MCOperand &MO = MI.getOperand(OpNo);
132 return getMachineOpValue(MI, MO, Fixups, STI);
133
135 return 0;
136}
137
138uint64_t VEMCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned OpNo,
139 SmallVectorImpl &Fixups,
140 const MCSubtargetInfo &STI) const {
141 const MCOperand &MO = MI.getOperand(OpNo);
144 static_cast<VECC::CondCode>(getMachineOpValue(MI, MO, Fixups, STI)));
145 return 0;
146}
147
148uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
149 SmallVectorImpl &Fixups,
150 const MCSubtargetInfo &STI) const {
151 const MCOperand &MO = MI.getOperand(OpNo);
154 getMachineOpValue(MI, MO, Fixups, STI)));
155 return 0;
156}
157
158#include "VEGenMCCodeEmitter.inc"
159
162 return new VEMCCodeEmitter(MCII, Ctx);
163}
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
MCRegister getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_ve_srel32
fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
@ fixup_ve_pc_hi32
fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo@pc_hi
@ fixup_ve_pc_lo32
fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo
VE::Fixups getFixupKind(uint8_t S)
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
static unsigned VECondCodeToVal(VECC::CondCode CC)
static unsigned VERDToVal(VERD::RoundingMode R)
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
MCCodeEmitter * createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition VEMCCodeEmitter.cpp:160