VERegisterInfo.cpp Source File (original) (raw)

14#include "VE.h"

24using namespace llvm;

26#define DEBUG_TYPE "ve-register-info"

28#define GET_REGINFO_TARGET_DESC

29#include "VEGenRegisterInfo.inc"

39 default:

40 return CSR_SaveList;

42 return CSR_preserve_all_SaveList;

43 }

44}

48 switch (CC) {

51 default:

52 return CSR_RegMask;

54 return CSR_preserve_all_RegMask;

55 }

56}

59 return CSR_NoRegs_RegMask;

60}

65 const Register ReservedRegs[] = {

66 VE::SX8,

67 VE::SX9,

68 VE::SX10,

69 VE::SX11,

72 VE::SX12,

73 VE::SX13,

75 VE::SX14,

76 VE::SX15,

77 VE::SX16,

78 VE::SX17,

81 };

83 for (auto R : ReservedRegs)

85 ++ItAlias)

93}

97 return &VE::I64RegClass;

98}

101

102 unsigned OffDisp = 2;

103

104#define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii

105

106 {

108 switch (MI.getOpcode()) {

109 case INLINEASM:

114

115 OffDisp = 1;

116 break;

117 }

118 }

119#undef RRCAS_multi_cases

120

121 return OffDisp;

122}

123

124namespace {

125class EliminateFrameIndex {

126 const TargetInstrInfo &TII;

127 const TargetRegisterInfo &TRI;

129 MachineBasicBlock &MBB;

132

133

134 MachineFunction &getFunc() const { return *MBB.getParent(); }

135 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {

136 return TRI.getSubReg(Reg, Idx);

137 }

138 inline const MCInstrDesc &get(unsigned Opcode) const {

139 return TII.get(Opcode);

140 }

141 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) {

143 }

144 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) {

145 return build(get(InstOpc), DestReg);

146 }

147 inline MachineInstrBuilder build(const MCInstrDesc &MCID) {

149 }

150 inline MachineInstrBuilder build(unsigned InstOpc) {

152 }

153

154

155

156

157 void prepareReplaceFI(MachineInstr &MI, Register &FrameReg, int64_t &Offset,

158 int64_t Bytes = 0);

159

160

161

163 int FIOperandNum);

164

165

166 void processSTQ(MachineInstr &MI, Register FrameReg, int64_t Offset,

167 int FIOperandNum);

168 void processLDQ(MachineInstr &MI, Register FrameReg, int64_t Offset,

169 int FIOperandNum);

170

171 void processSTVM(MachineInstr &MI, Register FrameReg, int64_t Offset,

172 int FIOperandNum);

173 void processLDVM(MachineInstr &MI, Register FrameReg, int64_t Offset,

174 int FIOperandNum);

175

176 void processSTVM512(MachineInstr &MI, Register FrameReg, int64_t Offset,

177 int FIOperandNum);

178 void processLDVM512(MachineInstr &MI, Register FrameReg, int64_t Offset,

179 int FIOperandNum);

180

181public:

182 EliminateFrameIndex(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,

186

187

188 void processMI(MachineInstr &MI, Register FrameReg, int64_t Offset,

189 int FIOperandNum);

190};

191}

192

193

194

196 int64_t &Offset, int64_t Bytes) {

198

199

200 return;

201 }

202

203

204

205

206

207

208 build(VE::LEAzii, clobber).addImm(0).addImm(0).addImm(Lo_32(Offset));

209 build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32));

210 build(VE::LEASLrri, clobber)

211 .addReg(clobber)

212 .addReg(FrameReg)

214

215

216 FrameReg = clobber;

218}

219

220

222 int64_t Offset, int FIOperandNum) {

224

225

226

227 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);

229}

230

232 int64_t Offset, int FIOperandNum) {

233 assert(MI.getOpcode() == VE::STQrii);

235

236 prepareReplaceFI(MI, FrameReg, Offset, 8);

237

238 Register SrcReg = MI.getOperand(3).getReg();

239 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);

240 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);

241

243 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg);

245

246 MI.setDesc(get(VE::STrii));

247 MI.getOperand(3).setReg(SrcHiReg);

250}

251

253 int64_t Offset, int FIOperandNum) {

254 assert(MI.getOpcode() == VE::LDQrii);

256

257 prepareReplaceFI(MI, FrameReg, Offset, 8);

258

259 Register DestReg = MI.getOperand(0).getReg();

260 Register DestHiReg = getSubReg(DestReg, VE::sub_even);

261 Register DestLoReg = getSubReg(DestReg, VE::sub_odd);

262

264 build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0);

266 MI.setDesc(get(VE::LDrii));

267 MI.getOperand(0).setReg(DestHiReg);

270}

271

273 int64_t Offset, int FIOperandNum) {

274 assert(MI.getOpcode() == VE::STVMrii);

276

277

278

279

280

281

282

283

284

285

286

287

288

289 prepareReplaceFI(MI, FrameReg, Offset, 24);

290

291 Register SrcReg = MI.getOperand(3).getReg();

292 bool isKill = MI.getOperand(3).isKill();

293

294

296 for (int i = 0; i < 3; ++i) {

297 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i);

299 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(

303 }

305 MI.setDesc(get(VE::STrii));

306 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true);

308}

309

311 int64_t Offset, int FIOperandNum) {

312 assert(MI.getOpcode() == VE::LDVMrii);

314

315

316

317

318

319

320

321

322

323

324

325

326

327 prepareReplaceFI(MI, FrameReg, Offset, 24);

328

329 Register DestReg = MI.getOperand(0).getReg();

330

331

332 unsigned TmpReg = VE::SX16;

333 for (int i = 0; i < 4; ++i) {

334 if (i != 3) {

336 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);

339 } else {

340

341 MI.setDesc(get(VE::LDrii));

342 MI.getOperand(0).ChangeToRegister(TmpReg, true);

343 }

344

345

346 if (i == 0)

348 else if (i != 3)

349 build(VE::LVMir_m, DestReg)

350 .addImm(i)

352 .addReg(DestReg);

353 else

354 BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestReg)

358 }

360}

361

363 int64_t Offset, int FIOperandNum) {

364 assert(MI.getOpcode() == VE::STVM512rii);

366

367 prepareReplaceFI(MI, FrameReg, Offset, 56);

368

369 Register SrcReg = MI.getOperand(3).getReg();

370 Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd);

371 Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even);

372 bool isKill = MI.getOperand(3).isKill();

373

374

376

378 for (int i = 0; i < 4; ++i) {

379 LastMI = build(VE::SVMmr, TmpReg).addReg(SrcLoReg).addImm(i);

381 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(

385 }

386 if (isKill)

388

389 for (int i = 0; i < 3; ++i) {

390 build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(i);

392 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(

396 }

397 LastMI = build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(3);

398 if (isKill) {

400

402 }

403 MI.setDesc(get(VE::STrii));

404 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true);

406}

407

409 int64_t Offset, int FIOperandNum) {

410 assert(MI.getOpcode() == VE::LDVM512rii);

412

413 prepareReplaceFI(MI, FrameReg, Offset, 56);

414

415 Register DestReg = MI.getOperand(0).getReg();

416 Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd);

417 Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even);

418

419

421 build(VE::IMPLICIT_DEF, DestReg);

422 for (int i = 0; i < 4; ++i) {

424 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);

426 build(VE::LVMir_m, DestLoReg)

427 .addImm(i)

429 .addReg(DestLoReg);

431 }

432 for (int i = 0; i < 3; ++i) {

434 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);

436 build(VE::LVMir_m, DestHiReg)

437 .addImm(i)

439 .addReg(DestHiReg);

441 }

442 MI.setDesc(get(VE::LDrii));

443 MI.getOperand(0).ChangeToRegister(TmpReg, true);

444 BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestHiReg)

449}

450

452 int64_t Offset, int FIOperandNum) {

453 switch (MI.getOpcode()) {

454 case VE::STQrii:

455 processSTQ(MI, FrameReg, Offset, FIOperandNum);

456 return;

457 case VE::LDQrii:

458 processLDQ(MI, FrameReg, Offset, FIOperandNum);

459 return;

460 case VE::STVMrii:

461 processSTVM(MI, FrameReg, Offset, FIOperandNum);

462 return;

463 case VE::LDVMrii:

464 processLDVM(MI, FrameReg, Offset, FIOperandNum);

465 return;

466 case VE::STVM512rii:

467 processSTVM512(MI, FrameReg, Offset, FIOperandNum);

468 return;

469 case VE::LDVM512rii:

470 processLDVM512(MI, FrameReg, Offset, FIOperandNum);

471 return;

472 }

473 prepareReplaceFI(MI, FrameReg, Offset);

475}

476

478 int SPAdj, unsigned FIOperandNum,

480 assert(SPAdj == 0 && "Unexpected");

481

483 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

484

491 EliminateFrameIndex EFI(TII, TRI, DL, *MI.getParent(), II);

492

493

496 TFI.getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();

498

499 EFI.processMI(MI, FrameReg, Offset, FIOperandNum);

500 return false;

501}

502

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file implements the BitVector class.

const HexagonInstrInfo * TII

Promote Memory to Register

uint64_t IntrinsicInst * II

static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, unsigned FramePtr)

static unsigned offsetToDisp(MachineInstr &MI)

Definition VERegisterInfo.cpp:100

#define RRCAS_multi_cases(NAME)

CallingConv::ID getCallingConv() const

getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...

MCRegAliasIterator enumerates all registers aliasing Reg.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

MachineInstrBundleIterator< MachineInstr > iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

LLVM_ABI bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

Wrapper class representing virtual and physical registers.

TargetInstrInfo - Interface to description of machine instruction set.

const VEInstrInfo * getInstrInfo() const override

const VERegisterInfo * getRegisterInfo() const override

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ PreserveAll

Used for runtime calls that preserves (almost) all registers.

@ Fast

Attempts to make calls as fast as possible (e.g.

LLVM_ABI Error build(ArrayRef< Module * > Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)

Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

constexpr uint32_t Hi_32(uint64_t Value)

Return the high 32 bits of a 64 bit value.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr uint32_t Lo_32(uint64_t Value)

Return the low 32 bits of a 64 bit value.

unsigned getKillRegState(bool B)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

unsigned M0(unsigned Val)

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition VERegisterInfo.cpp:62

const uint32_t * getNoPreservedMask() const override

Definition VERegisterInfo.cpp:58

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

Code Generation virtual methods...

Definition VERegisterInfo.cpp:35

bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

Definition VERegisterInfo.cpp:477

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override

Definition VERegisterInfo.cpp:46

Definition VERegisterInfo.cpp:503

VERegisterInfo()

Definition VERegisterInfo.cpp:32

const TargetRegisterClass * getPointerRegClass(unsigned Kind) const override

Definition VERegisterInfo.cpp:96