VirtRegMap.cpp Source File (original) (raw)

39#include "llvm/Config/llvm-config.h"

45#include

46#include

47#include

49using namespace llvm;

51#define DEBUG_TYPE "regalloc"

53 STATISTIC(NumSpillSlots, "Number of spill slots allocated");

54 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");

63 false, true)

66 MRI = &mf.getRegInfo();

67 TII = mf.getSubtarget().getInstrInfo();

68 TRI = mf.getSubtarget().getRegisterInfo();

69 MF = &mf;

71 Virt2PhysMap.clear();

72 Virt2StackSlotMap.clear();

73 Virt2SplitMap.clear();

74 Virt2ShapeMap.clear();

76 grow();

77}

80 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();

81 Virt2PhysMap.resize(NumRegs);

82 Virt2StackSlotMap.resize(NumRegs);

83 Virt2SplitMap.resize(NumRegs);

84}

88 assert(!Virt2PhysMap[virtReg] &&

89 "attempt to assign physical register to already mapped "

90 "virtual register");

92 "Attempt to map virtReg to a reserved physReg");

93 Virt2PhysMap[virtReg] = physReg;

94}

97 unsigned Size = TRI->getSpillSize(*RC);

98 Align Alignment = TRI->getSpillAlign(*RC);

101 Align CurrentAlign = ST.getFrameLowering()->getStackAlign();

102 if (Alignment > CurrentAlign && TRI ->canRealignStack(*MF)) {

103 Alignment = CurrentAlign;

104 }

106 ++NumSpillSlots;

107 return SS;

108}

109

111 Register Hint = MRI->getSimpleHint(VirtReg);

112 if (!Hint.isValid())

113 return false;

114 if (Hint.isVirtual())

117}

118

120 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VirtReg);

121 if (Hint.second.isPhysical())

122 return true;

123 if (Hint.second.isVirtual())

124 return hasPhys(Hint.second);

125 return false;

126}

127

131 "attempt to assign stack slot to already spilled register");

133 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);

134}

135

139 "attempt to assign stack slot to already spilled register");

141 (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&

142 "illegal fixed frame index");

143 Virt2StackSlotMap[virtReg] = SS;

144}

145

147 OS << "********** REGISTER MAP **********\n";

148 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

150 if (Virt2PhysMap[Reg]) {

151 OS << '[' << printReg(Reg, TRI) << " -> "

152 << printReg(Virt2PhysMap[Reg], TRI) << "] "

153 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";

154 }

155 }

156

157 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

160 OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]

161 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";

162 }

163 }

164 OS << '\n';

165}

166

167#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

171#endif

172

174

181

185 VRM.init(MF);

186 return VRM;

187}

188

189

190

191

192

193

194

195

196

197

198namespace {

199

200class VirtRegRewriter {

211 bool ClearVirtRegs;

212

213 void rewrite();

214 void addMBBLiveIns();

215 bool readsUndefSubreg(const MachineOperand &MO) const;

220 LaneBitmask liveOutUndefPhiLanesForUndefSubregDef(

223

224public:

228 : Indexes(Indexes), LIS(LIS), LRM(LRM), VRM(VRM), DebugVars(DebugVars),

229 ClearVirtRegs(ClearVirtRegs) {}

230

232};

233

235public:

236 static char ID;

237 bool ClearVirtRegs;

238 VirtRegRewriterLegacy(bool ClearVirtRegs = true)

239 : MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}

240

241 void getAnalysisUsage(AnalysisUsage &AU) const override;

242

243 bool runOnMachineFunction(MachineFunction&) override;

244

245 MachineFunctionProperties getSetProperties() const override {

246 if (ClearVirtRegs) {

247 return MachineFunctionProperties().setNoVRegs();

248 }

249

250 return MachineFunctionProperties();

251 }

252};

253

254}

255

256char VirtRegRewriterLegacy::ID = 0;

257

259

261 "Virtual Register Rewriter", false, false)

270

271void VirtRegRewriterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {

272 AU.setPreservesCFG();

282

283 if (!ClearVirtRegs)

285

287}

288

289bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {

290 VirtRegMap &VRM = getAnalysis().getVRM();

291 LiveIntervals &LIS = getAnalysis().getLIS();

292 LiveRegMatrix &LRM = getAnalysis().getLRM();

293 SlotIndexes &Indexes = getAnalysis().getSI();

295 getAnalysis().getLDV();

296

297 VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);

298 return R.run(MF);

299}

300

305

312

313 VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);

314 if (!R.run(MF))

316

322

323

324 if (ClearVirtRegs)

326 return PA;

327}

328

330 MF = &fn;

334

335 LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"

336 << "********** Function: " << MF->getName() << '\n');

338

339

341

342

343 addMBBLiveIns();

344

345

346 rewrite();

347

348 if (ClearVirtRegs) {

349

350

351

352

354

355

356

358 MRI->clearVirtRegs();

359 }

360

361 return true;

362}

363

364void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,

368

369 using SubRangeIteratorPair =

370 std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;

371

376 SubRanges.push_back(std::make_pair(&SR, SR.begin()));

377 if ( First .isValid() || SR.segments.front().start < First)

378 First = SR.segments.front().start;

379 if ( Last .isValid() || SR.segments.back().end > Last)

380 Last = SR.segments.back().end;

381 }

382

383

384

388

389

391 for (auto &RangeIterPair : SubRanges) {

394 while (SRI != SR->end() && SRI->end <= MBBBegin)

395 ++SRI;

396 if (SRI == SR->end())

397 continue;

398 if (SRI->start <= MBBBegin)

400 }

401 if (LaneMask.none())

402 continue;

405 }

406}

407

408

409

410void VirtRegRewriter::addMBBLiveIns() {

411 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {

413 if (MRI->reg_nodbg_empty(VirtReg))

414 continue;

417 continue;

418

419

421 if (!PhysReg) {

422

423

424 assert(!ClearVirtRegs && "Unmapped virtual register");

425 continue;

426 }

427

429 addLiveInsForSubRanges(LI, PhysReg);

430 } else {

431

432

433

435 for (const auto &Seg : LI) {

437 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {

440 }

441 }

442 }

443 }

444

445

446

449}

450

451

452

453bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {

454

456 return true;

457

462

463

465 "Reads of completely dead register should be marked undef already");

466 unsigned SubRegIdx = MO.getSubReg();

468 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);

469

471 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))

472 return false;

473 }

474 return true;

475}

476

477void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) {

478 if (.isIdentityCopy())

479 return;

481 ++NumIdCopies;

482

483 Register DstReg = MI.getOperand(0).getReg();

484

485

486

488 return;

489

490 RewriteRegs.insert(DstReg);

491

492

493

494

495

496

497

498 if (MI.getOperand(1).isUndef() || MI.getNumOperands() > 2) {

499 MI.setDesc(TII->get(TargetOpcode::KILL));

501 return;

502 }

503

504 if (Indexes)

506 MI.eraseFromBundle();

508}

509

510

511

512

513

514void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {

515 if (.isCopy() && .isKill())

516 return;

517

518 if (MI.isBundledWithPred() && .isBundledWithSucc()) {

520

521

525 I != E && I->isBundledWithSucc(); ++I) {

526 if (->isCopy() && ->isKill())

527 return;

528 MIs.push_back(&*I);

529 }

531

532 auto anyRegsAlias = [](const MachineInstr *Dst,

536 if (Src != Dst)

537 if (TRI->regsOverlap(Dst->getOperand(0).getReg(),

538 Src->getOperand(1).getReg()))

539 return true;

540 return false;

541 };

542

543

544

545

546 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) {

547 for (int I = E; I--; )

548 if (!anyRegsAlias(MIs[I], ArrayRef(MIs).take_front(E), TRI)) {

549 if (I + 1 != E)

551 --E;

552 }

553 if (PrevE == E) {

554 MF->getFunction().getContext().emitError(

555 "register rewriting failed: cycle in copy bundle");

556 break;

557 }

558 }

559

562

563

564

565 if (BundledMI != BundleStart) {

566 BundledMI->removeFromBundle();

567 MBB.insert(BundleStart, BundledMI);

568 } else if (BundledMI->isBundledWithSucc()) {

569 BundledMI->unbundleFromSucc();

570 BundleStart = &*std::next(BundledMI->getIterator());

571 }

572

573 if (Indexes && BundledMI != FirstMI)

575 }

576 }

577}

578

579

580

581

582bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,

587 for (MCRegUnit Unit : TRI->regunits(SuperPhysReg)) {

589

590

591

592

593

594

595

596

597

598

599 if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))

600 return true;

601 }

602 return false;

603}

604

605

606

607

608LaneBitmask VirtRegRewriter::liveOutUndefPhiLanesForUndefSubregDef(

613

615

620 LiveOutUndefLanes |= NeedImpDefLanes;

621 }

622 }

623 }

624

629 LiveOutUndefLanes &= ~InterferingLanes;

630

632 dbgs() << "Need live out undef defs for " << printReg(PhysReg)

633 << LiveOutUndefLanes << " from " << printMBBReference(MBB) << '\n';

634 });

635

636 return LiveOutUndefLanes;

637}

638

639void VirtRegRewriter::rewrite() {

640 bool NoSubRegLiveness = MRI ->subRegLivenessEnabled();

644

650

652 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());

653

655 continue;

658 if (!PhysReg)

659 continue;

660

662

663 RewriteRegs.insert(PhysReg);

664 assert( MRI ->isReserved(PhysReg) && "Reserved register assignment");

665

666

669 if (NoSubRegLiveness || MRI ->shouldTrackSubRegLiveness(VirtReg)) {

670

671

672

674 (MO.isDef() && subRegLiveThrough(MI, PhysReg)))

676

677 if (MO.isDef()) {

678

681 else

683 }

684 } else {

685 if (MO.isUse()) {

686 if (readsUndefSubreg(MO))

687

688

689

691 } else if (!MO.isDead()) {

695

697 liveOutUndefPhiLanesForUndefSubregDef(LI, *MBBI, SubReg,

698 PhysReg, MI);

699 if (LiveOutUndefLanes.any()) {

701

702

703

704 if ( TRI ->getCoveringSubRegIndexes(MRI->getRegClass(VirtReg),

705 LiveOutUndefLanes,

706 CoveringIndexes))

708 "cannot represent required subregister defs");

709

710

711

712

713

714

715 for (unsigned SubIdx : CoveringIndexes)

716 SuperDefs.push_back(TRI->getSubReg(PhysReg, SubIdx));

717 }

718 }

719 }

720 }

721

722

723

724

725

726 if (MO.isDef()) {

729 }

730

731

732 PhysReg = TRI->getSubReg(PhysReg, SubReg);

733 assert(PhysReg.isValid() && "Invalid SubReg for physical register");

735 }

736

737

740 }

741

742

743

744 while (!SuperKills.empty())

746

747 while (!SuperDeads.empty())

749

750 while (!SuperDefs.empty())

752

754

755 expandCopyBundle(MI);

756

757

758 handleIdentityCopy(MI);

759 }

760 }

761

762 if (LIS) {

763

764

765 for (Register PhysReg : RewriteRegs) {

766 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

768 }

769 }

770 }

771

772 RewriteRegs.clear();

773}

774

777 OS << "virt-reg-rewriter";

778 if (!ClearVirtRegs)

779 OS << "";

780}

781

783 return new VirtRegRewriterLegacy(ClearVirtRegs);

784}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator MBBI

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

const HexagonInstrInfo * TII

A common definition of LaneBitmask for use in TableGen and CodeGen.

Promote Memory to Register

ModuleAnalysisManager MAM

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static bool isPhysical(const MachineOperand &MO)

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Represents analyses that only rely on functions' control flow.

Implements a dense probed hash-table based set.

FunctionPass class - This class is used to implement most global optimizations.

void emitDebugValues(VirtRegMap *VRM)

emitDebugValues - Emit new DBG_VALUE instructions reflecting the changes that happened during registe...

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

LLVM_ABI void addKillFlags(const VirtRegMap *)

Add kill flags to any instruction that kills a virtual register.

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

void removeRegUnit(MCRegUnit Unit)

Remove computed live range for register unit Unit.

LiveInterval & getInterval(Register Reg)

LiveRange & getRegUnit(MCRegUnit Unit)

Return the live range for register unit Unit.

LLVM_ABI MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const

If LI is confined to a single basic block, return a pointer to that block.

bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const

bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const

This class represents the liveness of a register, stack slot, etc.

Segments::const_iterator const_iterator

bool liveAt(SlotIndex index) const

LaneBitmask checkInterferenceLanes(SlotIndex Start, SlotIndex End, MCRegister PhysReg)

Check for interference in the segment [Start, End) that may prevent assignment to PhysReg,...

Wrapper class representing physical registers. Should be passed by value.

constexpr bool isValid() const

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

An RAII based helper class to modify MachineFunctionProperties when running pass.

LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

LLVM_ABI void sortUniqueLiveIns()

Sorts and uniques the LiveIns vector.

LLVM_ABI void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const

reverse_instr_iterator instr_rend()

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

iterator_range< succ_iterator > successors()

Instructions::reverse_iterator reverse_instr_iterator

LLVM_ABI int CreateSpillStackObject(uint64_t Size, Align Alignment)

Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

BasicBlockListType::iterator iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

void setIsInternalRead(bool Val=true)

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

LLVM_ABI void setIsRenamable(bool Val=true)

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

void setIsUndef(bool Val=true)

getReg - Returns the register number.

const uint32_t * getRegMask() const

getRegMask - Returns a bit mask of registers preserved by this RegMask operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

SlotIndex - An opaque wrapper around machine indexes.

SlotIndex getBoundaryIndex() const

Returns the boundary index for associated with this index.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)

Insert the given machine instruction into the mapping.

MBBIndexIterator getMBBLowerBound(MBBIndexIterator Start, SlotIndex Idx) const

Get an iterator pointing to the first IdxMBBPair with SlotIndex greater than or equal to Idx.

LLVM_ABI void removeSingleMachineInstrFromMaps(MachineInstr &MI)

Removes a single machine instruction MI from the mapping.

MBBIndexIterator MBBIndexBegin() const

Returns an iterator for the begin of the idx2MBBMap.

MBBIndexIterator MBBIndexEnd() const

Return an iterator for the end of the idx2MBBMap.

SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator

Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

LLVM_ABI VirtRegMap run(MachineFunction &MF, MachineFunctionAnalysisManager &MAM)

Definition VirtRegMap.cpp:182

LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition VirtRegMap.cpp:176

LLVM_ABI bool hasKnownPreference(Register VirtReg) const

returns true if VirtReg has a known preferred register.

Definition VirtRegMap.cpp:119

LLVM_ABI int assignVirt2StackSlot(Register virtReg)

create a mapping for the specifed virtual register to the next available stack slot

Definition VirtRegMap.cpp:128

void clearAllVirt()

clears all virtual to physical register mappings

LLVM_ABI void init(MachineFunction &MF)

LLVM_ABI bool hasPreferredPhys(Register VirtReg) const

returns true if VirtReg is assigned to its preferred physreg.

Definition VirtRegMap.cpp:110

LLVM_ABI void dump() const

Definition VirtRegMap.cpp:168

MachineRegisterInfo & getRegInfo() const

LLVM_ABI void assignVirt2Phys(Register virtReg, MCRegister physReg)

creates a mapping for the specified virtual register to the specified physical register

Definition VirtRegMap.cpp:86

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

LLVM_ABI void print(raw_ostream &OS, const Module *M=nullptr) const

Definition VirtRegMap.cpp:146

LLVM_ABI void grow()

Definition VirtRegMap.cpp:79

bool hasPhys(Register virtReg) const

returns true if the specified virtual register is mapped to a physical register

static constexpr int NO_STACK_SLOT

LLVM_ABI void printPipeline(raw_ostream &OS, function_ref< StringRef(StringRef)>) const

Definition VirtRegMap.cpp:775

LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition VirtRegMap.cpp:302

An efficient, type-erasing, non-owning reference to a callable.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

auto reverse(ContainerTy &&C)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

ArrayRef(const T &OneElt) -> ArrayRef< T >

LLVM_ABI char & VirtRegRewriterID

VirtRegRewriter pass.

Definition VirtRegMap.cpp:258

LLVM_ABI FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)

Definition VirtRegMap.cpp:782

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

This struct is a compact representation of a valid (non-zero power of two) alignment.

A special type used by analysis passes to provide an address that identifies that particular analysis...

constexpr bool none() const

constexpr bool any() const