WebAssemblyInstrInfo.cpp Source File (original) (raw)

25using namespace llvm;

27#define DEBUG_TYPE "wasm-instr-info"

29#define GET_INSTRINFO_CTOR_DTOR

30#include "WebAssemblyGenInstrInfo.inc"

33#define GET_INSTRINFO_NAMED_OPS

34#include "WebAssemblyGenInstrInfo.inc"

40 RI(STI.getTargetTriple()) {}

44 switch (MI.getOpcode()) {

45 case WebAssembly::CONST_I32:

46 case WebAssembly::CONST_I64:

47 case WebAssembly::CONST_F32:

48 case WebAssembly::CONST_F64:

51 return true;

52 default:

54 }

55}

60 Register SrcReg, bool KillSrc,

61 bool RenamableDest,

62 bool RenamableSrc) const {

65 auto &MRI = MBB.getParent()->getRegInfo();

68 ? MRI.getRegClass(DestReg)

69 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);

75}

78 MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {

84 return nullptr;

88}

95 bool ) const {

100 if (MFI.isCFGStackified())

101 return true;

102

103 bool HaveCond = false;

105 switch (MI.getOpcode()) {

106 default:

107

108 return true;

109 case WebAssembly::BR_IF:

110 if (HaveCond)

111 return true;

113 Cond.push_back(MI.getOperand(1));

114 TBB = MI.getOperand(0).getMBB();

115 HaveCond = true;

116 break;

117 case WebAssembly::BR_UNLESS:

118 if (HaveCond)

119 return true;

121 Cond.push_back(MI.getOperand(1));

122 TBB = MI.getOperand(0).getMBB();

123 HaveCond = true;

124 break;

125 case WebAssembly::BR:

126 if (!HaveCond)

127 TBB = MI.getOperand(0).getMBB();

128 else

129 FBB = MI.getOperand(0).getMBB();

130 break;

131 }

132 if (MI.isBarrier())

133 break;

134 }

135

136 return false;

137}

138

140 int *BytesRemoved) const {

141 assert(!BytesRemoved && "code size not handled");

142

144 unsigned Count = 0;

145

146 while (I != MBB.instr_begin()) {

147 --I;

148 if (I->isDebugInstr())

149 continue;

150 if (->isTerminator())

151 break;

152

153 I->eraseFromParent();

154 I = MBB.instr_end();

156 }

157

159}

160

164 assert(!BytesAdded && "code size not handled");

165

166 if (Cond.empty()) {

167 if ( TBB )

168 return 0;

169

171 return 1;

172 }

173

174 assert(Cond.size() == 2 && "Expected a flag and a successor block");

175

178 else

180 if (!FBB)

181 return 1;

182

184 return 2;

185}

186

189 assert(Cond.size() == 2 && "Expected a flag and a condition expression");

191 return false;

192}

193

196 static const std::pair<int, const char *> TargetIndices[] = {

202 return ArrayRef(TargetIndices);

203}

204

209

210

211

212

213

214

215

216

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218

219

220

221

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223

224

226 int &Index,

227 int64_t &Offset) const {

228 unsigned Opc = MI.getOpcode();

231 Offset = MI.explicit_uses().begin()->getImm();

232 return true;

233 }

234 return false;

235}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file contains the WebAssembly implementation of the TargetInstrInfo class.

This file provides WebAssembly-specific target descriptions.

This file declares WebAssembly-specific per-machine-function information.

This file declares the WebAssembly-specific subclass of TargetSubtarget.

This file contains the declaration of the WebAssembly-specific utility functions.

This file contains the entry points for global functions defined in the LLVM WebAssembly back-end.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Instructions::iterator instr_iterator

MachineInstrBundleIterator< MachineInstr > iterator

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

static MachineOperand CreateImm(int64_t Val)

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

virtual bool isReMaterializableImpl(const MachineInstr &MI) const

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...

virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const

This method commutes the operands of the given machine instruction MI.

This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...

bool isVRegStackified(Register VReg) const

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Definition WebAssemblyInstrInfo.cpp:187

WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)

Definition WebAssemblyInstrInfo.cpp:36

const MachineOperand & getCalleeOperand(const MachineInstr &MI) const override

Definition WebAssemblyInstrInfo.cpp:206

ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override

Definition WebAssemblyInstrInfo.cpp:195

bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index, int64_t &Offset) const override

Definition WebAssemblyInstrInfo.cpp:225

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition WebAssemblyInstrInfo.cpp:57

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition WebAssemblyInstrInfo.cpp:161

bool isReMaterializableImpl(const MachineInstr &MI) const override

Definition WebAssemblyInstrInfo.cpp:42

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Definition WebAssemblyInstrInfo.cpp:77

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

Definition WebAssemblyInstrInfo.cpp:91

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition WebAssemblyInstrInfo.cpp:139

@ Kill

The last use of a register.

bool isLocalTee(unsigned Opc)

unsigned getCopyOpcodeForRegClass(const TargetRegisterClass *RC)

Returns the appropriate copy opcode for the given register class.

const MachineOperand & getCalleeOp(const MachineInstr &MI)

Returns the operand number of a callee, assuming the argument is a call instruction.

bool isLocalSet(unsigned Opc)

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

FunctionAddr VTableAddr Count

ArrayRef(const T &OneElt) -> ArrayRef< T >