X86FastTileConfig.cpp Source File (original) (raw)

32using namespace llvm;

34#define DEBUG_TYPE "fasttileconfig"

36namespace {

48public:

52 StringRef getPassName() const override {

53 return "Fast Tile Register Configure";

54 }

56 void getAnalysisUsage(AnalysisUsage &AU) const override {

59 }

62 bool runOnMachineFunction(MachineFunction &MFunc) override;

66 }

68 static char ID;

69};

71}

73char X86FastTileConfig::ID = 0;

76 "Fast Tile Register Configure", false, false)

85 if (MI.isDebugInstr() || MI.isCopy() || MI.getNumOperands() < 3 ||

86 .isPseudo())

87 return false;

94 if (Reg.isVirtual()) {

95 if (MRI->getRegClass(Reg)->getID() == X86::TILERegClassID)

96 return true;

97 }

98 if (Reg >= X86::TMM0 && Reg <= X86::TMM7)

99 return true;

100 }

101

102 return false;

103}

104

106 if (Reg >= X86::TMM0 && Reg <= X86::TMM7)

107 return Reg - X86::TMM0;

109}

110

111

112

114 bool Change = false;

117 if ( isTileDef (MRI, MI) && MI.getOpcode() != X86::PLDTILECFGV)

118 continue;

119

120 if (MI.getOpcode() != X86::PLDTILECFGV) {

121 MachineOperand &Row = MI.getOperand(1);

122 unsigned TMMIdx = getTMMIndex(MI.getOperand(0).getReg());

123 MachineOperand &Col = MI.getOperand(2);

124 ShapeInfos.push_back({TMMIdx, ShapeT(&Row, &Col)});

125 } else {

126

127

128 int SS = MI.getOperand(0).getIndex();

129 for (auto &ShapeInfo : ShapeInfos) {

131 unsigned TMMIdx = ShapeInfo.first;

132 Register RowReg = ShapeInfo.second.getRow()->getReg();

133 Register ColReg = ShapeInfo.second.getCol()->getReg();

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150 int RowOffset = 48 + TMMIdx;

151 int ColOffset = 16 + TMMIdx * 2;

152

153 Register SubRowReg = TRI->getSubReg(RowReg, X86::sub_8bit);

155 MachineInstrBuilder StoreRow =

158

159 MachineInstrBuilder StoreCol =

162 }

163 ShapeInfos.clear();

164 Change = true;

165 }

166 }

167

168 return Change;

169}

170

171bool X86FastTileConfig::runOnMachineFunction(MachineFunction &MFunc) {

172 X86FI = MFunc.getInfo();

173

174 if (X86FI->getAMXProgModel() != AMXProgModelEnum::ManagedRA)

175 return false;

176

177 MF = &MFunc;

179 const TargetSubtargetInfo *ST = &MFunc.getSubtarget();

180 TRI = ST->getRegisterInfo();

182 bool Change = false;

183

184

185 for (MachineBasicBlock &MBB : MFunc)

186 Change |= configBasicBlock(MBB);

187

188 return Change;

189}

190

192 return new X86FastTileConfig();

193}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Promote Memory to Register

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

static bool isTileDef(MachineRegisterInfo *MRI, MachineInstr &MI)

static unsigned getTMMIndex(Register Reg)

Definition X86FastTileConfig.cpp:105

Represent the analysis usage information of a pass.

void setPreservesAll()

Set by analyses that do not transform their input at all.

FunctionPass class - This class is used to implement most global optimizations.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Properties which a MachineFunction may have at a given point in time.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

void push_back(const T &Elt)

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...

AMXProgModelEnum getAMXProgModel() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

auto reverse(ContainerTy &&C)

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

FunctionPass * createX86FastTileConfigPass()

Return a pass that config the tile registers after fast reg allocation.

Definition X86FastTileConfig.cpp:191