X86SuppressAPXForReloc.cpp Source File (original) (raw)

30using namespace llvm;

32#define DEBUG_TYPE "x86-suppress-apx-for-relocation"

35 "x86-enable-apx-for-relocation",

36 cl::desc("Enable APX features (EGPR, NDD and NF) for instructions with "

37 "relocations on x86-64 ELF"),

40namespace {

42public:

45 StringRef getPassName() const override {

46 return "X86 Suppress APX features for relocation";

47 }

49 bool runOnMachineFunction(MachineFunction &MF) override;

51 static char ID;

52};

53}

55char X86SuppressAPXForRelocationPass::ID = 0;

58 "X86 Suppress APX features for relocation", false, false)

60 "X86 Suppress APX features for relocation", false, false)

63 return new X86SuppressAPXForRelocationPass();

64}

69 if ( Reg .isVirtual()) {

71 return;

72 }

76 MRI->setRegClass(Reg, NewRC);

77}

89 unsigned int OpNum) {

93 if (Use.getOpcode() == X86::PHI)

95}

99 if (!ST.hasEGPR())

100 return false;

101

103 auto suppressEGPRInInstrWithReloc = [&](MachineInstr &MI,

110 LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "

111 << MI);

112 for (unsigned OpNo : OpNoArray)

115 }

116 };

117

120 unsigned Opcode = MI.getOpcode();

121 switch (Opcode) {

122

123

124

125

126 case X86::TEST32mr:

127 case X86::TEST64mr: {

128 suppressEGPRInInstrWithReloc(MI, {5});

129 break;

130 }

131 case X86::CMP32rm:

132 case X86::CMP64rm:

133 case X86::MOV32rm:

134 case X86::MOV64rm: {

135 suppressEGPRInInstrWithReloc(MI, {0});

136 break;

137 }

138 case X86::ADC32rm:

139 case X86::ADD32rm:

140 case X86::AND32rm:

141 case X86::OR32rm:

142 case X86::SBB32rm:

143 case X86::SUB32rm:

144 case X86::XOR32rm:

145 case X86::ADC64rm:

146 case X86::ADD64rm:

147 case X86::AND64rm:

148 case X86::OR64rm:

149 case X86::SBB64rm:

150 case X86::SUB64rm:

151 case X86::XOR64rm: {

152 suppressEGPRInInstrWithReloc(MI, {0, 1});

153 break;

154 }

155 }

156 }

157 }

158 return true;

159}

160

163 if (!ST.hasNDD() && !ST.hasNF())

164 return false;

165

170 unsigned Opcode = MI.getOpcode();

171 switch (Opcode) {

172 case X86::ADD64rm_NF:

173 case X86::ADD64mr_NF_ND:

174 case X86::ADD64rm_NF_ND: {

180 break;

181 }

182 case X86::ADD64rm_ND: {

188 LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "

189 << MI);

190 Register Reg = MRI->createVirtualRegister(&X86::GR64_NOREX2RegClass);

194 .addReg(MI.getOperand(1).getReg());

195 MI.getOperand(1).setReg(Reg);

197 MI.setDesc(NewDesc);

199 MI.tieOperands(0, 1);

202 }

203 break;

204 }

205 case X86::ADD64mr_ND: {

209 LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "

210 << MI);

212 Register Reg = MRI->createVirtualRegister(&X86::GR64_NOREX2RegClass);

216 .addReg(MI.getOperand(6).getReg());

219 MI.getOperand(0).getReg())

221 .addReg(MI.getOperand(1).getReg())

222 .addImm(MI.getOperand(2).getImm())

223 .addReg(MI.getOperand(3).getReg())

224 .add(MI.getOperand(4))

225 .addReg(MI.getOperand(5).getReg());

227 MI.findRegisterDefOperand(X86::EFLAGS, nullptr);

228 if (FlagDef && FlagDef->isDead()) {

231 if (NewFlagDef)

233 }

234 MI.eraseFromParent();

237 }

238 break;

239 }

240 }

241 }

242 }

243 return true;

244}

245

246bool X86SuppressAPXForRelocationPass::runOnMachineFunction(

249 return false;

250 const X86Subtarget &ST = MF.getSubtarget();

253

255}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

cl::opt< bool > X86EnableAPXForRelocation

static bool handleInstructionWithEGPR(MachineFunction &MF, const X86Subtarget &ST)

Definition X86SuppressAPXForReloc.cpp:97

cl::opt< bool > X86EnableAPXForRelocation("x86-enable-apx-for-relocation", cl::desc("Enable APX features (EGPR, NDD and NF) for instructions with " "relocations on x86-64 ELF"), cl::init(false))

static void suppressEGPRRegClass(MachineRegisterInfo *MRI, MachineInstr &MI, const X86Subtarget &ST, unsigned int OpNum)

Definition X86SuppressAPXForReloc.cpp:66

static void suppressEGPRRegClassInRegAndUses(MachineRegisterInfo *MRI, MachineInstr &MI, const X86Subtarget &ST, unsigned int OpNum)

Definition X86SuppressAPXForReloc.cpp:86

static bool handleNDDOrNFInstructions(MachineFunction &MF, const X86Subtarget &ST)

Definition X86SuppressAPXForReloc.cpp:161

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

FunctionPass class - This class is used to implement most global optimizations.

Describe properties that are true of each instruction in the target description file.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

MachineOperand class - Representation of each machine instruction operand.

void setIsDead(bool Val=true)

unsigned getTargetFlags() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

A Use represents the edge between a Value definition and its users.

const TargetRegisterClass * constrainRegClassToNonRex2(const TargetRegisterClass *RC) const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ MO_GOTTPOFF

MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...

@ MO_GOTPCREL

MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...

int getMemoryOperandNo(uint64_t TSFlags)

bool isApxExtendedReg(MCRegister Reg)

unsigned getOperandBias(const MCInstrDesc &Desc)

Compute whether all of the def operands are repeated in the uses and therefore should be skipped.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createX86SuppressAPXForRelocationPass()

Definition X86SuppressAPXForReloc.cpp:62

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.