X86TileConfig.cpp Source File (original) (raw)

36using namespace llvm;

38#define DEBUG_TYPE "tileconfig"

40namespace {

55 }

62 MachineFunctionProperties::Property::NoPHIs);

63 }

65 static char ID;

66};

68}

70char X86TileConfig::ID = 0;

73 false, false)

79 if (Reg.isVirtual()) {

80 unsigned RegClassID = MRI->getRegClass(Reg)->getID();

81 if (RegClassID == X86::TILERegClassID)

82 return 1;

83 if (RegClassID == X86::TILEPAIRRegClassID)

84 return 2;

85 } else {

86 if (Reg >= X86::TMM0 && Reg <= X86::TMM7)

87 return 1;

88 if (Reg >= X86::TMM0_TMM1 && Reg <= X86::TMM6_TMM7)

89 return 2;

90 }

91 return 0;

92}

99 if (!PhysReg)

100 return;

101

102 if (Num == 1) {

103 unsigned Index = PhysReg - X86::TMM0;

104 if (!Phys2Shapes[Index].isValid()) {

106 Phys2Shapes[Index] = std::move(Shape);

107 return;

108 }

109 }

110

111

112 if (Num == 2) {

113 unsigned Index0 = (PhysReg - X86::TMM0_TMM1) * 2;

114 unsigned Index1 = (PhysReg - X86::TMM0_TMM1) * 2 + 1;

115

118

119 if (!Phys2Shapes[Index0].isValid()) {

121 Phys2Shapes[Index0] = std::move(Shape0);

122 }

123

124 if (!Phys2Shapes[Index1].isValid()) {

126 Phys2Shapes[Index1] = std::move(Shape1);

127 }

128 }

129}

130

133}

134

135bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {

137

138 if (X86FI->getAMXProgModel() != AMXProgModelEnum::ManagedRA)

139 return false;

140

145 LiveIntervals &LIS = getAnalysis().getLIS();

146 VirtRegMap &VRM = getAnalysis().getVRM();

147

149 return false;

150

151 int SS = INT_MAX;

154 if (MI.getOpcode() == X86::PLDTILECFGV) {

155 SS = MI.getOperand(0).getIndex();

156 break;

157 }

158 }

159 if (SS != INT_MAX)

160 break;

161 }

162

163 if (SS == INT_MAX)

164 return false;

165

166

167

168 unsigned ConstPos = 0;

171 if (MI.getOpcode() == X86::MOV8mi && SS == MI.getOperand(0).getIndex()) {

172 ConstMI = &MI;

173 break;

174 }

175 ++ConstPos;

176 }

177 assert(ConstMI && "Cannot find an insertion point");

178

179 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs();

181 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {

183 if (MRI.reg_nodbg_empty(VirtReg))

184 continue;

186 continue;

188 }

189

190

191 for (unsigned I = 0; I < AMXRegNum; ++I) {

192 ShapeT Shape = Phys2Shapes[I];

194 continue;

196 bool IsRow = true;

199

200

201

202

203

204

205

206

207

208

209

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211

212

213

214

216 int Offset = IsRow ? 48 + I : 16 + I * 2;

217 for (auto &DefMI : MRI.def_instructions(R)) {

219 if (DefMI.isMoveImmediate()) {

221

222 assert(Imm == DefMI.getOperand(1).getImm() &&

223 "Cannot initialize with different shapes");

224 continue;

225 }

226 if (DefMI.getOperand(1).isImm()) {

227 Imm = DefMI.getOperand(1).getImm();

228 } else {

229 assert(DefMI.getOpcode() == X86::MOV32r0 &&

230 "The opcode is assumed to be MOV32r0 if the operand is not "

231 "immediate.");

233 }

234

237 TII->get(IsRow ? X86::MOV8mi : X86::MOV16mi)),

240 ConstMI = NewMI;

242 } else {

243 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit;

244 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));

245 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16))

246 SubIdx = 0;

247 auto Iter = DefMI.getIterator();

249 (unsigned)std::distance(MBB.instr_begin(), Iter) < ConstPos)

253 TII->get(IsRow ? X86::MOV8mr : X86::MOV16mr)),

255 .addReg(R, 0, SubIdx);

258 }

259 }

260 IsRow = false;

261 }

262 }

263 return true;

264}

265

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Tile Register false unsigned getAMXRegNum(MachineRegisterInfo *MRI, Register Reg)

static void collectVirtRegShapes(MachineRegisterInfo *MRI, VirtRegMap &VRM, Register VirtReg, SmallVector< ShapeT, 8 > &Phys2Shapes)

static bool isAMXRegClass(MachineRegisterInfo *MRI, Register Reg)

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

void setPreservesAll()

Set by analyses that do not transform their input at all.

FunctionPass class - This class is used to implement most global optimizations.

SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)

LiveInterval & getInterval(Register Reg)

void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)

Extend the live range LR to reach all points in Indices.

Wrapper class representing physical registers. Should be passed by value.

instr_iterator instr_begin()

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

virtual MachineFunctionProperties getRequiredProperties() const

Properties which a MachineFunction may have at a given point in time.

MachineFunctionProperties & set(Property P)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

MachineOperand * getRow(unsigned I=0) const

MachineOperand * getCol(unsigned I=0) const

SlotIndex - An opaque wrapper around machine indexes.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

ShapeT getShape(Register virtReg) const

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

bool isShapeMapEmpty() const

X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...

AMXProgModelEnum getAMXProgModel() const

self_iterator getIterator()

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

FunctionPass * createX86TileConfigPass()

Return a pass that config the tile registers.