XCoreDisassembler.cpp Source File (original) (raw)

26using namespace llvm;

29#define DEBUG_TYPE "xcore-disassembler"

33namespace {

37public:

44};

45}

50 if (Bytes.size() < 2) {

52 return false;

53 }

55 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);

56 return true;

57}

62 if (Bytes.size() < 4) {

64 return false;

65 }

67 Insn =

68 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);

69 return true;

70}

74 return RegInfo->getRegClass(RC).getRegister(RegNo);

75}

100 if (Val > 11)

102 static const unsigned Values[] = {

103 32 , 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32

104 };

107}

108

115

119 if (Combined < 27)

122 if (Combined == 31)

124 Combined += 5;

125 }

126 Combined -= 27;

127 unsigned Op1High = Combined % 3;

128 unsigned Op2High = Combined / 3;

132}

133

136 unsigned &Op3) {

138 if (Combined >= 27)

140

141 unsigned Op1High = Combined % 3;

142 unsigned Op2High = (Combined / 3) % 3;

143 unsigned Op3High = Combined / 9;

148}

149

153 unsigned Op1, Op2, Op3;

159 }

160 return S;

161}

162

166 unsigned Op1, Op2, Op3;

172 }

173 return S;

174}

175

179 unsigned Op1, Op2, Op3;

185 }

186 return S;

187}

188

192 unsigned Op1, Op2, Op3;

198 }

199 return S;

200}

201

205 unsigned Op1, Op2, Op3;

212 }

213 return S;

214}

215

219 unsigned Op1, Op2, Op3;

227 }

228 return S;

229}

230

234 unsigned Op1, Op2, Op3;

241 }

242 return S;

243}

244

248 unsigned Op1, Op2, Op3;

255 }

256 return S;

257}

258

259

263

265 switch (Opcode) {

266 case 0x0:

269 case 0x1:

272 case 0x2:

275 case 0x3:

278 case 0x4:

281 case 0x5:

284 case 0x6:

287 case 0x7:

290 case 0x8:

293 case 0x9:

296 case 0x10:

299 case 0x11:

302 case 0x12:

305 case 0x13:

308 case 0x14:

311 case 0x15:

314 case 0x16:

317 case 0x17:

320 case 0x18:

323 case 0x19:

326 }

328}

329

333 unsigned Op1, Op2;

337

340 return S;

341}

342

346 unsigned Op1, Op2;

350

353 return S;

354}

355

359 unsigned Op1, Op2;

363

366 return S;

367}

368

372 unsigned Op1, Op2;

376

380 return S;

381}

382

386 unsigned Op1, Op2;

390

393 return S;

394}

395

399 unsigned Op1, Op2;

403

406 return S;

407}

408

412 unsigned Op1, Op2;

416

420 return S;

421}

422

426

429 switch (Opcode) {

430 case 0x0c:

433 case 0x1c:

436 case 0x2c:

439 case 0x3c:

440 Inst.setOpcode(XCore::LDAWF_l3r);

442 case 0x4c:

443 Inst.setOpcode(XCore::LDAWB_l3r);

445 case 0x5c:

446 Inst.setOpcode(XCore::LDA16F_l3r);

448 case 0x6c:

449 Inst.setOpcode(XCore::LDA16B_l3r);

451 case 0x7c:

454 case 0x8c:

457 case 0x9c:

460 case 0x10c:

463 case 0x11c:

466 case 0x12c:

467 Inst.setOpcode(XCore::ASHR_l2rus);

469 case 0x12d:

470 Inst.setOpcode(XCore::OUTPW_l2rus);

472 case 0x12e:

473 Inst.setOpcode(XCore::INPW_l2rus);

475 case 0x13c:

476 Inst.setOpcode(XCore::LDAWF_l2rus);

478 case 0x14c:

479 Inst.setOpcode(XCore::LDAWB_l2rus);

481 case 0x15c:

484 case 0x18c:

487 case 0x19c:

490 }

492}

493

497 unsigned Op1, Op2;

499 Op1, Op2);

502

505 return S;

506}

507

511 unsigned Op1, Op2;

513 Op1, Op2);

516

519 return S;

520}

521

525 unsigned Op1, Op2, Op3, Op4, Op5, Op6;

529 return S;

532 return S;

539 return S;

540}

541

545

548 switch (Opcode) {

549 case 0x00:

552 }

554}

555

559 unsigned Op1, Op2, Op3, Op4, Op5;

567

573 return S;

574}

575

579 unsigned Op1, Op2, Op3;

586 }

591 }

592 return S;

593}

594

598 unsigned Op1, Op2, Op3;

605 }

611 }

612 return S;

613}

614

615#include "XCoreGenDisassemblerTables.inc"

616

621 uint16_t insn16;

622

625 }

626

627

630 if (Result != Fail) {

633 }

634

635 uint32_t insn32;

636

639 }

640

641

642 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);

643 if (Result != Fail) {

646 }

647

649}

650

654 return new XCoreDisassembler(STI, Ctx);

655}

656

MCDisassembler::DecodeStatus DecodeStatus

static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

#define LLVM_EXTERNAL_VISIBILITY

static MCDisassembler * createXCoreDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition XCoreDisassembler.cpp:651

static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:189

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreDisassembler()

Definition XCoreDisassembler.cpp:658

static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:245

static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:383

static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:508

static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:596

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

Definition XCoreDisassembler.cpp:72

static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:410

static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:231

static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:576

static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:97

static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:202

static DecodeStatus DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:423

static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:176

static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:216

static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:556

static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:356

static DecodeStatus Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3)

Definition XCoreDisassembler.cpp:135

static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:494

static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:163

static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:343

static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:87

static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:77

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

Definition XCoreDisassembler.cpp:59

static DecodeStatus DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:542

static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:369

static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:396

static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:522

static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:260

static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2)

Definition XCoreDisassembler.cpp:117

static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:109

static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:330

static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint16_t &Insn)

Definition XCoreDisassembler.cpp:47

static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition XCoreDisassembler.cpp:150

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

Target - Wrapper for Target specific information.

This class implements an extremely fast bulk output stream that can only output to a stream.

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheXCoreTarget()

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.