XCoreInstrInfo.cpp Source File (original) (raw)

24using namespace llvm;

26#define GET_INSTRINFO_CTOR_DTOR

27#include "XCoreGenInstrInfo.inc"

29namespace llvm {

30namespace XCore {

38}

39}

42void XCoreInstrInfo::anchor() {}

45 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),

46 RI() {

47}

50 return op.isImm() && op.getImm() == 0;

51}

59 int &FrameIndex) const {

60 int Opcode = MI.getOpcode();

61 if (Opcode == XCore::LDWFI)

62 {

63 if ((MI.getOperand(1).isFI()) &&

64 (MI.getOperand(2).isImm()) &&

66 FrameIndex = MI.getOperand(1).getIndex();

67 return MI.getOperand(0).getReg();

68 }

69 }

70 return 0;

71}

79 int &FrameIndex) const {

80 int Opcode = MI.getOpcode();

81 if (Opcode == XCore::STWFI)

82 {

83 if ((MI.getOperand(1).isFI()) &&

84 (MI.getOperand(2).isImm()) &&

86 FrameIndex = MI.getOperand(1).getIndex();

87 return MI.getOperand(0).getReg();

88 }

89 }

90 return 0;

91}

97static inline bool IsBRU(unsigned BrOpc) {

98 return BrOpc == XCore::BRFU_u6

99 || BrOpc == XCore::BRFU_lu6

100 || BrOpc == XCore::BRBU_u6

101 || BrOpc == XCore::BRBU_lu6;

102}

103

104static inline bool IsBRT(unsigned BrOpc) {

105 return BrOpc == XCore::BRFT_ru6

106 || BrOpc == XCore::BRFT_lru6

107 || BrOpc == XCore::BRBT_ru6

108 || BrOpc == XCore::BRBT_lru6;

109}

110

111static inline bool IsBRF(unsigned BrOpc) {

112 return BrOpc == XCore::BRFF_ru6

113 || BrOpc == XCore::BRFF_lru6

114 || BrOpc == XCore::BRBF_ru6

115 || BrOpc == XCore::BRBF_lru6;

116}

117

120}

121

122static inline bool IsBR_JT(unsigned BrOpc) {

123 return BrOpc == XCore::BR_JT

124 || BrOpc == XCore::BR_JT32;

125}

126

127

128

130{

131 if (IsBRT(BrOpc)) {

133 } else if (IsBRF(BrOpc)) {

135 } else {

137 }

138}

139

140

141

143{

144 switch (CC) {

148 }

149}

150

151

152

154{

155 switch (CC) {

159 }

160}

161

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184

189 bool AllowModify) const {

190

193 return false;

194

195 if (!isUnpredicatedTerminator(*I))

196 return false;

197

198

200

201

202 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {

205 return false;

206 }

207

210 return true;

211

212

213

214

218 return false;

219 }

220

221

223

224

225 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))

226 return true;

227

228 unsigned SecondLastOpc = SecondLastInst->getOpcode();

230

231

232

235

239

241 return false;

242 }

243

244

245

249 I = LastInst;

250 if (AllowModify)

251 I->eraseFromParent();

252 return false;

253 }

254

255

257 I = LastInst;

258 if (AllowModify)

259 I->eraseFromParent();

260 return true;

261 }

262

263

264 return true;

265}

266

272 int *BytesAdded) const {

273

274 assert(TBB && "insertBranch must not be told to insert a fallthrough");

276 "Unexpected number of components!");

277 assert(!BytesAdded && "code size not handled");

278

279 if (!FBB) {

280 if (Cond.empty()) {

281

283 } else {

284

288 }

289 return 1;

290 }

291

292

293 assert(Cond.size() == 2 && "Unexpected number of components!");

298 return 2;

299}

300

301unsigned

303 assert(!BytesRemoved && "code size not handled");

304

307 return 0;

308

310 return 0;

311

312

313 I->eraseFromParent();

314

316

318 --I;

320 return 1;

321

322

323 I->eraseFromParent();

324 return 2;

325}

326

331 bool RenamableDest, bool RenamableSrc) const {

332 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);

333 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);

334

335 if (GRDest && GRSrc) {

339 return;

340 }

341

342 if (GRDest && SrcReg == XCore::SP) {

344 return;

345 }

346

347 if (DestReg == XCore::SP && GRSrc) {

350 return;

351 }

353}

354

360 if (I != MBB.end() && ->isDebugInstr())

361 DL = I->getDebugLoc();

373}

374

377 Register DestReg, int FrameIndex,

382 if (I != MBB.end() && ->isDebugInstr())

383 DL = I->getDebugLoc();

394}

395

399 "Invalid XCore branch condition!");

401 return false;

402}

403

404static inline bool isImmU6(unsigned val) {

405 return val < (1 << 6);

406}

407

408static inline bool isImmU16(unsigned val) {

409 return val < (1 << 16);

410}

411

414 return false;

415 }

417 return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;

418}

419

425 if (MI != MBB.end() && ->isDebugInstr())

426 dl = MI->getDebugLoc();

432 }

434 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;

436 }

438 const Constant *C = ConstantInt::get(

444}

static bool isZeroImm(const MachineOperand &Op)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...

unsigned const TargetRegisterInfo * TRI

static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)

static bool isImmU16(unsigned val)

static bool isImmU6(unsigned val)

static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)

GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode.

static bool IsBRU(unsigned BrOpc)

static bool IsBR_JT(unsigned BrOpc)

static bool isImmMskBitp(unsigned val)

static bool IsBRT(unsigned BrOpc)

static bool IsBRF(unsigned BrOpc)

static bool IsCondBranch(unsigned BrOpc)

static unsigned GetCondBranchFromCond(XCore::CondCode CC)

GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This is an important base class in LLVM.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

Wrapper class representing physical registers. Should be passed by value.

iterator getLastNonDebugInstr(bool SkipPseudoOp=true)

Returns an iterator to the last non-debug instruction in the basic block, or end().

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Function & getFunction()

Return the LLVM function that this machine code represents.

MachineConstantPool * getConstantPool()

getConstantPool - Return the constant pool object for the current function.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

MachineBasicBlock * getMBB() const

static MachineOperand CreateImm(int64_t Val)

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

static IntegerType * getInt32Ty(LLVMContext &C)

LLVM Value Representation.

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...

MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isMask_32(uint32_t Value)

Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...

int bit_width(T Value)

Returns the number of bits needed to represent Value if Value is nonzero.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getKillRegState(bool B)

This struct is a compact representation of a valid (non-zero power of two) alignment.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.