XCoreRegisterInfo.cpp Source File (original) (raw)

31using namespace llvm;

33#define DEBUG_TYPE "xcore-reg-info"

35#define GET_REGINFO_TARGET_DESC

36#include "XCoreGenRegisterInfo.inc"

43static inline bool isImmUs(unsigned val) {

44 return val <= 11;

45}

47static inline bool isImmU6(unsigned val) {

48 return val < (1 << 6);

49}

51static inline bool isImmU16(unsigned val) {

52 return val < (1 << 16);

53}

58 unsigned Reg, unsigned FrameReg, int Offset ) {

63 switch (MI.getOpcode()) {

64 case XCore::LDWFI:

69 break;

70 case XCore::STWFI:

76 break;

77 case XCore::LDAWFI:

81 break;

82 default:

84 }

85}

89 unsigned Reg, unsigned FrameReg,

91 assert(RS && "requiresRegisterScavenging failed");

96 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0);

97 RS->setRegUsed(ScratchOffset);

100 switch (MI.getOpcode()) {

101 case XCore::LDWFI:

106 break;

107 case XCore::STWFI:

113 break;

114 case XCore::LDAWFI:

118 break;

119 default:

121 }

122}

123

131

132 switch (MI.getOpcode()) {

133 int NewOpcode;

134 case XCore::LDWFI:

135 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;

139 break;

140 case XCore::STWFI:

141 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;

146 break;

147 case XCore::LDAWFI:

148 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;

151 break;

152 default:

154 }

155}

156

160 assert(RS && "requiresRegisterScavenging failed");

164 unsigned OpCode = MI.getOpcode();

165

166 unsigned ScratchBase;

167 if (OpCode==XCore::STWFI) {

168 ScratchBase =

169 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0);

170 RS->setRegUsed(ScratchBase);

171 } else

172 ScratchBase = Reg;

175 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0);

176 RS->setRegUsed(ScratchOffset);

178

179 switch (OpCode) {

180 case XCore::LDWFI:

185 break;

186 case XCore::STWFI:

192 break;

193 case XCore::LDAWFI:

197 break;

198 default:

200 }

201}

202

206

209

210

211 static const MCPhysReg CalleeSavedRegs[] = {

212 XCore::R4, XCore::R5, XCore::R6, XCore::R7,

213 XCore::R8, XCore::R9, XCore::R10,

214 0

215 };

216 static const MCPhysReg CalleeSavedRegsFP[] = {

217 XCore::R4, XCore::R5, XCore::R6, XCore::R7,

218 XCore::R8, XCore::R9,

219 0

220 };

222 if (TFI->hasFP(*MF))

223 return CalleeSavedRegsFP;

224 return CalleeSavedRegs;

225}

226

230

235 if (TFI->hasFP(MF)) {

237 }

239}

240

241bool

245

246bool

250

251bool

253 int SPAdj, unsigned FIOperandNum,

255 assert(SPAdj == 0 && "Unexpected");

258 int FrameIndex = FrameOp.getIndex();

259

263

267

268 #ifndef NDEBUG

272 LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");

274 LLVM_DEBUG(errs() << "StackSize : " << StackSize << "\n");

275#endif

276

278

280

281

282 if (MI.isDebugValue()) {

283 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false );

284 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);

285 return false;

286 }

287

288

289 Offset += MI.getOperand(FIOperandNum + 1).getImm();

290 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);

291

292 assert(Offset%4 == 0 && "Misaligned stack offset");

294 << "<--------->\n");

296

297 Register Reg = MI.getOperand(0).getReg();

298 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");

299

300 if (TFI->hasFP(MF)) {

303 else

305 } else {

308 else

310 }

311

314 return true;

315}

316

317

320

321 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;

322}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file implements the BitVector class.

uint64_t IntrinsicInst * II

This file declares the machine register scavenger class.

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

static bool isImmU16(unsigned val)

static bool isImmU6(unsigned val)

static bool isImmUs(int64_t val)

static void InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS)

Definition XCoreRegisterInfo.cpp:87

static void InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset)

Definition XCoreRegisterInfo.cpp:124

static void InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset)

Definition XCoreRegisterInfo.cpp:56

static void InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS)

Definition XCoreRegisterInfo.cpp:157

MachineInstrBundleIterator< MachineInstr > iterator

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

bool needsFrameMoves() const

True if this function needs frame moves for debug or exceptions.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

Wrapper class representing virtual and physical registers.

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Kill

The last use of a register.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

unsigned getKillRegState(bool B)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

bool requiresRegisterScavenging(const MachineFunction &MF) const override

Definition XCoreRegisterInfo.cpp:242

bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

Definition XCoreRegisterInfo.cpp:252

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

Code Generation virtual methods...

Definition XCoreRegisterInfo.cpp:208

static bool needsFrameMoves(const MachineFunction &MF)

Return whether to emit frame moves.

Definition XCoreRegisterInfo.cpp:203

Definition XCoreRegisterInfo.cpp:318

XCoreRegisterInfo()

Definition XCoreRegisterInfo.cpp:38

bool useFPForScavengingIndex(const MachineFunction &MF) const override

Definition XCoreRegisterInfo.cpp:247

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition XCoreRegisterInfo.cpp:227