XtensaISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H

15#define LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H

21namespace llvm {

26public:

31 return LHSTy.getSizeInBits() <= 32 ? MVT::i32 : MVT::i64;

32 }

35 EVT VT) const override;

38 EVT VT) const override {

40 return MVT::i32;

42 }

47 bool ForCodeSize) const override;

49 std::pair<unsigned, const TargetRegisterClass *>

58 const char *Constraint) const override;

61 std::vector &Ops,

67 bool isVarArg,

76 bool isVarArg,

100private:

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

147};

148

149}

150

151#endif

static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Analysis containing CSE Info

static Value * LowerCTPOP(LLVMContext &Context, Value *V, Instruction *IP)

Emit the code to lower ctpop of V before the specified instruction IP.

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)

static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)

static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)

static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)

This file describes how to lower LLVM code to machine code.

static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

an instruction that atomically reads a memory location, combines it with another value,...

A parsed version of the target data layout string in and methods for querying it.

This is an important class for using LLVM in a threaded context.

Representation of each machine instruction.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

Definition XtensaISelLowering.h:85

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override

Examine constraint string and operand type and determine a weight value.

TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override

Given a constraint, return the type of constraint it is for this target.

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override

Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...

MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition XtensaISelLowering.h:30

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

EVT getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const override

Return the ValueType of the result of SETCC operations.

Definition XtensaISelLowering.h:37

SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI)

AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

const XtensaSubtarget & getSubtarget() const

Definition XtensaISelLowering.h:94

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Return the register type for a given MVT.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

DWARFExpression::Operation Op

EVT changeVectorElementTypeToInteger() const

Return a vector with the same number of elements as this vector, but with the element type converted ...

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

bool isVector() const

Return true if this is a vector value type.