XtensaInstrInfo.cpp Source File (original) (raw)

25#define GET_INSTRINFO_CTOR_DTOR

26#include "XtensaGenInstrInfo.inc"

28using namespace llvm;

37 if (MCID.mayLoad())

39 if (MCID.mayStore())

48}

52 Xtensa::ADJCALLSTACKUP),

53 RI(STI), STI(STI) {}

56 int &FrameIndex) const {

57 if (MI.getOpcode() == Xtensa::L32I) {

58 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&

59 MI.getOperand(2).getImm() == 0) {

60 FrameIndex = MI.getOperand(1).getIndex();

61 return MI.getOperand(0).getReg();

62 }

63 }

65}

68 int &FrameIndex) const {

69 if (MI.getOpcode() == Xtensa::S32I) {

70 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&

71 MI.getOperand(2).getImm() == 0) {

72 FrameIndex = MI.getOperand(1).getIndex();

73 return MI.getOperand(0).getReg();

74 }

75 }

77}

85 if (Amount == 0)

86 return;

92 MCRegister Reg = RegInfo.createVirtualRegister(RC);

94 if (isInt<8>(Amount)) {

96 } else {

102 }

103

104 if (STI.isWindowedABI()) {

106 } else {

110 }

111}

112

116 Register SrcReg, bool KillSrc,

117 bool RenamableDest, bool RenamableSrc) const {

118 unsigned Opcode;

119

120

121

122 if (Xtensa::ARRegClass.contains(DestReg, SrcReg)) {

126 return;

127 }

128

129 if (STI.hasSingleFloat() && Xtensa::FPRRegClass.contains(SrcReg) &&

130 Xtensa::FPRRegClass.contains(DestReg))

131 Opcode = Xtensa::MOV_S;

132 else if (STI.hasSingleFloat() && Xtensa::FPRRegClass.contains(SrcReg) &&

133 Xtensa::ARRegClass.contains(DestReg))

134 Opcode = Xtensa::RFR;

135 else if (STI.hasSingleFloat() && Xtensa::ARRegClass.contains(SrcReg) &&

136 Xtensa::FPRRegClass.contains(DestReg))

137 Opcode = Xtensa::WFR;

138 else

140

143}

144

148

151 unsigned LoadOpcode, StoreOpcode;

156}

157

160 Register DestReg, int FrameIdx,

165 unsigned LoadOpcode, StoreOpcode;

168}

169

171 unsigned &LoadOpcode,

172 unsigned &StoreOpcode,

173 int64_t offset) const {

174 if (RC == &Xtensa::ARRegClass) {

175 LoadOpcode = Xtensa::L32I;

176 StoreOpcode = Xtensa::S32I;

177 } else if (RC == &Xtensa::FPRRegClass) {

178 LoadOpcode = Xtensa::LSI;

179 StoreOpcode = Xtensa::SSI;

180 } else {

182 }

183}

184

191

192

193 *Reg = RegInfo.createVirtualRegister(RC);

194 if (Value >= -2048 && Value <= 2047) {

196 } else if (Value >= -32768 && Value <= 32767) {

199

202 } else if (Value >= -4294967296LL && Value <= 4294967295LL) {

203

206 const Constant *CVal = ConstantInt::get(

208 false);

210

212 } else {

213

214

216 }

217}

218

220 switch (MI.getOpcode()) {

221 case TargetOpcode::INLINEASM: {

223 const char *AsmStr = MI.getOperand(0).getSymbolName();

225 }

226 default:

227 return MI.getDesc().getSize();

228 }

229}

230

233 assert(Cond.size() <= 4 && "Invalid branch condition!");

234

236 case Xtensa::BEQ:

237 Cond[0].setImm(Xtensa::BNE);

238 return false;

239 case Xtensa::BNE:

240 Cond[0].setImm(Xtensa::BEQ);

241 return false;

242 case Xtensa::BLT:

243 Cond[0].setImm(Xtensa::BGE);

244 return false;

245 case Xtensa::BGE:

246 Cond[0].setImm(Xtensa::BLT);

247 return false;

248 case Xtensa::BLTU:

249 Cond[0].setImm(Xtensa::BGEU);

250 return false;

251 case Xtensa::BGEU:

252 Cond[0].setImm(Xtensa::BLTU);

253 return false;

254 case Xtensa::BEQI:

255 Cond[0].setImm(Xtensa::BNEI);

256 return false;

257 case Xtensa::BNEI:

258 Cond[0].setImm(Xtensa::BEQI);

259 return false;

260 case Xtensa::BGEI:

261 Cond[0].setImm(Xtensa::BLTI);

262 return false;

263 case Xtensa::BLTI:

264 Cond[0].setImm(Xtensa::BGEI);

265 return false;

266 case Xtensa::BGEUI:

267 Cond[0].setImm(Xtensa::BLTUI);

268 return false;

269 case Xtensa::BLTUI:

270 Cond[0].setImm(Xtensa::BGEUI);

271 return false;

272 case Xtensa::BEQZ:

273 Cond[0].setImm(Xtensa::BNEZ);

274 return false;

275 case Xtensa::BNEZ:

276 Cond[0].setImm(Xtensa::BEQZ);

277 return false;

278 case Xtensa::BLTZ:

279 Cond[0].setImm(Xtensa::BGEZ);

280 return false;

281 case Xtensa::BGEZ:

282 Cond[0].setImm(Xtensa::BLTZ);

283 return false;

284 case Xtensa::BF:

285 Cond[0].setImm(Xtensa::BT);

286 return false;

287 case Xtensa::BT:

288 Cond[0].setImm(Xtensa::BF);

289 return false;

290 default:

292 }

293}

294

297 unsigned OpCode = MI.getOpcode();

298 switch (OpCode) {

299 case Xtensa::BR_JT:

300 case Xtensa::JX:

301 return nullptr;

302 case Xtensa::J:

303 return MI.getOperand(0).getMBB();

304 case Xtensa::BEQ:

305 case Xtensa::BNE:

306 case Xtensa::BLT:

307 case Xtensa::BLTU:

308 case Xtensa::BGE:

309 case Xtensa::BGEU:

310 return MI.getOperand(2).getMBB();

311 case Xtensa::BEQI:

312 case Xtensa::BNEI:

313 case Xtensa::BLTI:

314 case Xtensa::BLTUI:

315 case Xtensa::BGEI:

316 case Xtensa::BGEUI:

317 return MI.getOperand(2).getMBB();

318 case Xtensa::BEQZ:

319 case Xtensa::BNEZ:

320 case Xtensa::BLTZ:

321 case Xtensa::BGEZ:

322 return MI.getOperand(1).getMBB();

323 case Xtensa::BT:

324 case Xtensa::BF:

325 return MI.getOperand(1).getMBB();

326 default:

328 }

329}

330

332 int64_t BrOffset) const {

333 switch (BranchOp) {

334 case Xtensa::J:

335 BrOffset -= 4;

336 return isIntN(18, BrOffset);

337 case Xtensa::JX:

338 return true;

339 case Xtensa::BR_JT:

340 return true;

341 case Xtensa::BEQ:

342 case Xtensa::BNE:

343 case Xtensa::BLT:

344 case Xtensa::BLTU:

345 case Xtensa::BGE:

346 case Xtensa::BGEU:

347 case Xtensa::BEQI:

348 case Xtensa::BNEI:

349 case Xtensa::BLTI:

350 case Xtensa::BLTUI:

351 case Xtensa::BGEI:

352 case Xtensa::BGEUI:

353 BrOffset -= 4;

354 return isIntN(8, BrOffset);

355 case Xtensa::BEQZ:

356 case Xtensa::BNEZ:

357 case Xtensa::BLTZ:

358 case Xtensa::BGEZ:

359 BrOffset -= 4;

360 return isIntN(12, BrOffset);

361 case Xtensa::BT:

362 case Xtensa::BF:

363 BrOffset -= 4;

364 return isIntN(8, BrOffset);

365 default:

367 }

368}

369

374 bool AllowModify = false) const {

375

376

377

378

380 while (I != MBB.begin()) {

381 --I;

382 if (I->isDebugValue())

383 continue;

384

385

386

387 if (!isUnpredicatedTerminator(*I))

388 break;

389

390

391

395 if ( isBranch (I, ThisCond, ThisTarget))

396 return true;

397

398

399 if (!ThisTarget->isMBB())

400 return true;

401

402 if (ThisCond[0].getImm() == Xtensa::J) {

403

404 if (!AllowModify) {

406 continue;

407 }

408

409

410 while (std::next(I) != MBB.end())

411 std::next(I)->eraseFromParent();

412

413 Cond.clear();

414 FBB = 0;

415

416

418 continue;

419 }

420

421

422 if (Cond.empty()) {

423

424 FBB = TBB;

427

428

429 for (unsigned int i = 0; i < (I->getNumExplicitOperands() - 1); i++)

430 Cond.push_back(I->getOperand(i));

431

432 continue;

433 }

434

435

438

439

440

442 return true;

443

444

445 unsigned OldCond = Cond[0].getImm();

446 if (OldCond == ThisCond[0].getImm())

447 continue;

448 }

449

450 return false;

451}

452

454 int *BytesRemoved) const {

455

457 unsigned Count = 0;

458 if (BytesRemoved)

459 *BytesRemoved = 0;

460

461 while (I != MBB.begin()) {

462 --I;

467 break;

468 if ( Target ->isMBB())

469 break;

470

471 if (BytesRemoved)

473 I->eraseFromParent();

474 I = MBB.end();

476 }

478}

479

483 unsigned Count = 0;

484 if (BytesAdded)

485 *BytesAdded = 0;

486 if (FBB) {

487

488

489

493 if (BytesAdded)

496 }

497

500}

501

505 const DebugLoc &DL, int64_t BrOffset,

507 assert(RS && "RegScavenger required for long branching");

509 "new block should be inserted for expanding unconditional branch");

511

517

520 "Branch offsets outside of the signed 32-bit range not supported");

521

522 Register ScratchReg = MRI.createVirtualRegister(&Xtensa::ARRegClass);

523 auto II = MBB.end();

524

525

526

529

530 RS->enterBasicBlockEnd(MBB);

532 RS->scavengeRegisterBackwards(Xtensa::ARRegClass, L32R.getIterator(),

533 false, 0,

534 false);

535 if (ScavRegister != Xtensa::NoRegister)

536 RS->setRegUsed(ScavRegister);

537 else {

538

539

540 ScavRegister = Xtensa::A12;

541

542 int FrameIndex = XtensaFI->getBranchRelaxationScratchFrameIndex();

543 if (FrameIndex == -1)

545 "Unable to properly handle scavenged register for indirect jump, "

546 "function code size is significantly larger than estimated");

547

549 &Xtensa::ARRegClass, Register());

550 RI.eliminateFrameIndex(std::prev(L32R.getIterator()),

551 0, 1);

552

554 &Xtensa::ARRegClass, Register());

555 RI.eliminateFrameIndex(RestoreBB.back(),

556 0, 1);

557 JumpToMBB = &RestoreBB;

558 }

559

560 unsigned LabelId = XtensaFI->createCPLabelId();

561

566

567 MRI.replaceRegWith(ScratchReg, ScavRegister);

568 MRI.clearVirtRegs();

569}

570

575 "Xtensa branch conditions have less than four components!");

576

577 if (Cond.empty() || (Cond[0].getImm() == Xtensa::J)) {

578

580 if (BytesAdded && MI)

582 return 1;

583 }

584

585 unsigned Count = 0;

586 unsigned BR_C = Cond[0].getImm();

588 switch (BR_C) {

589 case Xtensa::BEQ:

590 case Xtensa::BNE:

591 case Xtensa::BLT:

592 case Xtensa::BLTU:

593 case Xtensa::BGE:

594 case Xtensa::BGEU:

599 break;

600 case Xtensa::BEQI:

601 case Xtensa::BNEI:

602 case Xtensa::BLTI:

603 case Xtensa::BLTUI:

604 case Xtensa::BGEI:

605 case Xtensa::BGEUI:

610 break;

611 case Xtensa::BEQZ:

612 case Xtensa::BNEZ:

613 case Xtensa::BLTZ:

614 case Xtensa::BGEZ:

616 break;

617 case Xtensa::BT:

618 case Xtensa::BF:

620 break;

621 default:

623 }

624 if (BytesAdded && MI)

628}

629

635 int *BytesAdded) const {

636

637 assert(TBB && "InsertBranch must not be told to insert a fallthrough");

639 "Xtensa branch conditions have less than four components!");

640

641 if (Cond.empty() || (Cond[0].getImm() == Xtensa::J)) {

642

644 if (BytesAdded && MI)

646 return 1;

647 }

648

649 unsigned Count = 0;

650 unsigned BR_C = Cond[0].getImm();

652 switch (BR_C) {

653 case Xtensa::BEQ:

654 case Xtensa::BNE:

655 case Xtensa::BLT:

656 case Xtensa::BLTU:

657 case Xtensa::BGE:

658 case Xtensa::BGEU:

663 break;

664 case Xtensa::BEQI:

665 case Xtensa::BNEI:

666 case Xtensa::BLTI:

667 case Xtensa::BLTUI:

668 case Xtensa::BGEI:

669 case Xtensa::BGEUI:

674 break;

675 case Xtensa::BEQZ:

676 case Xtensa::BNEZ:

677 case Xtensa::BLTZ:

678 case Xtensa::BGEZ:

680 break;

681 case Xtensa::BT:

682 case Xtensa::BF:

684 break;

685 default:

687 }

688 if (BytesAdded && MI)

692}

693

697 unsigned OpCode = MI->getOpcode();

698 switch (OpCode) {

699 case Xtensa::J:

700 case Xtensa::JX:

701 case Xtensa::BR_JT:

702 Cond[0].setImm(OpCode);

704 return true;

705 case Xtensa::BEQ:

706 case Xtensa::BNE:

707 case Xtensa::BLT:

708 case Xtensa::BLTU:

709 case Xtensa::BGE:

710 case Xtensa::BGEU:

711 Cond[0].setImm(OpCode);

713 return true;

714

715 case Xtensa::BEQI:

716 case Xtensa::BNEI:

717 case Xtensa::BLTI:

718 case Xtensa::BLTUI:

719 case Xtensa::BGEI:

720 case Xtensa::BGEUI:

721 Cond[0].setImm(OpCode);

723 return true;

724

725 case Xtensa::BEQZ:

726 case Xtensa::BNEZ:

727 case Xtensa::BLTZ:

728 case Xtensa::BGEZ:

729 Cond[0].setImm(OpCode);

731 return true;

732

733 case Xtensa::BT:

734 case Xtensa::BF:

735 Cond[0].setImm(OpCode);

737 return true;

738

739 default:

740 assert(->getDesc().isBranch() && "Unknown branch opcode");

741 return false;

742 }

743}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...

Promote Memory to Register

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

uint64_t IntrinsicInst * II

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file declares the machine register scavenger class.

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This is an important base class in LLVM.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

Describe properties that are true of each instruction in the target description file.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...

unsigned getConstantPoolIndex(const Constant *C, Align Alignment)

getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

MachineConstantPool * getConstantPool()

getConstantPool - Return the constant pool object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

LLVM_ABI void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

A description of a memory reference used in the backend.

Flags

Flags values. These may be or'd together.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

MachineBasicBlock * getMBB() const

static MachineOperand CreateImm(int64_t Val)

static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)

bool isMBB() const

isMBB - Tests if this is a MO_MachineBasicBlock operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

Target - Wrapper for Target specific information.

static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)

LLVM Value Representation.

static XtensaConstantPoolMBB * Create(LLVMContext &C, const MachineBasicBlock *M, unsigned ID)

XtensaConstantPoolValue - Xtensa specific constantpool value.

bool isBranch(const MachineBasicBlock::iterator &MI, SmallVectorImpl< MachineOperand > &Cond, const MachineOperand *&Target) const

Definition XtensaInstrInfo.cpp:694

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition XtensaInstrInfo.cpp:113

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition XtensaInstrInfo.cpp:453

Definition XtensaInstrInfo.cpp:67

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

Definition XtensaInstrInfo.cpp:331

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

Definition XtensaInstrInfo.cpp:219

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Definition XtensaInstrInfo.cpp:231

void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const override

Definition XtensaInstrInfo.cpp:502

void adjustStackPtr(MCRegister SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const

Adjust SP by Amount bytes.

Definition XtensaInstrInfo.cpp:80

Definition XtensaInstrInfo.cpp:55

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition XtensaInstrInfo.cpp:158

unsigned insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I, int64_t offset, ArrayRef< MachineOperand > Cond, DebugLoc DL, int *BytesAdded) const

Definition XtensaInstrInfo.cpp:571

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition XtensaInstrInfo.cpp:145

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition XtensaInstrInfo.cpp:480

unsigned insertBranchAtInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded) const

Definition XtensaInstrInfo.cpp:630

MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override

Definition XtensaInstrInfo.cpp:296

XtensaInstrInfo(const XtensaSubtarget &STI)

Definition XtensaInstrInfo.cpp:50

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Definition XtensaInstrInfo.cpp:370

void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode, int64_t offset) const

Definition XtensaInstrInfo.cpp:170

void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MCRegister *Reg, int64_t Value) const

Definition XtensaInstrInfo.cpp:185

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

@ Kill

The last use of a register.

This is an optimization pass for GlobalISel generic memory operations.

@ Low

Lower the current thread's priority such that it does not affect foreground tasks significantly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

FunctionAddr VTableAddr Count

unsigned getKillRegState(bool B)

constexpr bool isIntN(unsigned N, int64_t x)

Checks if an signed integer fits into the given (dynamic) bit width.

This struct is a compact representation of a valid (non-zero power of two) alignment.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.