LLVM: lib/Target/Xtensa/XtensaInstrInfo.h Source File (original) (raw)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H

16#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H

17

22

23#define GET_INSTRINFO_HEADER

24

25#include "XtensaGenInstrInfo.inc"

26

27namespace llvm {

28

29class XtensaTargetMachine;

30class XtensaSubtarget;

34

35public:

37

40

42

43

45

47 int &FrameIndex) const override;

48

50 int &FrameIndex) const override;

51

54 bool KillSrc, bool RenamableDest = false,

55 bool RenamableSrc = false) const override;

56

61

67

68

70 unsigned &StoreOpcode, int64_t offset) const;

71

72

73

76

77 bool

79

81

83 int64_t BrOffset) const override;

84

88 bool AllowModify) const override;

89

91 int *BytesRemoved = nullptr) const override;

92

96 int *BytesAdded = nullptr) const override;

97

100 int64_t BrOffset = 0,

102

107 int *BytesAdded) const;

108

110 int64_t offset,

112 int *BytesAdded) const;

113

114

115

116

117

118

122

124};

125}

126

127#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Target - Wrapper for Target specific information.

LLVM Value Representation.

const XtensaSubtarget & getSubtarget() const

Definition XtensaInstrInfo.h:123

bool isBranch(const MachineBasicBlock::iterator &MI, SmallVectorImpl< MachineOperand > &Cond, const MachineOperand *&Target) const

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const override

void adjustStackPtr(MCRegister SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const

Adjust SP by Amount bytes.

Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override

const XtensaRegisterInfo & getRegisterInfo() const

Definition XtensaInstrInfo.h:44

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I, int64_t offset, ArrayRef< MachineOperand > Cond, DebugLoc DL, int *BytesAdded) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

unsigned insertBranchAtInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded) const

MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override

XtensaInstrInfo(const XtensaSubtarget &STI)

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode, int64_t offset) const

void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MCRegister *Reg, int64_t Value) const

This is an optimization pass for GlobalISel generic memory operations.