LLVM: llvm::HexagonInstrInfo Class Reference (original) (raw)

#include "[Target/Hexagon/HexagonInstrInfo.h](HexagonInstrInfo%5F8h%5Fsource.html)"

Definition at line 40 of file HexagonInstrInfo.h.

◆ addLatencyToSchedule()

◆ analyzeBranch()

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

This function can analyze one/two way branching only and should (mostly) be called by target independent side.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
2. If this block ends with only an unconditional branch, it sets TBB to be the destination block.
3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm

Definition at line 435 of file HexagonInstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::dbgs(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isEndLoopN(), llvm::MachineOperand::isMBB(), isNewValueJump(), LLVM_DEBUG, MBB, PredOpcodeHasJMP_c(), llvm::printMBBReference(), and TBB.

Referenced by insertBranch().

◆ analyzeCompare()

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1898 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::isImm(), MI, and Opc.

◆ analyzeLoopForPipelining()

◆ areMemAccessesTriviallyDisjoint()

Definition at line 2004 of file HexagonInstrInfo.cpp.

References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), and llvm::MachineInstr::mayLoad().

◆ canExecuteInBundle()

◆ changeAddrMode_abs_io() [1/2]

◆ changeAddrMode_abs_io() [2/2]

◆ changeAddrMode_io_abs() [1/2]

◆ changeAddrMode_io_abs() [2/2]

◆ changeAddrMode_io_pi()

◆ changeAddrMode_io_rr() [1/2]

◆ changeAddrMode_io_rr() [2/2]

◆ changeAddrMode_pi_io()

◆ changeAddrMode_rr_io() [1/2]

◆ changeAddrMode_rr_io() [2/2]

◆ changeAddrMode_rr_ur() [1/2]

◆ changeAddrMode_rr_ur() [2/2]

◆ changeAddrMode_ur_rr() [1/2]

◆ changeAddrMode_ur_rr() [2/2]

◆ changeDuplexOpcode()

◆ ClobbersPredicate()

If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

Definition at line 1748 of file HexagonInstrInfo.cpp.

References MI.

◆ copyPhysReg()

Emit instructions to copy a pair of physical registers.

This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.

The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.

Definition at line 860 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::LivePhysRegs::contains(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getLiveInRegsAt(), llvm::getUndefRegState(), I, llvm_unreachable, MBB, llvm::printMBBReference(), and llvm::printReg().

Referenced by expandPostRAPseudo().

◆ CreateTargetPostRAHazardRecognizer()

◆ CreateTargetScheduleState()

◆ createVR()

◆ decomposeMachineOperandsTargetFlags()

◆ doesNotReturn()

◆ expandPostRAPseudo()

This function is called for all pseudo instructions that remain after register allocation.

expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.

Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.

Definition at line 1057 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::cast(), llvm::MachineInstrBuilder::cloneMemRefs(), copyPhysReg(), llvm::MachineFunction::createExternalSymbolName(), DL, llvm::dyn_cast(), llvm::get(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::GlobalVariable::getInitializer(), llvm::getKillRegState(), getLiveInRegsAt(), getLiveOutRegsAt(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineOperand::getReg(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::getRegState(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::getUndefRegState(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::RegState::InternalRead, isConstant(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, mayAlias(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOVolatile, MRI, llvm::Offset, Opc, T, and llvm::RegState::Undef.

◆ expandVGatherPseudo()

◆ findLoopInstr()

Find the hardware loop instruction used to set-up the specified loop.

On Hexagon, we have two instructions used to set-up the hardware loop (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions to indicate the end of a loop.

Definition at line 198 of file HexagonInstrInfo.cpp.

References findLoopInstr(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), Opc, PB(), llvm::MachineBasicBlock::predecessors(), and llvm::reverse().

Referenced by analyzeLoopForPipelining(), findLoopInstr(), and insertBranch().

◆ genAllInsnTimingClasses()

Definition at line 4696 of file HexagonInstrInfo.cpp.

References A(), B(), llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::dbgs(), DL, llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::MachineInstr::getDesc(), getName(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), I, and LLVM_DEBUG.

◆ getAddrMode()

◆ getBaseAndOffset()

Definition at line 3311 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), getBaseAndOffsetPosition(), getMemAccessSize(), llvm::MachineOperand::getSubReg(), isMemOp(), isPostIncrement(), MI, llvm::Offset, and llvm::LocationSize::precise().

Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), and getMemOperandsWithOffsetWidth().

◆ getBaseAndOffsetPosition()

◆ getBranchingInstrs()

◆ getBundleNoShuf()

◆ getCExtOpNum()

◆ getCompoundCandidateGroup()

◆ getCompoundOpcode()

Definition at line 3533 of file HexagonInstrInfo.cpp.

References assert(), getCompoundCandidateGroup(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::MachineOperand::isImm(), llvm::isUInt(), and llvm::MachineInstr::readsRegister().

◆ getCondOpcode()

◆ getDotCurOp()

◆ getDotNewOp()

◆ getDotNewPredJumpOp()

◆ getDotNewPredOp()

◆ getDotOldOp()

◆ getDuplexCandidateGroup()

Definition at line 3943 of file HexagonInstrInfo.cpp.

References contains(), llvm::HexagonRegisterInfo::getStackRegister(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDblRegForSubInst(), llvm::isInt(), isIntRegForSubInst(), llvm::isShiftedInt(), llvm::isShiftedUInt(), llvm::isUInt(), and MI.

Referenced by changeDuplexOpcode(), and isDuplexPair().

◆ getDuplexOpcode()

◆ getEquivalentHWInstr()

◆ getIncrementValue()

◆ getInlineAsmLength()

◆ getInstrLatency()

◆ getInstrTimingClassLatency()

◆ getInvertedPredicatedOpcode()

◆ getInvertedPredSense()

◆ getMaxValue()

◆ getMemAccessSize()

◆ getMemOperandsWithOffsetWidth()

◆ getMinValue()

◆ getNonDotCurOp()

◆ getNonExtOpcode()

◆ getNop()

◆ getOperandLatency()

◆ getPredReg()

◆ getPseudoInstrPair()

◆ getRegForm()

◆ getRegisterInfo()

◆ getSerializableBitmaskMachineOperandTargetFlags()

Return an array that contains the bitmask target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 2110 of file HexagonInstrInfo.cpp.

References llvm::ArrayRef().

◆ getSerializableDirectMachineOperandTargetFlags()

Return an array that contains the direct target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 2091 of file HexagonInstrInfo.cpp.

References llvm::ArrayRef().

◆ getSize()

Definition at line 4601 of file HexagonInstrInfo.cpp.

References assert(), BranchRelaxAsmLarge, getInlineAsmLength(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), HEXAGON_INSTR_SIZE, isConstExtended(), isExtended(), isReg(), MBB, MI, and Size.

◆ getType()

◆ getUnits()

◆ hasEHLabel()

◆ hasLoadFromStackSlot()

Check if the instruction or the bundle of instructions has load from stack slots.

This function checks if the instruction or bundle of instructions has load from stack slot and returns frameindex and machine memory operand of that instruction if true.

Return the frameindex and machine memory operand if true.

Definition at line 387 of file HexagonInstrInfo.cpp.

References Accesses, llvm::TargetInstrInfo::hasLoadFromStackSlot(), MBB, and MI.

◆ hasNonExtEquivalent()

◆ hasPseudoInstrPair()

◆ hasStoreToStackSlot()

Check if the instruction or the bundle of instructions has store to stack slots.

This function checks if the instruction or bundle of instructions has store to stack slot and returns frameindex and machine memory operand of that instruction if true.

Return the frameindex and machine memory operand if true.

Definition at line 405 of file HexagonInstrInfo.cpp.

References Accesses, llvm::TargetInstrInfo::hasStoreToStackSlot(), MBB, and MI.

◆ hasUncondBranch()

◆ immediateExtend()

◆ insertBranch()

Insert branch code into the end of the specified MachineBasicBlock.

The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted.

It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.

Definition at line 628 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), Cond, llvm::dbgs(), DL, findLoopInstr(), llvm::get(), llvm::getImm(), getReg(), llvm::MachineOperand::getReg(), llvm::getUndefRegState(), insertBranch(), isEndLoopN(), isNewValueJump(), isPredicated(), isReg(), isUndef(), llvm::MachineOperand::isUndef(), LLVM_DEBUG, llvm_unreachable, MBB, llvm::printMBBReference(), removeBranch(), reverseBranchCondition(), TBB, and validateBranchCond().

Referenced by insertBranch().

◆ insertNoop()

◆ invertAndChangeJumpTarget()

◆ isAbsoluteSet()

◆ isAccumulator()

◆ isAddrModeWithOffset()

◆ isAsCheapAsAMove()

◆ isBaseImmOffset()

◆ isComplex()

◆ isCompoundBranchInstr()

◆ isConstExtended()

Definition at line 2164 of file HexagonInstrInfo.cpp.

References assert(), llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, getCExtOpNum(), llvm::MachineOperand::getImm(), getMaxValue(), getMinValue(), llvm::MachineOperand::getTargetFlags(), llvm::HexagonII::HMOTF_ConstExtended, llvm::MachineOperand::isBlockAddress(), llvm::MachineOperand::isCPI(), isExtendable(), isExtended(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isJTI(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isSymbol(), and MI.

Referenced by getSize(), and immediateExtend().

◆ isDeallocRet()

◆ isDependent()

◆ isDotCurInst()

◆ isDotNewInst()

◆ isDuplexPair()

◆ isEndLoopN()

◆ isExpr()

◆ isExtendable()

◆ isExtended()

◆ isFloat()

◆ isHVXMemWithAIndirect()

◆ isHVXVec()

◆ isIndirectCall()

◆ isIndirectL4Return()

◆ isJumpR()

◆ isJumpWithinBranchRange()

◆ isLateSourceInstr()

◆ isLoadFromStackSlot()

TargetInstrInfo overrides.

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 289 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.

◆ isLoopN()

◆ isMemOp()

◆ isNewValue() [1/2]

◆ isNewValue() [2/2]

◆ isNewValueInst()

◆ isNewValueJump() [1/2]

◆ isNewValueJump() [2/2]

◆ isNewValueStore() [1/2]

◆ isNewValueStore() [2/2]

◆ isOperandExtended()

◆ isPostIncrement()

◆ isPredicable()

◆ isPredicated() [1/2]

Returns true if the instruction is already predicated.

Definition at line 1685 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.

Referenced by getBaseAndOffsetPosition(), getDotOldOp(), getPredicatedRegister(), getPredicateSense(), insertBranch(), isDotNewInst(), isNewValueJump(), isPredicatedNew(), isPredicatedNew(), and predOpcodeHasNot().

◆ isPredicated() [2/2]

◆ isPredicatedNew() [1/2]

◆ isPredicatedNew() [2/2]

◆ isPredicatedTrue() [1/2]

◆ isPredicatedTrue() [2/2]

◆ isPredicateLate()

◆ isPredictedTaken()

◆ isProfitableToDupForIfCvt()

Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.

The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 836 of file HexagonInstrInfo.cpp.

References MBB.

◆ isProfitableToIfCvt() [1/2]

Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 823 of file HexagonInstrInfo.cpp.

References MBB, and nonDbgBBSize().

◆ isProfitableToIfCvt() [2/2]

Second variant of isProfitableToIfCvt.

This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutually exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 829 of file HexagonInstrInfo.cpp.

References nonDbgBBSize().

◆ isPureSlot0()

◆ isQFPMul()

◆ isRestrictNoSlot1Store()

◆ isSaveCalleeSavedRegsCall()

◆ isSchedulingBoundary()

◆ isSignExtendingLoad()

◆ isSolo()

◆ isSpillPredRegOp()

◆ isStoreToStackSlot()

If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 337 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.

◆ isTailCall()

◆ isTC1()

◆ isTC2()

◆ isTC2Early()

◆ isTC4x()

◆ isToBeScheduledASAP()

◆ isValidAutoIncImm()

◆ isValidOffset()

Definition at line 2766 of file HexagonInstrInfo.cpp.

References assert(), llvm::dbgs(), getName(), Hexagon_ADDI_OFFSET_MAX, Hexagon_ADDI_OFFSET_MIN, Hexagon_MEMB_OFFSET_MAX, Hexagon_MEMB_OFFSET_MIN, Hexagon_MEMD_OFFSET_MAX, Hexagon_MEMD_OFFSET_MIN, Hexagon_MEMH_OFFSET_MAX, Hexagon_MEMH_OFFSET_MIN, Hexagon_MEMW_OFFSET_MAX, Hexagon_MEMW_OFFSET_MIN, llvm::isInt(), llvm::isPowerOf2_32(), llvm::isShiftedInt(), llvm::isShiftedUInt(), llvm::isUInt(), llvm_unreachable, llvm::Log2_32(), llvm::Offset, and TRI.

◆ isVecAcc()

◆ isVecALU()

◆ isVecUsableNextPacket()

◆ isZeroExtendingLoad()

◆ loadRegFromStackSlot()

Load the specified register of the given register class from the specified stack frame index.

The load instruction is to be added to the given machine basic block before the specified machine instruction.

Definition at line 1011 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOLoad.

◆ mayBeCurLoad()

◆ mayBeNewStore()

◆ nonDbgBBSize()

◆ nonDbgBundleSize()

◆ predCanBeUsedAsDotNew()

◆ PredicateInstruction()

Convert the instruction into a predicated instruction.

It returns true if the operation was successful.

Definition at line 1690 of file HexagonInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), B(), llvm::BuildMI(), Cond, llvm::dbgs(), DL, llvm::get(), getCondOpcode(), llvm::getImm(), getPredReg(), isEndLoopN(), isNewValueJump(), isPredicable(), LLVM_DEBUG, MI, MRI, Opc, predOpcodeHasNot(), and T.

◆ PredOpcodeHasJMP_c()

◆ predOpcodeHasNot()

◆ producesStall() [1/2]

◆ producesStall() [2/2]

◆ removeBranch()

◆ reverseBranchCondition()

◆ reversePrediction()

◆ reversePredSense()

◆ setBundleNoShuf()

◆ shouldSink()

◆ storeRegToStackSlot()

Store the specified register of the given register class to the specified stack frame index.

The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.

Definition at line 963 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOStore.

◆ SubsumesPredicate()

Returns true if the first specified predicate subsumes the second, e.g.

GE subsumes GT.

Definition at line 1742 of file HexagonInstrInfo.cpp.

◆ translateInstrsForDup() [1/2]

◆ translateInstrsForDup() [2/2]

◆ validateBranchCond()

The documentation for this class was generated from the following files:

• lib/Target/Hexagon/HexagonInstrInfo.h
• lib/Target/Hexagon/HexagonInstrInfo.cpp