LLVM: llvm::RISCVSubtarget Class Reference (original) (raw)

#include "[Target/RISCV/RISCVSubtarget.h](RISCVSubtarget%5F8h%5Fsource.html)"

Public Types
enum	RISCVProcFamilyEnum : uint8_t { Others, SiFive7, VentanaVeyron, MIPSP8700, Andes45 }
enum	RISCVVRGatherCostModelEnum : uint8_t { Quadratic, NLog2N }

Public Member Functions
	RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
	~RISCVSubtarget () override
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVFrameLowering *	getFrameLowering () const override
const RISCVInstrInfo *	getInstrInfo () const override
const RISCVRegisterInfo *	getRegisterInfo () const override
const RISCVTargetLowering *	getTargetLowering () const override
bool	enableMachineScheduler () const override
bool	enablePostRAScheduler () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
RISCVProcFamilyEnum	getProcFamily () const
	Returns RISC-V processor family.
RISCVVRGatherCostModelEnum	getVRGatherCostModel () const
bool	hasStdExtCOrZca () const
bool	hasStdExtCOrZcd () const
bool	hasStdExtCOrZcfOrZce () const
bool	hasStdExtZvl () const
bool	hasStdExtFOrZfinx () const
bool	hasStdExtDOrZdinx () const
bool	hasStdExtZfhOrZhinx () const
bool	hasStdExtZfhminOrZhinxmin () const
bool	hasHalfFPLoadStoreMove () const
bool	hasCLZLike () const
bool	hasCTZLike () const
bool	hasCPOPLike () const
bool	hasREV8Like () const
bool	hasBEXTILike () const
bool	hasCZEROLike () const
bool	hasConditionalMoveFusion () const
bool	hasShlAdd (int64_t ShAmt) const
bool	is64Bit () const
MVT	getXLenVT () const
unsigned	getXLen () const
bool	useMIPSLoadStorePairs () const
bool	useMIPSCCMovInsn () const
unsigned	getFLen () const
Align	getZilsdAlign () const
unsigned	getELen () const
unsigned	getRealMinVLen () const
unsigned	getRealMaxVLen () const
std::optional< unsigned >	getRealVLen () const
template
Quantity	expandVScale (Quantity X) const
	If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted to a fixed quantity.
RISCVABI::ABI	getTargetABI () const
bool	isSoftFPABI () const
bool	isRegisterReservedByUser (Register i) const override
bool	isXRaySupported () const override
bool	hasVInstructions () const
bool	hasVInstructionsI64 () const
bool	hasVInstructionsF16Minimal () const
bool	hasVInstructionsF16 () const
bool	hasVInstructionsBF16Minimal () const
bool	hasVInstructionsF32 () const
bool	hasVInstructionsF64 () const
bool	hasVInstructionsBF16 () const
bool	hasVInstructionsAnyF () const
bool	hasVInstructionsFullMultiply () const
unsigned	getMaxInterleaveFactor () const
bool	hasOptimizedSegmentLoadStore (unsigned NF) const
bool	enablePExtCodeGen () const
unsigned	getDLenFactor () const
const SelectionDAGTargetInfo *	getSelectionDAGInfo () const override
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RISCVRegisterBankInfo *	getRegBankInfo () const override
bool	isTargetAndroid () const
bool	isTargetFuchsia () const
bool	useConstantPoolForLargeInts () const
unsigned	getMaxBuildIntsCost () const
unsigned	getMaxLMULForFixedLengthVectors () const
bool	useRVVForFixedLengthVectors () const
bool	enableSubRegLiveness () const override
bool	enableMachinePipeliner () const override
bool	useDFAforSMS () const override
bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
unsigned	getCacheLineSize () const override
unsigned	getPrefetchDistance () const override
unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
unsigned	getMaxPrefetchIterationsAhead () const override
bool	enableWritePrefetching () const override
unsigned	getMinimumJumpTableEntries () const
unsigned	getTailDupAggressiveThreshold () const
unsigned	getMaxStoresPerMemset (bool OptSize) const
unsigned	getMaxGluedStoresPerMemcpy () const
unsigned	getMaxStoresPerMemcpy (bool OptSize) const
unsigned	getMaxStoresPerMemmove (bool OptSize) const
unsigned	getMaxLoadsPerMemcmp (bool OptSize) const
MISched::Direction	getPostRASchedDirection () const
void	overrideSchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override
void	overridePostRASchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Protected Attributes
std::unique_ptr< const SelectionDAGTargetInfo >	TSInfo
std::unique_ptr< CallLowering >	CallLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RISCVRegisterBankInfo >	RegBankInfo

Definition at line 79 of file RISCVSubtarget.h.

◆ RISCVProcFamilyEnum

Enumerator
Others
SiFive7
VentanaVeyron
MIPSP8700
Andes45

Definition at line 82 of file RISCVSubtarget.h.

◆ RISCVVRGatherCostModelEnum

◆ ~RISCVSubtarget()

RISCVSubtarget::~RISCVSubtarget ( )	overridedefault

◆ enableMachinePipeliner()

bool RISCVSubtarget::enableMachinePipeliner ( ) const	override

◆ enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const	inlineoverride

◆ enablePExtCodeGen()

bool RISCVSubtarget::enablePExtCodeGen	(	)	const

◆ enablePostRAScheduler()

bool llvm::RISCVSubtarget::enablePostRAScheduler ( ) const	inlineoverride

◆ enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const	override

◆ enableWritePrefetching()

bool llvm::RISCVSubtarget::enableWritePrefetching ( ) const	inlineoverride

◆ expandVScale()

template

Quantity llvm::RISCVSubtarget::expandVScale ( Quantity X) const	inline

◆ getCacheLineSize()

unsigned llvm::RISCVSubtarget::getCacheLineSize ( ) const	inlineoverride

◆ getCallLowering()

◆ getDLenFactor()

unsigned llvm::RISCVSubtarget::getDLenFactor ( ) const	inline

◆ getELen()

unsigned llvm::RISCVSubtarget::getELen ( ) const	inline

Definition at line 247 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

Referenced by combineBinOpOfExtractToReduceTree(), getContainerForFixedLengthVector(), getWideningInterleave(), isInterleaveShuffle(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), lowerGetVectorLength(), lowerVECTOR_SHUFFLE(), performVECTOR_SHUFFLECombine(), and useRVVForFixedLengthVectorVT().

◆ getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const	inline

◆ getFrameLowering()

◆ getInstrInfo()

◆ getInstructionSelector()

◆ getLegalizerInfo()

◆ getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost	(	)	const

◆ getMaxGluedStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxGluedStoresPerMemcpy ( ) const	inline

◆ getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const	inline

◆ getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors	(	)	const

◆ getMaxLoadsPerMemcmp()

unsigned llvm::RISCVSubtarget::getMaxLoadsPerMemcmp ( bool OptSize) const	inline

◆ getMaxPrefetchIterationsAhead()

unsigned llvm::RISCVSubtarget::getMaxPrefetchIterationsAhead ( ) const	inlineoverride

◆ getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const	protected

◆ getMaxStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemcpy ( bool OptSize) const	inline

◆ getMaxStoresPerMemmove()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemmove ( bool OptSize) const	inline

◆ getMaxStoresPerMemset()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemset ( bool OptSize) const	inline

◆ getMinimumJumpTableEntries()

unsigned RISCVSubtarget::getMinimumJumpTableEntries	(	)	const

◆ getMinPrefetchStride()

◆ getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const	protected

◆ getPostRASchedDirection()

◆ getPrefetchDistance()

unsigned llvm::RISCVSubtarget::getPrefetchDistance ( ) const	inlineoverride

◆ getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const	inline

◆ getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const	inline

◆ getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const	inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 163 of file RISCVSubtarget.h.

◆ getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const	inline

◆ getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const	inline

◆ getRealVLen()

std::optional< unsigned > llvm::RISCVSubtarget::getRealVLen ( ) const	inline

◆ getRegBankInfo()

◆ getRegisterInfo()

◆ getSelectionDAGInfo()

◆ getTailDupAggressiveThreshold()

unsigned llvm::RISCVSubtarget::getTailDupAggressiveThreshold ( ) const	inline

◆ getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const	inline

◆ getTargetLowering()

◆ getVRGatherCostModel()

RISCVVRGatherCostModelEnum llvm::RISCVSubtarget::getVRGatherCostModel ( ) const	inline

◆ getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const	inline

Definition at line 226 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), combineSelectAndUse(), combineVectorSizedSetCCEquality(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), lowerFABSorFNEG(), lowerFCOPYSIGN(), performBITREVERSECombine(), transformAddImmMulImm(), and transformAddShlImm().

◆ getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const	inline

Definition at line 223 of file RISCVSubtarget.h.

References is64Bit().

Referenced by buildDefaultVLOps(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), combine_CC(), combineShlAddIAdd(), combineSubShiftToOrcB(), combineToVCPOP(), combineVectorSizedSetCCEquality(), expandMul(), getDefaultScalableVLOps(), getDefaultVLOps(), getVSlidedown(), getVSlideup(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), lowerCttzElts(), lowerDisjointIndicesShuffle(), lowerFABSorFNEG(), lowerFCOPYSIGN(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerGetVectorLength(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), lowerVZIP(), matchSplatAsGather(), performCONCAT_VECTORSCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performSRACombine(), performVECTOR_SHUFFLECombine(), performVP_REVERSECombine(), performVP_STORECombine(), promoteVCIXScalar(), selectVSplatImmHelper(), and tryMemPairCombine().

◆ getZilsdAlign()

Align llvm::RISCVSubtarget::getZilsdAlign ( ) const	inline

◆ hasBEXTILike()

bool llvm::RISCVSubtarget::hasBEXTILike ( ) const	inline

◆ hasCLZLike()

bool llvm::RISCVSubtarget::hasCLZLike ( ) const	inline

◆ hasConditionalMoveFusion()

bool llvm::RISCVSubtarget::hasConditionalMoveFusion ( ) const	inline

◆ hasCPOPLike()

bool llvm::RISCVSubtarget::hasCPOPLike ( ) const	inline

◆ hasCTZLike()

bool llvm::RISCVSubtarget::hasCTZLike ( ) const	inline

◆ hasCZEROLike()

bool llvm::RISCVSubtarget::hasCZEROLike ( ) const	inline

◆ hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const	inline

◆ hasOptimizedSegmentLoadStore()

bool llvm::RISCVSubtarget::hasOptimizedSegmentLoadStore ( unsigned NF) const	inline

◆ hasREV8Like()

bool llvm::RISCVSubtarget::hasREV8Like ( ) const	inline

◆ hasShlAdd()

bool llvm::RISCVSubtarget::hasShlAdd ( int64_t ShAmt) const	inline

◆ hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const	inline

◆ hasStdExtCOrZcd()

bool llvm::RISCVSubtarget::hasStdExtCOrZcd ( ) const	inline

◆ hasStdExtCOrZcfOrZce()

bool llvm::RISCVSubtarget::hasStdExtCOrZcfOrZce ( ) const	inline

◆ hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const	inline

◆ hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const	inline

◆ hasStdExtZfhminOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhminOrZhinxmin ( ) const	inline

◆ hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const	inline

◆ hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const	inline

◆ hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const	inline

Definition at line 293 of file RISCVSubtarget.h.

Referenced by combineBinOpOfExtractToReduceTree(), combineVectorSizedSetCCEquality(), getELen(), getMaxInterleaveFactor(), getMaxLMULForFixedLengthVectors(), getMaxRVVVectorSizeInBits(), getMinRVVVectorSizeInBits(), getScavSlotsNumForRVV(), isSupportedArgumentType(), isSupportedReturnType(), lowerVectorIntrinsicScalars(), reverseZExtICmpCombine(), and useRVVForFixedLengthVectors().

◆ hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const	inline

◆ hasVInstructionsBF16()

bool llvm::RISCVSubtarget::hasVInstructionsBF16 ( ) const	inline

◆ hasVInstructionsBF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsBF16Minimal ( ) const	inline

◆ hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const	inline

◆ hasVInstructionsF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsF16Minimal ( ) const	inline

◆ hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const	inline

◆ hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const	inline

◆ hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const	inline

◆ hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const	inline

◆ is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const	inline

Definition at line 222 of file RISCVSubtarget.h.

Referenced by llvm::CC_RISCV_FastCC(), llvm::CC_RISCV_GHC(), emitFROUND(), getPACKOpcode(), getXLen(), getXLenVT(), isCompressibleLoad(), isCompressibleStore(), isLegalElementTypeForRVV(), lowerBuildVectorOfConstants(), performANDCombine(), performSETCCCombine(), performSIGN_EXTEND_INREGCombine(), performTRUNCATECombine(), performXORCombine(), and selectConstantAddr().

◆ isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register i) const	inlineoverride

◆ isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const	inline

◆ isTargetAndroid()

bool llvm::RISCVSubtarget::isTargetAndroid ( ) const	inline

◆ isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const	inline

◆ isXRaySupported()

bool llvm::RISCVSubtarget::isXRaySupported ( ) const	inlineoverride

◆ overridePostRASchedPolicy()

◆ overrideSchedPolicy()

◆ ParseSubtargetFeatures()

◆ useAA()

bool RISCVSubtarget::useAA ( ) const	override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 222 of file RISCVSubtarget.cpp.

References UseAA.

◆ useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts	(	)	const

◆ useDFAforSMS()

bool llvm::RISCVSubtarget::useDFAforSMS ( ) const	inlineoverride

◆ useMIPSCCMovInsn()

bool RISCVSubtarget::useMIPSCCMovInsn	(	)	const

◆ useMIPSLoadStorePairs()

bool RISCVSubtarget::useMIPSLoadStorePairs	(	)	const

◆ useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors	(	)	const

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo	mutableprotected