LLVM: llvm::AMDGPU::Hwreg Namespace Reference (original) (raw)

enum

Id {
ID_MODE = 1 , ID_STATUS = 2 , ID_TRAPSTS = 3 , ID_HW_ID = 4 ,
ID_GPR_ALLOC = 5 , ID_LDS_ALLOC = 6 , ID_IB_STS = 7 , ID_PERF_SNAPSHOT_DATA_gfx12 = 10 ,
ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11 , ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12 , ID_MEM_BASES = 15 , ID_TBA_LO = 16 ,
ID_TBA_HI = 17 , ID_TMA_LO = 18 , ID_TMA_HI = 19 , ID_FLAT_SCR_LO = 20 ,
ID_FLAT_SCR_HI = 21 , ID_XNACK_MASK = 22 , ID_HW_ID1 = 23 , ID_HW_ID2 = 24 ,
ID_POPS_PACKER = 25 , ID_SCHED_MODE = 26 , ID_PERF_SNAPSHOT_DATA_gfx11 = 27 , ID_IB_STS2 = 28 ,
ID_SHADER_CYCLES = 29 , ID_SHADER_CYCLES_HI = 30 , ID_DVGPR_ALLOC_LO = 31 , ID_DVGPR_ALLOC_HI = 32 ,
ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18 , ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19 , ID_STATE_PRIV = 4 , ID_PERF_SNAPSHOT_DATA1 = 15 ,
ID_PERF_SNAPSHOT_DATA2 = 16 , ID_EXCP_FLAG_PRIV = 17 , ID_EXCP_FLAG_USER = 18 , ID_TRAP_CTRL = 19 ,
ID_XCC_ID = 20 , ID_SQ_PERF_SNAPSHOT_DATA = 21 , ID_SQ_PERF_SNAPSHOT_DATA1 = 22 , ID_SQ_PERF_SNAPSHOT_PC_LO = 23 ,
ID_SQ_PERF_SNAPSHOT_PC_HI = 24 , ID_XNACK_STATE_PRIV = 33 , ID_XNACK_MASK_gfx1250 = 34
}

enum

ModeRegisterMasks : uint32_t {
FP_ROUND_MASK = 0xf << 0 , FP_DENORM_MASK = 0xf << 4 , DX10_CLAMP_MASK = 1 << 8 , IEEE_MODE_MASK = 1 << 9 ,
LOD_CLAMP_MASK = 1 << 10 , DEBUG_MASK = 1 << 11 , EXCP_EN_INVALID_MASK = 1 << 12 , EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13 ,
EXCP_EN_FLOAT_DIV0_MASK = 1 << 14 , EXCP_EN_OVERFLOW_MASK = 1 << 15 , EXCP_EN_UNDERFLOW_MASK = 1 << 16 , EXCP_EN_INEXACT_MASK = 1 << 17 ,
EXCP_EN_INT_DIV0_MASK = 1 << 18 , GPR_IDX_EN_MASK = 1 << 27 , VSKIP_MASK = 1 << 28 , CSP_MASK = 0x7u << 29 ,
DST_VGPR_MSB = 1 << 12 , SRC0_VGPR_MSB = 1 << 13 , SRC1_VGPR_MSB = 1 << 14 , SRC2_VGPR_MSB = 1 << 15 ,
VGPR_MSB_MASK = 0xf << 12 , REPLAY_MODE = 1 << 25 , FLAT_SCRATCH_IS_NV = 1 << 26
}