LLVM: llvm::PPC Namespace Reference (original) (raw)
Define some predicates that are used for node matching. More...
| Functions | |
|---|---|
| LLVM_ABI bool | isValidCPU (StringRef CPU) |
| LLVM_ABI void | fillValidCPUList (SmallVectorImpl< StringRef > &Values) |
| LLVM_ABI void | fillValidTuneCPUList (SmallVectorImpl< StringRef > &Values) |
| LLVM_ABI StringRef | getNormalizedPPCTargetCPU (const Triple &T, StringRef CPUName="") |
| LLVM_ABI StringRef | getNormalizedPPCTuneCPU (const Triple &T, StringRef CPUName="") |
| LLVM_ABI StringRef | normalizeCPUName (StringRef CPUName) |
| LLVM_ABI std::optional< llvm::StringMap< bool > > | getPPCDefaultTargetFeatures (const Triple &T, StringRef CPUName) |
| bool | evaluateAsConstant (const MCSpecifierExpr &Expr, int64_t &Res) |
| const char * | stripRegisterPrefix (const char *RegName) |
| stripRegisterPrefix - This method strips the character prefix from a register name so that only the number is left. | |
| MCRegister | getRegNumForOperand (const MCInstrDesc &Desc, MCRegister Reg, unsigned OpNo) |
| getRegNumForOperand - some operands use different numbering schemes for the same registers. | |
| static bool | isVFRegister (MCRegister Reg) |
| static bool | isVRRegister (MCRegister Reg) |
| static bool | isDMRROWpRegister (unsigned Reg) |
| Predicate | InvertPredicate (Predicate Opcode) |
| Invert the specified predicate. != -> ==, < -> >=. | |
| Predicate | getSwappedPredicate (Predicate Opcode) |
| Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a). | |
| unsigned | getPredicateCondition (Predicate Opcode) |
| Return the condition without hint bits. | |
| unsigned | getPredicateHint (Predicate Opcode) |
| Return the hint bits of the predicate. | |
| Predicate | getPredicate (unsigned Condition, unsigned Hint) |
| Return predicate consisting of specified condition and hint bits. | |
| int | getNonRecordFormOpcode (uint16_t) |
| bool | isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction. | |
| bool | isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction. | |
| bool | isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction. | |
| bool | isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes). | |
| bool | isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes). | |
| bool | isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction | |
| bool | isXXSLDWIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE) |
| isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction. | |
| bool | isXXBRHShuffleMask (ShuffleVectorSDNode *N) |
| isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction. | |
| bool | isXXBRWShuffleMask (ShuffleVectorSDNode *N) |
| isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction. | |
| bool | isXXBRDShuffleMask (ShuffleVectorSDNode *N) |
| isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction. | |
| bool | isXXBRQShuffleMask (ShuffleVectorSDNode *N) |
| isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction. | |
| bool | isXXPERMDIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE) |
| isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction. | |
| int | isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1. | |
| bool | isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize) |
| isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW. | |
| bool | isXXINSERTWMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE) |
| isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0. | |
| unsigned | getSplatIdxForPPCMnemonics (SDNode *N, unsigned EltSize, SelectionDAG &DAG) |
| getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics (which have a big endian bias - namely elements are counted from the left of the vector register). | |
| SDValue | get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG) |
| get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. | |
| FastISel * | createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) |
| int | getAltVSXFMAOpcode (uint16_t Opcode) |
| static const CPUInfo * | getCPUInfoByName (StringRef CPU) |
Define some predicates that are used for node matching.
◆ anonymous enum
| Enumerator |
|---|
| DIR_NONE |
| DIR_32 |
| DIR_440 |
| DIR_601 |
| DIR_602 |
| DIR_603 |
| DIR_7400 |
| DIR_750 |
| DIR_970 |
| DIR_A2 |
| DIR_E500 |
| DIR_E500mc |
| DIR_E5500 |
| DIR_PWR3 |
| DIR_PWR4 |
| DIR_PWR5 |
| DIR_PWR5X |
| DIR_PWR6 |
| DIR_PWR6X |
| DIR_PWR7 |
| DIR_PWR8 |
| DIR_PWR9 |
| DIR_PWR10 |
| DIR_PWR11 |
| DIR_PWR_FUTURE |
| DIR_64 |
Definition at line 39 of file PPCSubtarget.h.
◆ AddrMode
| Enumerator |
|---|
| AM_None |
| AM_DForm |
| AM_DSForm |
| AM_DQForm |
| AM_PrefixDForm |
| AM_XForm |
| AM_PCRel |
Definition at line 163 of file PPCISelLowering.h.
◆ BranchHintBit
| Enumerator |
|---|
| BR_NO_HINT |
| BR_NONTAKEN_HINT |
| BR_TAKEN_HINT |
| BR_HINT_MASK |
Definition at line 62 of file PPCPredicates.h.
◆ Fixups
| Enumerator | |
|---|---|
| fixup_ppc_br24 | |
| fixup_ppc_br24_notoc | |
| fixup_ppc_brcond14 | 14-bit PC relative relocation for conditional branches. |
| fixup_ppc_br24abs | 24-bit absolute relocation for direct branches like 'ba' and 'bla'. |
| fixup_ppc_brcond14abs | 14-bit absolute relocation for conditional branches. |
| fixup_ppc_half16 | A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'. |
| fixup_ppc_half16ds | A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'. |
| fixup_ppc_pcrel32 | |
| fixup_ppc_imm32 | |
| fixup_ppc_pcrel34 | |
| fixup_ppc_imm34 | |
| fixup_ppc_nofixup | Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic models, or inserts the thread-pointer register number. |
| fixup_ppc_half16dq | A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'. Produces the same relocation as fixup_ppc_half16ds. |
| LastTargetFixupKind | |
| NumTargetFixupKinds |
Definition at line 18 of file PPCFixupKinds.h.
◆ MemOpFlags
| Enumerator |
|---|
| MOF_None |
| MOF_SExt |
| MOF_ZExt |
| MOF_NoExt |
| MOF_NotAddNorCst |
| MOF_RPlusSImm16 |
| MOF_RPlusLo |
| MOF_RPlusSImm16Mult4 |
| MOF_RPlusSImm16Mult16 |
| MOF_RPlusSImm34 |
| MOF_RPlusR |
| MOF_PCRel |
| MOF_AddrIsSImm32 |
| MOF_SubWordInt |
| MOF_WordInt |
| MOF_DoubleWordInt |
| MOF_ScalarFloat |
| MOF_Vector |
| MOF_Vector256 |
| MOF_SubtargetBeforeP9 |
| MOF_SubtargetP9 |
| MOF_SubtargetP10 |
| MOF_SubtargetSPE |
Definition at line 128 of file PPCISelLowering.h.
◆ Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
| Enumerator |
|---|
| PRED_LT |
| PRED_LE |
| PRED_EQ |
| PRED_GE |
| PRED_GT |
| PRED_NE |
| PRED_UN |
| PRED_NU |
| PRED_LT_MINUS |
| PRED_LE_MINUS |
| PRED_EQ_MINUS |
| PRED_GE_MINUS |
| PRED_GT_MINUS |
| PRED_NE_MINUS |
| PRED_UN_MINUS |
| PRED_NU_MINUS |
| PRED_LT_PLUS |
| PRED_LE_PLUS |
| PRED_EQ_PLUS |
| PRED_GE_PLUS |
| PRED_GT_PLUS |
| PRED_NE_PLUS |
| PRED_UN_PLUS |
| PRED_NU_PLUS |
| PRED_SPE |
| PRED_BIT_SET |
| PRED_BIT_UNSET |
Definition at line 26 of file PPCPredicates.h.
◆ Specifier
| Enumerator |
|---|
| S_None |
| S_LO |
| S_HI |
| S_HA |
| S_HIGH |
| S_HIGHA |
| S_HIGHER |
| S_HIGHERA |
| S_HIGHEST |
| S_HIGHESTA |
| S_AIX_TLSGD |
| S_AIX_TLSGDM |
| S_AIX_TLSIE |
| S_AIX_TLSLD |
| S_AIX_TLSLE |
| S_AIX_TLSML |
| S_DTPMOD |
| S_DTPREL |
| S_DTPREL_HA |
| S_DTPREL_HI |
| S_DTPREL_HIGH |
| S_DTPREL_HIGHA |
| S_DTPREL_HIGHER |
| S_DTPREL_HIGHERA |
| S_DTPREL_HIGHEST |
| S_DTPREL_HIGHESTA |
| S_DTPREL_LO |
| S_GOT |
| S_GOT_DTPREL |
| S_GOT_DTPREL_HA |
| S_GOT_DTPREL_HI |
| S_GOT_DTPREL_LO |
| S_GOT_HA |
| S_GOT_HI |
| S_GOT_LO |
| S_GOT_PCREL |
| S_GOT_TLSGD |
| S_GOT_TLSGD_HA |
| S_GOT_TLSGD_HI |
| S_GOT_TLSGD_LO |
| S_GOT_TLSGD_PCREL |
| S_GOT_TLSLD |
| S_GOT_TLSLD_HA |
| S_GOT_TLSLD_HI |
| S_GOT_TLSLD_LO |
| S_GOT_TLSLD_PCREL |
| S_GOT_TPREL |
| S_GOT_TPREL_HA |
| S_GOT_TPREL_HI |
| S_GOT_TPREL_LO |
| S_GOT_TPREL_PCREL |
| S_L |
| S_LOCAL |
| S_NOTOC |
| S_PCREL |
| S_PCREL_OPT |
| S_PLT |
| S_TLS |
| S_TLSGD |
| S_TLSLD |
| S_TLS_PCREL |
| S_TOC |
| S_TOCBASE |
| S_TOC_HA |
| S_TOC_HI |
| S_TOC_LO |
| S_TPREL |
| S_TPREL_HA |
| S_TPREL_HI |
| S_TPREL_HIGH |
| S_TPREL_HIGHA |
| S_TPREL_HIGHER |
| S_TPREL_HIGHERA |
| S_TPREL_HIGHEST |
| S_TPREL_HIGHESTA |
| S_TPREL_LO |
| S_U |
Definition at line 45 of file PPCMCAsmInfo.h.
◆ createFastISel()
◆ evaluateAsConstant()
◆ fillValidCPUList()
◆ fillValidTuneCPUList()
◆ get_VSPLTI_elt()
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.
The ByteSize field indicates the number of bytes of each element [124] -> [bhw].
Definition at line 2385 of file PPCISelLowering.cpp.
References assert(), llvm::bit_cast(), llvm::cast(), llvm::dyn_cast(), llvm::SDNode::getAsZExtVal(), getNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::isa(), llvm::isAllOnesConstant(), llvm::isNullConstant(), isSplat(), N, SDValue(), and llvm::SignExtend32().
◆ getAltVSXFMAOpcode()
| int llvm::PPC::getAltVSXFMAOpcode | ( | uint16_t | Opcode | ) |
|---|
◆ getCPUInfoByName()
◆ getNonRecordFormOpcode()
| int llvm::PPC::getNonRecordFormOpcode ( uint16_t ) | extern |
|---|
◆ getNormalizedPPCTargetCPU()
◆ getNormalizedPPCTuneCPU()
◆ getPPCDefaultTargetFeatures()
◆ getPredicate()
◆ getPredicateCondition()
| unsigned llvm::PPC::getPredicateCondition ( Predicate Opcode) | inline |
|---|
◆ getPredicateHint()
| unsigned llvm::PPC::getPredicateHint ( Predicate Opcode) | inline |
|---|
◆ getRegNumForOperand()
getRegNumForOperand - some operands use different numbering schemes for the same registers.
For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).
Definition at line 122 of file PPCMCTargetDesc.cpp.
References isVFRegister(), and isVRRegister().
Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().
◆ getSplatIdxForPPCMnemonics()
◆ getSwappedPredicate()
| Predicate llvm::PPC::getSwappedPredicate | ( | Predicate | Opcode | ) |
|---|
◆ InvertPredicate()
| Predicate llvm::PPC::InvertPredicate | ( | Predicate | Opcode | ) |
|---|
◆ isDMRROWpRegister()
| bool llvm::PPC::isDMRROWpRegister ( unsigned Reg) | inlinestatic |
|---|
◆ isSplatShuffleMask()
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
Definition at line 2058 of file PPCISelLowering.cpp.
References assert(), llvm::isPowerOf2_32(), and N.
Referenced by getSplatIdxForPPCMnemonics().
◆ isValidCPU()
◆ isVFRegister()
◆ isVMRGEOShuffleMask()
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction
Determine if the specified shuffle mask is suitable for the vmrgew or vmrgow instructions.
Parameters
| [in] | N | The shuffle vector SD Node to analyze |
|---|---|---|
| [in] | CheckEven | Check for an even merge (true) or an odd merge (false) |
| [in] | ShuffleKind | Identify the type of merge: 0 = big-endian merge with two different inputs; 1 = either-endian merge with two identical inputs; 2 = little-endian merge with two different inputs (inputs are swapped for little-endian merges). |
| [in] | DAG | The current SelectionDAG |
Returns
true iff this shuffle mask
Definition at line 1985 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), isVMerge(), and N.
◆ isVMRGHShuffleMask()
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1895 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), isVMerge(), and N.
◆ isVMRGLShuffleMask()
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1870 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), isVMerge(), and N.
◆ isVPKUDUMShuffleMask()
◆ isVPKUHUMShuffleMask()
◆ isVPKUWUMShuffleMask()
◆ isVRRegister()
◆ isVSLDOIShuffleMask()
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 2014 of file PPCISelLowering.cpp.
References llvm::cast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), and N.
◆ isXXBRDShuffleMask()
◆ isXXBRHShuffleMask()
◆ isXXBRQShuffleMask()
◆ isXXBRWShuffleMask()
◆ isXXINSERTWMask()
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0.
This is essentially any shuffle of v4f32/v4i32 vectors that just inserts one element from one vector into the other. This function will also set a couple of output parameters for how much the source vector needs to be shifted and what byte number needs to be specified for the instruction to put the element in the desired location of the target vector.
Definition at line 2135 of file PPCISelLowering.cpp.
References isNByteElemShuffleMask(), llvm::M0(), llvm::M1(), and N.
◆ isXXPERMDIShuffleMask()
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
Can node N be lowered to an XXPERMDI instruction?
If so, set Swap if the inputs to the instruction should be swapped and set DM to the value for the immediate. Specifically, set Swap to true only if N can be lowered to XXPERMDI AND element 0 of the result comes from the first input (LE) or second input (BE). Set DM to the calculated result (0-3) only if N can be lowered.
Returns
true iff the given mask of shuffle node N is a XXPERMDI shuffle mask.
Definition at line 2309 of file PPCISelLowering.cpp.
References assert(), DM, isNByteElemShuffleMask(), llvm::M0(), llvm::M1(), and N.