LLVM: llvm::amdhsa Namespace Reference (original) (raw)

Enumerations

enum

: uint8_t { FLOAT_ROUND_MODE_NEAR_EVEN = 0 , FLOAT_ROUND_MODE_PLUS_INFINITY = 1 , FLOAT_ROUND_MODE_MINUS_INFINITY = 2 , FLOAT_ROUND_MODE_ZERO = 3 }

enum

: uint8_t { FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0 , FLOAT_DENORM_MODE_FLUSH_DST = 1 , FLOAT_DENORM_MODE_FLUSH_SRC = 2 , FLOAT_DENORM_MODE_FLUSH_NONE = 3 }

enum

: uint8_t { SYSTEM_VGPR_WORKITEM_ID_X = 0 , SYSTEM_VGPR_WORKITEM_ID_X_Y = 1 , SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2 , SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 }

enum

: int32_t {
COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) ,
COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) ,
COMPUTE_PGM_RSRC1_GFX6_GFX11 =(ENABLE_DX10_CLAMP, 21, 1) , COMPUTE_PGM_RSRC1_GFX12_PLUS =(ENABLE_WG_RR_EN, 21, 1) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1_GFX6_GFX11 =(ENABLE_DX10_CLAMP, 21, 1) ,
COMPUTE_PGM_RSRC1_GFX12_PLUS =(ENABLE_WG_RR_EN, 21, 1) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , COMPUTE_PGM_RSRC1_GFX6_GFX8 =(RESERVED0, 26, 1) ,
COMPUTE_PGM_RSRC1_GFX9_PLUS =(FP16_OVFL, 26, 1) , COMPUTE_PGM_RSRC1_GFX6_GFX120 =(RESERVED1, 27, 1) , COMPUTE_PGM_RSRC1_GFX125 =(FLAT_SCRATCH_IS_NV, 27, 1) , COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) ,
COMPUTE_PGM_RSRC1_GFX6_GFX9 =(RESERVED3, 29, 3) , COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1) , COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1) , COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1)
}

enum

: int32_t {
COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2_GFX6_GFX120 =(USER_SGPR_COUNT, 1, 5) , COMPUTE_PGM_RSRC2_GFX6_GFX11 =(ENABLE_TRAP_HANDLER, 6, 1) , COMPUTE_PGM_RSRC2_GFX120 =(ENABLE_DYNAMIC_VGPR, 6, 1) ,
COMPUTE_PGM_RSRC2_GFX125 =(USER_SGPR_COUNT, 1, 6) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) ,
COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) ,
COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) ,
COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) ,
COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
}

enum

: int32_t { COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) , COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) , COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) , COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) }

enum

: int32_t {
COMPUTE_PGM_RSRC3_GFX10_GFX11 =(SHARED_VGPR_COUNT, 0, 4) , COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4) , COMPUTE_PGM_RSRC3_GFX10 =(RESERVED1, 4, 8) , COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6) ,
COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6) , COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6) , COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4) , COMPUTE_PGM_RSRC3_GFX10_PLUS =(RESERVED2, 12, 1) ,
COMPUTE_PGM_RSRC3_GFX10_GFX11 =(SHARED_VGPR_COUNT, 0, 4) , COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4) , COMPUTE_PGM_RSRC3_GFX10_GFX120 =(RESERVED4, 14, 8) , COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) ,
COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , COMPUTE_PGM_RSRC3_GFX10_PLUS =(RESERVED2, 12, 1) ,
COMPUTE_PGM_RSRC3_GFX10 =(RESERVED1, 4, 8) , COMPUTE_PGM_RSRC3_GFX11_PLUS =(IMAGE_OP, 31, 1)
}

enum

: int32_t {
KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) ,
KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) ,
KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
}

enum

: int32_t { KERNARG_PRELOAD_SPEC =(LENGTH, 0, 7) , KERNARG_PRELOAD_SPEC =(LENGTH, 0, 7) }

enum

: uint32_t {
GROUP_SEGMENT_FIXED_SIZE_OFFSET = 0 , PRIVATE_SEGMENT_FIXED_SIZE_OFFSET = 4 , KERNARG_SIZE_OFFSET = 8 , RESERVED0_OFFSET = 12 ,
KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET = 16 , RESERVED1_OFFSET = 24 , COMPUTE_PGM_RSRC3_OFFSET = 44 , COMPUTE_PGM_RSRC1_OFFSET = 48 ,
COMPUTE_PGM_RSRC2_OFFSET = 52 , KERNEL_CODE_PROPERTIES_OFFSET = 56 , KERNARG_PRELOAD_OFFSET = 58 , RESERVED3_OFFSET = 60
}