AArch64RegisterBankInfo.cpp Source File (original) (raw)

33#include "llvm/IR/IntrinsicsAArch64.h"

36#include

38#define GET_TARGET_REGBANK_IMPL

39#include "AArch64GenRegisterBank.inc"

42#include "AArch64GenRegisterBankInfo.def"

44using namespace llvm;

51 static auto InitializeRegisterBankOnce = [&]() {

59 (void)RBGPR;

60 assert(&AArch64::GPRRegBank == &RBGPR &&

61 "The order in RegBanks is messed up");

64 (void)RBFPR;

65 assert(&AArch64::FPRRegBank == &RBFPR &&

66 "The order in RegBanks is messed up");

69 (void)RBCCR;

70 assert(&AArch64::CCRegBank == &RBCCR &&

71 "The order in RegBanks is messed up");

75 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&

76 "Subclass not added?");

78 "GPRs should hold up to 128-bit");

82 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&

83 "Subclass not added?");

84 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&

85 "Subclass not added?");

87 "FPRs should hold up to 512-bit via QQQQ sequence");

89 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&

90 "Class not added?");

92 "CCR should hold up to 32-bit");

98 "PartialMappingIdx's are incorrectly ordered");

102 "PartialMappingIdx's are incorrectly ordered");

103

104

105#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \

106 do { \

107 assert( \

108 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \

109 #Idx " is incorrectly initialized"); \

110 } while (false)

111

121

122

123#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \

124 do { \

125 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \

126 PartialMappingIdx::PMI_First##RBName, Size, \

127 Offset) && \

128 #RBName #Size " " #Offset " is incorrectly initialized"); \

129 } while (false)

130

131#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)

132

142

143

144

145#define CHECK_VALUEMAP_3OPS(RBName, Size) \

146 do { \

147 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \

148 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \

149 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \

150 } while (false)

151

160

161#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \

162 do { \

163 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \

164 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \

165 (void)PartialMapDstIdx; \

166 (void)PartialMapSrcIdx; \

167 const ValueMapping *Map = getCopyMapping(AArch64::RBNameDst##RegBankID, \

168 AArch64::RBNameSrc##RegBankID, \

169 TypeSize::getFixed(Size)); \

170 (void)Map; \

171 assert(Map[0].BreakDown == \

172 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \

173 Map[0].NumBreakDowns == 1 && \

174 #RBNameDst #Size " Dst is incorrectly initialized"); \

175 assert(Map[1].BreakDown == \

176 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \

177 Map[1].NumBreakDowns == 1 && \

178 #RBNameSrc #Size " Src is incorrectly initialized"); \

179 \

180 } while (false)

181

190

191#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \

192 do { \

193 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \

194 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \

195 (void)PartialMapDstIdx; \

196 (void)PartialMapSrcIdx; \

197 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \

198 (void)Map; \

199 assert(Map[0].BreakDown == \

200 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \

201 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \

202 " Dst is incorrectly initialized"); \

203 assert(Map[1].BreakDown == \

204 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \

205 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \

206 " Src is incorrectly initialized"); \

207 \

208 } while (false)

209

214

215 assert(verify(TRI) && "Invalid register bank information");

216 };

217

218 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);

219}

220

224

225

226

227

228

229

230

231

232 if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)

233

234 return 5;

235 if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)

236

237 return 4;

238

240}

241

244 LLT Ty) const {

245 switch (RC.getID()) {

246 case AArch64::GPR64sponlyRegClassID:

247 return getRegBank(AArch64::GPRRegBankID);

248 default:

250 }

251}

252

260

261 switch (MI.getOpcode()) {

262 case TargetOpcode::G_OR: {

263

264

266 if (Size != 32 && Size != 64)

267 break;

268

269

270

271 if (MI.getNumOperands() != 3)

272 break;

276 3);

279 3);

280

281 AltMappings.push_back(&GPRMapping);

282 AltMappings.push_back(&FPRMapping);

283 return AltMappings;

284 }

285 case TargetOpcode::G_BITCAST: {

287 if (Size != 32 && Size != 64)

288 break;

289

290

291

292 if (MI.getNumOperands() != 2)

293 break;

294

297 1, 1,

299 2);

301 2, 1,

303 2);

305 3,

306

307 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,

310 2);

312 3,

313

314 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,

317 2);

318

319 AltMappings.push_back(&GPRMapping);

320 AltMappings.push_back(&FPRMapping);

321 AltMappings.push_back(&GPRToFPRMapping);

322 AltMappings.push_back(&FPRToGPRMapping);

323 return AltMappings;

324 }

325 case TargetOpcode::G_LOAD: {

327 if (Size != 64)

328 break;

329

330

331

332 if (MI.getNumOperands() != 2)

333 break;

334

337 1, 1,

340

342 2);

344 2, 1,

347

349 2);

350

351 AltMappings.push_back(&GPRMapping);

352 AltMappings.push_back(&FPRMapping);

353 return AltMappings;

354 }

355 default:

356 break;

357 }

359}

360

361void AArch64RegisterBankInfo::applyMappingImpl(

362 MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const {

365

366 switch (MI.getOpcode()) {

367 case TargetOpcode::G_OR:

368 case TargetOpcode::G_BITCAST:

369 case TargetOpcode::G_LOAD:

370

371 assert((OpdMapper.getInstrMapping().getID() >= 1 &&

372 OpdMapper.getInstrMapping().getID() <= 4) &&

373 "Don't know how to handle that ID");

375 case TargetOpcode::G_INSERT_VECTOR_ELT: {

376

377 Builder.setInsertPt(*MI.getParent(), MI.getIterator());

378 auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg());

379 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID));

380 MI.getOperand(2).setReg(Ext.getReg(0));

382 }

383 case AArch64::G_DUP: {

384

385 assert(MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() < 32 &&

386 "Expected sources smaller than 32-bits");

387 Builder.setInsertPt(*MI.getParent(), MI.getIterator());

388

390 auto ConstMI = MRI.getVRegDef(MI.getOperand(1).getReg());

391 if (ConstMI->getOpcode() == TargetOpcode::G_CONSTANT) {

392 auto CstVal = ConstMI->getOperand(1).getCImm()->getValue();

393 ConstReg =

394 Builder.buildConstant(LLT::scalar(32), CstVal.sext(32)).getReg(0);

395 } else {

398 }

399 MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID));

400 MI.getOperand(1).setReg(ConstReg);

402 }

403 default:

405 }

406}

407

409AArch64RegisterBankInfo::getSameKindOfOperandsMapping(

411 const unsigned Opc = MI.getOpcode();

412 const MachineFunction &MF = *MI.getParent()->getParent();

413 const MachineRegisterInfo &MRI = MF.getRegInfo();

414

415 unsigned NumOperands = MI.getNumOperands();

416 assert(NumOperands <= 3 &&

417 "This code is for instructions with 3 or less operands");

418

419 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

422

424

425#ifndef NDEBUG

426

427

428

429

430

431

432

433

434 for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {

435 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());

440 "Operand has incompatible size");

442 (void)OpIsFPR;

443 assert(IsFPR == OpIsFPR && "Operand has incompatible type");

444 }

445#endif

446

449}

450

451

454

456 default:

457 return false;

458 case Intrinsic::aarch64_neon_uaddlv:

459 case Intrinsic::aarch64_neon_uaddv:

460 case Intrinsic::aarch64_neon_saddv:

461 case Intrinsic::aarch64_neon_umaxv:

462 case Intrinsic::aarch64_neon_smaxv:

463 case Intrinsic::aarch64_neon_uminv:

464 case Intrinsic::aarch64_neon_sminv:

465 case Intrinsic::aarch64_neon_faddv:

466 case Intrinsic::aarch64_neon_fmaxv:

467 case Intrinsic::aarch64_neon_fminv:

468 case Intrinsic::aarch64_neon_fmaxnmv:

469 case Intrinsic::aarch64_neon_fminnmv:

470 case Intrinsic::aarch64_neon_fmulx:

471 case Intrinsic::aarch64_neon_frecpe:

472 case Intrinsic::aarch64_neon_frecps:

473 case Intrinsic::aarch64_neon_frecpx:

474 case Intrinsic::aarch64_neon_frsqrte:

475 case Intrinsic::aarch64_neon_frsqrts:

476 case Intrinsic::aarch64_neon_facge:

477 case Intrinsic::aarch64_neon_facgt:

478 case Intrinsic::aarch64_neon_fabd:

479 case Intrinsic::aarch64_sisd_fabd:

480 case Intrinsic::aarch64_neon_sqrdmlah:

481 case Intrinsic::aarch64_neon_sqrdmlsh:

482 case Intrinsic::aarch64_neon_sqrdmulh:

483 case Intrinsic::aarch64_neon_sqadd:

484 case Intrinsic::aarch64_neon_sqsub:

485 case Intrinsic::aarch64_crypto_sha1h:

486 case Intrinsic::aarch64_neon_srshl:

487 case Intrinsic::aarch64_neon_urshl:

488 case Intrinsic::aarch64_neon_sqshl:

489 case Intrinsic::aarch64_neon_uqshl:

490 case Intrinsic::aarch64_neon_sqrshl:

491 case Intrinsic::aarch64_neon_uqrshl:

492 case Intrinsic::aarch64_neon_ushl:

493 case Intrinsic::aarch64_neon_sshl:

494 case Intrinsic::aarch64_crypto_sha1c:

495 case Intrinsic::aarch64_crypto_sha1p:

496 case Intrinsic::aarch64_crypto_sha1m:

497 case Intrinsic::aarch64_sisd_fcvtxn:

498 return true;

499 case Intrinsic::aarch64_neon_saddlv: {

500 const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());

501 return SrcTy.getElementType().getSizeInBits() >= 16 &&

502 SrcTy.getElementCount().getFixedValue() >= 4;

503 }

504 }

505}

506

507bool AArch64RegisterBankInfo::isPHIWithFPConstraints(

510 if (.isPHI() || Depth > MaxFPRSearchDepth)

511 return false;

512

513 return any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

514 [&](const MachineInstr &UseMI) {

515 if (onlyUsesFP(UseMI, MRI, TRI, Depth + 1))

516 return true;

517 return isPHIWithFPConstraints(UseMI, MRI, TRI, Depth + 1);

518 });

519}

520

521bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,

524 unsigned Depth) const {

525 unsigned Op = MI.getOpcode();

527 return true;

528

529

531 return true;

532

533

534

535 if (Op != TargetOpcode::COPY && .isPHI() &&

537 return false;

538

539

541 if (RB == &AArch64::FPRRegBank)

542 return true;

543 if (RB == &AArch64::GPRRegBank)

544 return false;

545

546

547

548

549

550 if (.isPHI() || Depth > MaxFPRSearchDepth)

551 return false;

552

553 return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {

554 return Op.isReg() &&

555 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);

556 });

557}

558

559bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,

562 unsigned Depth) const {

563 switch (MI.getOpcode()) {

564 case TargetOpcode::G_FPTOSI:

565 case TargetOpcode::G_FPTOUI:

566 case TargetOpcode::G_FPTOSI_SAT:

567 case TargetOpcode::G_FPTOUI_SAT:

568 case TargetOpcode::G_FCMP:

569 case TargetOpcode::G_LROUND:

570 case TargetOpcode::G_LLROUND:

571 case AArch64::G_PMULL:

572 return true;

573 case TargetOpcode::G_INTRINSIC:

575 case Intrinsic::aarch64_neon_fcvtas:

576 case Intrinsic::aarch64_neon_fcvtau:

577 case Intrinsic::aarch64_neon_fcvtzs:

578 case Intrinsic::aarch64_neon_fcvtzu:

579 case Intrinsic::aarch64_neon_fcvtms:

580 case Intrinsic::aarch64_neon_fcvtmu:

581 case Intrinsic::aarch64_neon_fcvtns:

582 case Intrinsic::aarch64_neon_fcvtnu:

583 case Intrinsic::aarch64_neon_fcvtps:

584 case Intrinsic::aarch64_neon_fcvtpu:

585 return true;

586 default:

587 break;

588 }

589 break;

590 default:

591 break;

592 }

594}

595

596bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,

599 unsigned Depth) const {

600 switch (MI.getOpcode()) {

601 case AArch64::G_DUP:

602 case AArch64::G_SADDLP:

603 case AArch64::G_UADDLP:

604 case TargetOpcode::G_SITOFP:

605 case TargetOpcode::G_UITOFP:

606 case TargetOpcode::G_EXTRACT_VECTOR_ELT:

607 case TargetOpcode::G_INSERT_VECTOR_ELT:

608 case TargetOpcode::G_BUILD_VECTOR:

609 case TargetOpcode::G_BUILD_VECTOR_TRUNC:

610 return true;

611 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:

613 case Intrinsic::aarch64_neon_ld1x2:

614 case Intrinsic::aarch64_neon_ld1x3:

615 case Intrinsic::aarch64_neon_ld1x4:

616 case Intrinsic::aarch64_neon_ld2:

617 case Intrinsic::aarch64_neon_ld2lane:

618 case Intrinsic::aarch64_neon_ld2r:

619 case Intrinsic::aarch64_neon_ld3:

620 case Intrinsic::aarch64_neon_ld3lane:

621 case Intrinsic::aarch64_neon_ld3r:

622 case Intrinsic::aarch64_neon_ld4:

623 case Intrinsic::aarch64_neon_ld4lane:

624 case Intrinsic::aarch64_neon_ld4r:

625 return true;

626 default:

627 break;

628 }

629 break;

630 default:

631 break;

632 }

634}

635

636bool AArch64RegisterBankInfo::prefersFPUse(const MachineInstr &MI,

639 unsigned Depth) const {

640 switch (MI.getOpcode()) {

641 case TargetOpcode::G_SITOFP:

642 case TargetOpcode::G_UITOFP:

643 return MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() ==

644 MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();

645 }

647}

648

649bool AArch64RegisterBankInfo::isLoadFromFPType(const MachineInstr &MI) const {

650

652 const Value *LdVal = MemOp->getMMO().getValue();

653 if (!LdVal)

654 return false;

655

656 Type *EltTy = nullptr;

658 EltTy = GV->getValueType();

659

660

662 if (StructEltTy->getNumElements() == 0)

663 break;

664 EltTy = StructEltTy->getTypeAtIndex(0U);

665 }

666

670

671

672 for (const auto *LdUser : LdVal->users()) {

674 EltTy = LdUser->getType();

675 break;

676 }

677 if (isa(LdUser) && LdUser->getOperand(1) == LdVal) {

678 EltTy = LdUser->getOperand(0)->getType();

679 break;

680 }

681 }

682 }

684}

685

688 const unsigned Opc = MI.getOpcode();

689

690

691

693 Opc == TargetOpcode::G_PHI) {

697 return Mapping;

698 }

699

704

705 switch (Opc) {

706

707

708 case TargetOpcode::G_ADD:

709 case TargetOpcode::G_SUB:

710 case TargetOpcode::G_PTR_ADD:

711 case TargetOpcode::G_MUL:

712 case TargetOpcode::G_SDIV:

713 case TargetOpcode::G_UDIV:

714

715 case TargetOpcode::G_AND:

716 case TargetOpcode::G_OR:

717 case TargetOpcode::G_XOR:

718

719 case TargetOpcode::G_FADD:

720 case TargetOpcode::G_FSUB:

721 case TargetOpcode::G_FMUL:

722 case TargetOpcode::G_FDIV:

723 case TargetOpcode::G_FMAXIMUM:

724 case TargetOpcode::G_FMINIMUM:

725 return getSameKindOfOperandsMapping(MI);

726 case TargetOpcode::G_FPEXT: {

727 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());

728 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

732 2);

733 }

734

735 case TargetOpcode::G_SHL:

736 case TargetOpcode::G_LSHR:

737 case TargetOpcode::G_ASHR: {

738 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());

739 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

740 if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32)

743 return getSameKindOfOperandsMapping(MI);

744 }

745 case TargetOpcode::COPY: {

746 Register DstReg = MI.getOperand(0).getReg();

747 Register SrcReg = MI.getOperand(1).getReg();

748

749 if ((DstReg.isPhysical() || MRI .getType(DstReg).isValid()) ||

750 (SrcReg.isPhysical() || MRI .getType(SrcReg).isValid())) {

753 if (!DstRB)

754 DstRB = SrcRB;

755 else if (!SrcRB)

756 SrcRB = DstRB;

757

758

759 assert(DstRB && SrcRB && "Both RegBank were nullptr");

764

765 1);

766 }

767

768 [[fallthrough]];

769 }

770 case TargetOpcode::G_BITCAST: {

771 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());

772 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

775 bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;

777 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;

779 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;

783

784 Opc == TargetOpcode::G_BITCAST ? 2 : 1);

785 }

786 default:

787 break;

788 }

789

790 unsigned NumOperands = MI.getNumOperands();

792

793

796 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

797 auto &MO = MI.getOperand(Idx);

798 if (!MO.isReg() || !MO.getReg())

799 continue;

800

801 LLT Ty = MRI.getType(MO.getReg());

802 if (!Ty.isValid())

803 continue;

804 OpSize[Idx] = Ty.getSizeInBits().getKnownMinValue();

805

806

807

808

809 if (Ty.isVector())

812 (MO.isDef() && onlyDefinesFP(MI, MRI, TRI)) ||

813 (MO.isUse() && onlyUsesFP(MI, MRI, TRI)) ||

814 Ty.getSizeInBits() > 64)

816 else

818 }

819

820 unsigned Cost = 1;

821

822

823 switch (Opc) {

824 case AArch64::G_DUP: {

825 Register ScalarReg = MI.getOperand(1).getReg();

826 LLT ScalarTy = MRI.getType(ScalarReg);

827 auto ScalarDef = MRI.getVRegDef(ScalarReg);

828

829 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)

831

834 onlyDefinesFP(*ScalarDef, MRI, TRI)))

836 else {

839

841 }

843 }

844 break;

845 }

846 case TargetOpcode::G_TRUNC: {

847 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

848 if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128)

850 break;

851 }

852 case TargetOpcode::G_SITOFP:

853 case TargetOpcode::G_UITOFP: {

854 if (MRI.getType(MI.getOperand(0).getReg()).isVector())

855 break;

856

857

858 Register SrcReg = MI.getOperand(1).getReg();

860 MRI.getType(SrcReg).getSizeInBits() ==

861 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits())

863 else

865 break;

866 }

867 case TargetOpcode::G_FPTOSI_SAT:

868 case TargetOpcode::G_FPTOUI_SAT:

869 case TargetOpcode::G_FPTOSI:

870 case TargetOpcode::G_FPTOUI: {

871 LLT DstType = MRI.getType(MI.getOperand(0).getReg());

872 if (DstType.isVector())

873 break;

876 break;

877 }

880 if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&

881 all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

883 return onlyUsesFP(UseMI, MRI, TRI) ||

884 prefersFPUse(UseMI, MRI, TRI);

885 }))

887 else

889 break;

890 }

891 case TargetOpcode::G_INTRINSIC_LRINT:

892 case TargetOpcode::G_INTRINSIC_LLRINT:

893 if (MRI.getType(MI.getOperand(0).getReg()).isVector())

894 break;

896 break;

897 case TargetOpcode::G_FCMP: {

898

902 OpRegBankIdx = {Idx0,

904 break;

905 }

906 case TargetOpcode::G_BITCAST:

907

908 if (OpRegBankIdx[0] != OpRegBankIdx[1])

913 break;

914 case TargetOpcode::G_LOAD: {

915

916

917

918

919

920

923 break;

924 }

925

927

929 break;

930 }

931

932

933 if (isLoadFromFPType(MI)) {

935 break;

936 }

937

938

939

940

941 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

943

944

945

946

947

948

949

950

951

952 if (isPHIWithFPConstraints(UseMI, MRI, TRI))

953 return true;

954

955 return onlyUsesFP(UseMI, MRI, TRI) ||

956 prefersFPUse(UseMI, MRI, TRI);

957 }))

959 break;

960 }

961 case TargetOpcode::G_STORE:

962

964 Register VReg = MI.getOperand(0).getReg();

965 if (!VReg)

966 break;

970 break;

971 }

972 break;

973 case TargetOpcode::G_INDEXED_STORE:

975 Register VReg = MI.getOperand(1).getReg();

976 if (!VReg)

977 break;

981 break;

982 }

983 break;

984 case TargetOpcode::G_INDEXED_SEXTLOAD:

985 case TargetOpcode::G_INDEXED_ZEXTLOAD:

986

988 break;

989 case TargetOpcode::G_INDEXED_LOAD: {

990 if (isLoadFromFPType(MI))

992 break;

993 }

994 case TargetOpcode::G_SELECT: {

995

997 break;

998

999

1000

1001 LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());

1002 if (SrcTy.isVector()) {

1004 break;

1005 }

1006

1007

1008

1009

1010 unsigned NumFP = 0;

1011

1012

1013

1014

1015

1016

1017

1018 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

1019 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))

1020 ++NumFP;

1021

1022

1023

1024

1025

1026

1027

1028

1029

1030

1031

1032

1033

1034

1035 for (unsigned Idx = 2; Idx < 4; ++Idx) {

1036 Register VReg = MI.getOperand(Idx).getReg();

1040 ++NumFP;

1041 }

1042

1043

1044

1045 if (NumFP >= 2)

1047

1048 break;

1049 }

1050 case TargetOpcode::G_UNMERGE_VALUES: {

1051

1052

1054 break;

1055

1056 LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());

1057

1058

1059 if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||

1060 any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

1061 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {

1062

1063 for (unsigned Idx = 0, NumOperands = MI.getNumOperands();

1064 Idx < NumOperands; ++Idx)

1066 }

1067 break;

1068 }

1069 case TargetOpcode::G_EXTRACT_VECTOR_ELT:

1070

1073

1074

1076 break;

1077 case TargetOpcode::G_INSERT_VECTOR_ELT:

1080

1081

1082 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)

1084 else {

1085

1086

1087 LLT Ty = MRI.getType(MI.getOperand(2).getReg());

1088 if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16) {

1089

1091 }

1093 }

1094

1095

1097 break;

1098 case TargetOpcode::G_EXTRACT: {

1099

1100 auto Src = MI.getOperand(1).getReg();

1101 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

1102 if (SrcTy.getSizeInBits() != 128)

1103 break;

1104 auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass

1107 OpRegBankIdx[0] = Idx;

1108 OpRegBankIdx[1] = Idx;

1109 break;

1110 }

1111 case TargetOpcode::G_BUILD_VECTOR: {

1112

1113

1115 break;

1116 Register VReg = MI.getOperand(1).getReg();

1117 if (!VReg)

1118 break;

1119

1120

1121

1122

1123

1124

1126 unsigned DefOpc = DefMI->getOpcode();

1127 const LLT SrcTy = MRI.getType(VReg);

1129 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==

1130 TargetOpcode::G_CONSTANT;

1131 }))

1132 break;

1134 SrcTy.getSizeInBits() < 32 ||

1136

1137

1138 unsigned NumOperands = MI.getNumOperands();

1139 for (unsigned Idx = 0; Idx < NumOperands; ++Idx)

1141 }

1142 break;

1143 }

1144 case TargetOpcode::G_VECREDUCE_FADD:

1145 case TargetOpcode::G_VECREDUCE_FMUL:

1146 case TargetOpcode::G_VECREDUCE_FMAX:

1147 case TargetOpcode::G_VECREDUCE_FMIN:

1148 case TargetOpcode::G_VECREDUCE_FMAXIMUM:

1149 case TargetOpcode::G_VECREDUCE_FMINIMUM:

1150 case TargetOpcode::G_VECREDUCE_ADD:

1151 case TargetOpcode::G_VECREDUCE_MUL:

1152 case TargetOpcode::G_VECREDUCE_AND:

1153 case TargetOpcode::G_VECREDUCE_OR:

1154 case TargetOpcode::G_VECREDUCE_XOR:

1155 case TargetOpcode::G_VECREDUCE_SMAX:

1156 case TargetOpcode::G_VECREDUCE_SMIN:

1157 case TargetOpcode::G_VECREDUCE_UMAX:

1158 case TargetOpcode::G_VECREDUCE_UMIN:

1159

1160

1162 break;

1163 case TargetOpcode::G_VECREDUCE_SEQ_FADD:

1164 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:

1165

1166

1168 break;

1169 case TargetOpcode::G_INTRINSIC:

1170 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {

1172 case Intrinsic::aarch64_neon_fcvtas:

1173 case Intrinsic::aarch64_neon_fcvtau:

1174 case Intrinsic::aarch64_neon_fcvtzs:

1175 case Intrinsic::aarch64_neon_fcvtzu:

1176 case Intrinsic::aarch64_neon_fcvtms:

1177 case Intrinsic::aarch64_neon_fcvtmu:

1178 case Intrinsic::aarch64_neon_fcvtns:

1179 case Intrinsic::aarch64_neon_fcvtnu:

1180 case Intrinsic::aarch64_neon_fcvtps:

1181 case Intrinsic::aarch64_neon_fcvtpu: {

1183 if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {

1185 break;

1186 }

1189 if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&

1190 all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

1192 return onlyUsesFP(UseMI, MRI, TRI) ||

1193 prefersFPUse(UseMI, MRI, TRI);

1194 }))

1196 else

1198 break;

1199 }

1200 case Intrinsic::aarch64_neon_vcvtfxs2fp:

1201 case Intrinsic::aarch64_neon_vcvtfxu2fp:

1202 case Intrinsic::aarch64_neon_vcvtfp2fxs:

1203 case Intrinsic::aarch64_neon_vcvtfp2fxu:

1204

1205

1206

1209

1210

1211 break;

1212 default: {

1213

1214

1215 unsigned Idx = 0;

1216 if (onlyDefinesFP(MI, MRI, TRI))

1217 for (const auto &Op : MI.defs()) {

1218 if (Op.isReg())

1220 ++Idx;

1221 }

1222 else

1223 Idx += MI.getNumExplicitDefs();

1224

1225 if (onlyUsesFP(MI, MRI, TRI))

1226 for (const auto &Op : MI.explicit_uses()) {

1227 if (Op.isReg())

1229 ++Idx;

1230 }

1231 break;

1232 }

1233 }

1234 break;

1235 }

1236 case TargetOpcode::G_LROUND:

1237 case TargetOpcode::G_LLROUND: {

1238

1240 break;

1241 }

1242 }

1243

1244

1246 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

1247 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {

1248 LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());

1249 if (!Ty.isValid())

1250 continue;

1251 auto Mapping =

1253 if (!Mapping->isValid())

1255

1256 OpdsMapping[Idx] = Mapping;

1257 }

1258 }

1259

1261 NumOperands);

1262}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

static unsigned getIntrinsicID(const SDNode *N)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define CHECK_VALUEMAP(RBName, Size)

static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)

Definition AArch64RegisterBankInfo.cpp:452

#define CHECK_VALUEMAP_3OPS(RBName, Size)

static const unsigned CustomMappingID

Definition AArch64RegisterBankInfo.cpp:45

#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)

#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)

#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)

This file declares the targeting of the RegisterBankInfo class for AArch64.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

Implement a low-level type suitable for MachineInstr level instruction selection.

This file declares the MachineIRBuilder class.

static const MCPhysReg FPR[]

FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.

This file defines the SmallVector class.

static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, TypeSize Size)

static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, TypeSize Size)

Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...

static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)

static const RegisterBankInfo::PartialMapping PartMappings[]

static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)

Get the instruction mapping for G_FPEXT.

static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, TypeSize Size)

Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.

static const RegisterBankInfo::ValueMapping ValMappings[]

InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override

Get the alternative mappings for MI.

Definition AArch64RegisterBankInfo.cpp:254

unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Definition AArch64RegisterBankInfo.cpp:221

const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override

Get a register bank that covers RC.

Definition AArch64RegisterBankInfo.cpp:243

AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)

Definition AArch64RegisterBankInfo.cpp:47

const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override

Get the mapping of the different operands of MI on the register bank.

Definition AArch64RegisterBankInfo.cpp:687

const AArch64RegisterInfo * getRegisterInfo() const override

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Helper class to build MachineInstr.

MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ANYEXT Op0.

Get the register for the operand index.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Helper class that represents how the value of an instruction may be mapped and what is the related co...

bool isValid() const

Check whether this object is valid.

virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const

Get the alternative mappings for MI.

const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const

Method to get a uniquely generated InstructionMapping.

static void applyDefaultMapping(const OperandsMapper &OpdMapper)

Helper method to apply something that is like the default mapping.

const InstructionMapping & getInvalidInstructionMapping() const

Method to get a uniquely generated invalid InstructionMapping.

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

unsigned getMaximumSize(unsigned RegBankID) const

Get the maximum size in bits that fits in the given register bank.

TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

Get the size in bits of Reg.

virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const

Get a register bank that covers RC.

const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

static const unsigned DefaultMappingID

Identifier used when the related instruction mapping instance is generated by target independent code...

SmallVector< const InstructionMapping *, 4 > InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const

Try to get the mapping of MI.

This class implements the register bank concept.

LLVM_ABI bool covers(const TargetRegisterClass &RC) const

Check whether this register bank covers RC.

unsigned getID() const

Get the identifier of this register bank.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

unsigned getID() const

Return the register class ID number.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

static constexpr TypeSize getFixed(ScalarTy ExactSize)

Type * getArrayElementType() const

bool isFPOrFPVectorTy() const

Return true if this is a FP type or a vector of FP.

iterator_range< user_iterator > users()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

bool isPreISelGenericOpcode(unsigned Opcode)

Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.

bool isPreISelGenericOptimizationHint(unsigned Opcode)

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

DWARFExpression::Operation Op

void call_once(once_flag &flag, Function &&F, Args &&... ArgList)

Execute the function specified as a parameter once.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...

The llvm::once_flag structure.