AArch64Subtarget.cpp Source File (original) (raw)

30using namespace llvm;

32#define DEBUG_TYPE "aarch64-subtarget"

34#define GET_SUBTARGETINFO_CTOR

35#define GET_SUBTARGETINFO_TARGET_DESC

36#include "AArch64GenSubtargetInfo.inc"

48 "aarch64-macho-enable-nonlazybind",

49 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),

53 cl::desc("Enable the use of AA during codegen."));

56 "aarch64-insert-extract-base-cost",

64 "registers, so they can't be used by register allocator. "

65 "Should only be used for testing register allocator."),

71 cl::desc("Override the variant of check applied "

72 "to authenticated LR during tail call"),

77 cl::desc("Set minimum number of entries to use a jump table on AArch64"));

80 "aarch64-streaming-hazard-size",

81 cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."),

85 "aarch64-stack-hazard-size",

86 cl::desc("alias for -aarch64-streaming-hazard-size"),

91 cl::desc("Force a vscale for tuning factor for SVE"));

98 cl::desc("Enable subreg liveness tracking"));

102 cl::desc("Prefer add+cnt over addvl/inc/dec"));

103

109

110AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(

112 bool HasMinSize) {

113

114

115 if (CPUString.empty())

116 CPUString = "generic";

117

118 if (TuneCPUString.empty())

119 TuneCPUString = CPUString;

120

122 initializeProperties(HasMinSize);

123

124 return *this;

125}

126

127void AArch64Subtarget::initializeProperties(bool HasMinSize) {

128

129

130

133

134

135

136 if (hasV8_4aOps() && !hasV8_8aOps())

137 AvoidLDAPUR = true;

138 break;

139 case Carmel:

141 break;

142 case CortexA35:

143 case CortexA53:

144 case CortexA55:

145 case CortexR82:

146 case CortexR82AE:

150 break;

151 case CortexA57:

156 break;

157 case CortexA65:

159 break;

160 case CortexA72:

161 case CortexA73:

162 case CortexA75:

166 break;

167 case CortexA76:

168 case CortexA77:

169 case CortexA78:

170 case CortexA78AE:

171 case CortexA78C:

172 case CortexX1:

176 break;

177 case CortexA320:

178 case CortexA510:

179 case CortexA520:

184 break;

185 case CortexA710:

186 case CortexA715:

187 case CortexA720:

188 case CortexA725:

189 case CortexX2:

190 case CortexX3:

191 case CortexX4:

192 case CortexX925:

197 break;

198 case A64FX:

207 break;

208 case MONAKA:

210 break;

211 case AppleA7:

212 case AppleA10:

213 case AppleA11:

214 case AppleA12:

215 case AppleA13:

216 case AppleA14:

217 case AppleA15:

218 case AppleA16:

219 case AppleA17:

220 case AppleM4:

221 case AppleM5:

228 break;

229 case ExynosM3:

234 break;

235 case Falkor:

237

243 break;

244 case Kryo:

251

253 break;

254 case NeoverseE1:

256 break;

257 case NeoverseN1:

261 break;

262 case NeoverseV2:

263 case NeoverseV3:

268 [[fallthrough]];

269 case NeoverseN2:

270 case NeoverseN3:

275 break;

276 case NeoverseV1:

282 break;

283 case Neoverse512TVB:

287 break;

288 case Saphira:

290

292 break;

293 case ThunderX2T99:

301

303 break;

304 case ThunderX:

305 case ThunderXT88:

306 case ThunderXT81:

307 case ThunderXT83:

311

313 break;

314 case TSV110:

318 break;

319 case ThunderX3T110:

327

329 break;

330 case Ampere1:

331 case Ampere1A:

332 case Ampere1B:

337 break;

338 case Oryon:

344 break;

345 case Olympus:

353 break;

354 }

355

360}

361

365 unsigned MinSVEVectorSizeInBitsOverride,

366 unsigned MaxSVEVectorSizeInBitsOverride,

368 bool HasMinSize)

378 : std::nullopt),

381 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),

385

389

391

392

393

394

397

399

402 for (unsigned i = 0; i < 29; ++i) {

403 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))

405 }

406

407 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))

409

410 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))

412

414}

415

419

423

427

431

435

436

437

438unsigned

441

442

445

446

447

448

449

452

456 }

460 }

461

462

463

464

468

469

470

471

472

475

477}

478

481

482

486

487

492

496

497

500 }

502

503

505 }

506 }

507

508

510 }

511

513}

514

526

531 !Def->isInstr() || Use ->isInstr() ||

532 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&

533 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))

534 return;

535

536

537

539 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {

540 Register Reg = DefMI->getOperand(DefOpIdx).getReg();

542 if (Op.isReg() && Op.isDef() && Op.getReg() == Reg) {

544 DefOpIdx = Op.getOperandNo();

545 }

546 }

547 }

548

549

551 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) {

552 Register Reg = UseMI->getOperand(UseOpIdx).getReg();

554 if (Op.isReg() && Op.isUse() && Op.getReg() == Reg) {

556 UseOpIdx = Op.getOperandNo();

557 break;

558 }

559 }

560 }

561

564}

565

569

572 return false;

573

575 return true;

578 }

579

580 return false;

581}

582

583std::unique_ptr

585 return balanceFPOps() ? std::make_unique() : nullptr;

586}

587

597

599

601

602

605 return hasSVE2() || hasSME();

606}

607

608

609

610

611

612

613

614

615

616

617

618

619

620

635

636std::optional<uint16_t>

638 const Function &ParentFn) const {

639 if (!ParentFn.hasFnAttribute("ptrauth-indirect-gotos"))

640 return std::nullopt;

641

642

644 (Twine(ParentFn.getName()) + " blockaddress").str());

645}

646

652

654 return getSchedModel().hasInstrSchedModel();

655}

This file describes how to lower LLVM calls to machine code calls.

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

This file declares the targeting of the Machinelegalizer class for AArch64.

#define AUTH_CHECK_METHOD_CL_VALUES_LR

This file declares the targeting of the RegisterBankInfo class for AArch64.

static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)

static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(10), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))

static cl::opt< bool > MachOUseNonLazyBind("aarch64-macho-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"), cl::Hidden)

static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))

static cl::opt< bool > EnableSubregLivenessTracking("aarch64-enable-subreg-liveness-tracking", cl::init(false), cl::Hidden, cl::desc("Enable subreg liveness tracking"))

static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)

static cl::opt< unsigned > AArch64StreamingHazardSize("aarch64-streaming-hazard-size", cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."), cl::init(0), cl::Hidden)

static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))

static cl::alias AArch64StreamingStackHazardSize("aarch64-stack-hazard-size", cl::desc("alias for -aarch64-streaming-hazard-size"), cl::aliasopt(AArch64StreamingHazardSize))

static cl::opt< bool > UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden, cl::desc("Prefer add+cnt over addvl/inc/dec"))

static cl::opt< unsigned > VScaleForTuningOpt("sve-vscale-for-tuning", cl::Hidden, cl::desc("Force a vscale for tuning factor for SVE"))

static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)

static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)

static cl::opt< unsigned > MinPrefetchStride("min-prefetch-stride", cl::desc("Min stride to add prefetches"), cl::Hidden)

static cl::opt< unsigned > PrefetchDistance("prefetch-distance", cl::desc("Number of instructions to prefetch ahead"), cl::Hidden)

static cl::opt< unsigned > MaxPrefetchIterationsAhead("max-prefetch-iters-ahead", cl::desc("Max number of iterations to prefetch ahead"), cl::Hidden)

static const unsigned MaxInterleaveFactor

Maximum vectorization interleave count.

static cl::opt< unsigned > EpilogueVectorizationMinVF("epilogue-vectorization-minimum-VF", cl::Hidden, cl::desc("Only loops with vectorization factor equal to or larger than " "the specified value are considered for epilogue vectorization."))

static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))

This class provides the information for the target register banks.

AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)

This constructor initializes the data members to match that of the specified triple.

Definition AArch64Subtarget.cpp:362

BitVector ReserveXRegisterForRA

BitVector ReserveXRegister

const CallLowering * getCallLowering() const override

Definition AArch64Subtarget.cpp:416

const AArch64RegisterInfo * getRegisterInfo() const override

TailFoldingOpts DefaultSVETFOpts

BitVector CustomCallSavedXRegs

bool IsStreamingCompatible

std::unique_ptr< InstructionSelector > InstSelector

ARMProcFamilyEnum ARMProcFamily

ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.

std::unique_ptr< RegisterBankInfo > RegBankInfo

bool useSmallAddressing() const

std::optional< unsigned > StreamingHazardSize

bool isTargetDarwin() const

bool enableEarlyIfConversion() const override

Definition AArch64Subtarget.cpp:566

const InlineAsmLowering * getInlineAsmLowering() const override

Definition AArch64Subtarget.cpp:420

unsigned getVectorInsertExtractBaseCost() const

Definition AArch64Subtarget.cpp:104

bool enableMachinePipeliner() const override

Definition AArch64Subtarget.cpp:653

std::unique_ptr< CallLowering > CallLoweringInfo

GlobalISel related APIs.

std::optional< uint16_t > getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const

Compute the integer discriminator for a given BlockAddress constant, if blockaddress signing is enabl...

Definition AArch64Subtarget.cpp:637

unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const

Definition AArch64Subtarget.cpp:479

bool useAA() const override

Definition AArch64Subtarget.cpp:598

uint8_t VectorInsertExtractBaseCost

const AArch64TargetLowering * getTargetLowering() const override

bool isTargetMachO() const

bool supportsAddressTopByteIgnored() const

CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.

Definition AArch64Subtarget.cpp:570

void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Definition AArch64Subtarget.cpp:515

Align PrefFunctionAlignment

const Triple & getTargetTriple() const

unsigned MinVectorRegisterBitWidth

void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override

Definition AArch64Subtarget.cpp:527

void mirFileLoaded(MachineFunction &MF) const override

Definition AArch64Subtarget.cpp:588

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

InstructionSelector * getInstructionSelector() const override

Definition AArch64Subtarget.cpp:424

unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...

Definition AArch64Subtarget.cpp:439

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

unsigned MaxJumpTableSize

bool isWindowsArm64EC() const

unsigned MinSVEVectorSizeInBits

bool isX16X17Safer() const

Returns whether the operating system makes it safer to store sensitive values in x16 and x17 as oppos...

Definition AArch64Subtarget.cpp:647

bool useScalarIncVL() const

Returns true to use the addvl/inc/dec instructions, as opposed to separate add + cnt instructions.

Definition AArch64Subtarget.cpp:600

unsigned MinimumJumpTableEntries

const LegalizerInfo * getLegalizerInfo() const override

Definition AArch64Subtarget.cpp:428

unsigned MaxSVEVectorSizeInBits

bool EnableSubregLiveness

std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override

Definition AArch64Subtarget.cpp:584

AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod(const MachineFunction &MF) const

Choose a method of checking LR before performing a tail call.

Definition AArch64Subtarget.cpp:621

AArch64InstrInfo InstrInfo

AArch64TargetLowering TLInfo

const RegisterBankInfo * getRegBankInfo() const override

Definition AArch64Subtarget.cpp:432

std::unique_ptr< LegalizerInfo > Legalizer

unsigned MaxBytesForLoopAlignment

std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo

bool isAppleMLike() const

Returns true if the processor is an Apple M-series or aligned A-series (A14 or newer).

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

bool hasExternalLinkage() const

bool hasExternalWeakLinkage() const

bool hasDLLImportStorageClass() const

bool hasInternalLinkage() const

Type * getValueType() const

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

LLVM_ABI void computeMaxCallFrameSize(MachineFunction &MF, std::vector< MachineBasicBlock::iterator > *FrameSDOps=nullptr)

Computes the maximum size of a callframe.

bool isMaxCallFrameSizeComputed() const

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

Holds all the information related to register banks.

Wrapper class representing virtual and physical registers.

Kind getKind() const

Returns an enum value representing the kind of the dependence.

@ Data

Regular data dependence (aka true-dependence).

void setLatency(unsigned Lat)

Sets the latency for this edge.

Returns the register associated with this edge.

Scheduling unit. This is a node in the scheduling DAG.

size_type count(StringRef Key) const

count - Return 1 if the element is in the map, 0 otherwise.

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

StringSet - A wrapper for StringMap that provides set-like functionality.

Primary interface to the complete machine description for the target machine.

bool shouldAssumeDSOLocal(const GlobalValue *GV) const

CodeModel::Model getCodeModel() const

Returns the code model.

Provide an instruction scheduling machine model to CodeGen passes.

LLVM_ABI unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const

Compute operand latency based on the available machine model.

Triple - Helper class for working with autoconf configuration names.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

bool isFunctionTy() const

True if this is an instance of FunctionType.

A Use represents the edge between a Value definition and its users.

LLVM_ABI StringRef getName() const

Return a constant reference to the value's name.

Represents a version number in the form major[.minor[.subminor[.build]]].

@ MO_DLLIMPORT

MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...

@ MO_NC

MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.

@ MO_GOT

MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...

@ MO_ARM64EC_CALLMANGLE

MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...

@ MO_TAGGED

MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.

@ MO_COFFSTUB

MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....

AuthCheckMethod

Variants of check performed on an authenticated pointer.

@ HighBitsNoTBI

Check by comparing bits 62 and 61 of the authenticated address.

@ None

Do not check the value at all.

LLVM_ABI bool isX18ReservedByDefault(const Triple &TT)

ValuesClass values(OptsTy... Options)

Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

constexpr from_range_t from_range

InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, const AArch64Subtarget &, const AArch64RegisterBankInfo &)

iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI uint16_t getPointerAuthStableSipHash(StringRef S)

Compute a stable non-zero 16-bit hash of the given string.

DWARFExpression::Operation Op

Implement std::hash so that hash_code can be used in STL containers.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

bool DisableLatencyHeuristic

A region of an MBB for scheduling.