LLVM: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Source File (original) (raw)
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9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
18#include
19#include
20#include
21
22
23#define GET_INSTRINFO_OPERAND_ENUM
24#include "AMDGPUGenInstrInfo.inc"
25
27
28namespace llvm {
29
30struct Align;
31class Argument;
32class Function;
33class GlobalValue;
34class MCInstrInfo;
35class MCRegisterClass;
36class MCRegisterInfo;
37class MCSubtargetInfo;
38class MDNode;
39class StringRef;
40class Triple;
41class raw_ostream;
42
43namespace AMDGPU {
44
45struct AMDGPUMCKernelCodeT;
46struct IsaVersion;
47
48
49
50
51
53static constexpr unsigned GFX9 = 1;
54static constexpr unsigned GFX9_4 = 1;
55static constexpr unsigned GFX10_1 = 1;
56static constexpr unsigned GFX10_3 = 1;
57static constexpr unsigned GFX11 = 1;
58static constexpr unsigned GFX12 = 1;
59}
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128#define GET_MIMGBaseOpcode_DECL
129#define GET_MIMGDim_DECL
130#define GET_MIMGEncoding_DECL
131#define GET_MIMGLZMapping_DECL
132#define GET_MIMGMIPMapping_DECL
133#define GET_MIMGBiASMapping_DECL
134#define GET_MAIInstInfoTable_DECL
135#define GET_isMFMA_F8F6F4Table_DECL
136#define GET_isCvtScaleF32_F32F16ToF8F4Table_DECL
137#define GET_True16D16Table_DECL
138#define GET_WMMAInstInfoTable_DECL
139#include "AMDGPUGenSearchableTables.inc"
140
141namespace IsaInfo {
142
143enum {
144
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148};
149
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153private:
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158public:
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186 XnackSetting = NewXnackSetting;
187 }
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213 SramEccSetting = NewSramEccSetting;
214 }
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220 std::string toString() const;
221};
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240 unsigned FlatWorkGroupSize);
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253 unsigned FlatWorkGroupSize);
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264 unsigned FlatWorkGroupSize);
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285 bool Addressable);
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290 bool FlatScrUsed, bool XNACKUsed);
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296 bool FlatScrUsed);
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307unsigned
309 std::optional EnableWavefrontSize32 = std::nullopt);
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317 std::optional EnableWavefrontSize32 = std::nullopt);
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332 unsigned DynamicVGPRBlockSize);
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337 unsigned DynamicVGPRBlockSize);
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342 unsigned DynamicVGPRBlockSize);
343
344
345
347 unsigned NumVGPRs,
348 unsigned DynamicVGPRBlockSize);
349
350
351
353 unsigned MaxWaves,
354 unsigned TotalNumVGPRs);
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369 std::optional EnableWavefrontSize32 = std::nullopt);
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375 unsigned DynamicVGPRBlockSize,
376 std::optional EnableWavefrontSize32 = std::nullopt);
377
378}
379
380
381template <unsigned HighBit, unsigned LowBit, unsigned D = 0>
383 static_assert(HighBit >= LowBit, "Invalid bit range!");
384 static constexpr unsigned Offset = LowBit;
385 static constexpr unsigned Width = HighBit - LowBit + 1;
386
389
392
395};
396
397
398template <unsigned Bit, unsigned D = 0>
400
401
404 return ((Values.encode() << Values.Offset) | ...);
405 }
406
407 static std::tuple decode(uint64_t Encoded) {
408 return {Fields::decode((Encoded >> Fields::Offset) &
409 maxUIntN(Fields::Width))...};
410 }
411};
412
415 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
416}
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470};
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490};
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513int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
514 unsigned VDataDwords, unsigned VAddrDwords);
515
518
522 bool IsG16Supported);
523
532
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540int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
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558int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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628 unsigned BLGP,
629 unsigned F8F8Opcode);
630
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636 unsigned FmtB,
637 unsigned F8F8Opcode);
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655int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily,
656 bool VOPD3);
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672
673namespace VOPD {
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697private:
698 unsigned SrcOperandsNum = 0;
699 unsigned MandatoryLiteralIdx = ~0u;
700 bool HasSrc2Acc = false;
701 unsigned NumVOPD3Mods = 0;
702 unsigned Opcode = 0;
703 bool IsVOP3 = false;
704
705public:
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709
711
712
714 return SrcOperandsNum - HasSrc2Acc;
715 }
716
717
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721
724 return MandatoryLiteralIdx;
725 }
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731 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
732 }
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741 unsigned getOpcode() const { return Opcode; }
742
743
744 unsigned isVOP3() const { return IsVOP3; }
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749private:
750 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
753 }
754};
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794private:
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800 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
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808 static constexpr unsigned SINGLE_MC_SRC_IDX[4][3] = {
809 {1, 2, 3}, {2, 3, 4}, {2, 4, 5}, {2, 4, 6}};
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817 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
818 4 };
819 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
820 2, 2, 5 };
821
822private:
825 const unsigned VOPD3ModsNum;
826 const int BitOp3Idx;
827
828public:
829
831 : Kind(Kind), VOPD3ModsNum(VOPD3ModsNum), BitOp3Idx(BitOp3Idx) {
833 }
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835
837 int BitOp3Idx)
839 VOPD3ModsNum(VOPD3ModsNum), BitOp3Idx(BitOp3Idx) {}
840
841public:
842
844
845
848
849 if (Kind == SINGLE && CompSrcIdx == 2 && BitOp3Idx != -1)
850 return BitOp3Idx;
851
852 if (VOPD3) {
853 return SINGLE_MC_SRC_IDX[VOPD3ModsNum][CompSrcIdx] + getPrevCompSrcNum() +
854 getPrevCompVOPD3ModsNum() + (Kind != SINGLE ? 1 : 0);
855 }
856
857 return SINGLE_MC_SRC_IDX[0][CompSrcIdx] + getPrevCompSrcNum() +
858 (Kind != SINGLE ? 1 : 0);
859 }
860
861
863 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
864 }
865
866
869 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
870 }
871
872private:
873 unsigned getPrevCompSrcNum() const {
875 }
876 unsigned getPrevCompParsedSrcNum() const {
878 }
879 unsigned getPrevCompVOPD3ModsNum() const {
881 }
882};
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886public:
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890 bool VOP3Layout = false)
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896 bool VOP3Layout = false)
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904};
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908private:
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911public:
912 using RegIndices = std::array<MCRegister, Component::MAX_OPR_NUM>;
913
915 : CompInfo{OpX, OpY} {}
916
918 : CompInfo{OprInfoX, OprInfoY} {}
919
922 return CompInfo[ComponentIdx];
923 }
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935 bool
938 bool AllowSameVGPR = false, bool VOPD3 = false) const {
940 VOPD3)
941 .has_value();
942 }
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953 std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
955 bool AllowSameVGPR = false, bool VOPD3 = false) const;
956
957private:
959 getRegIndices(unsigned ComponentIdx,
960 std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
961 bool VOPD3) const;
962};
963
964}
965
967std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
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1047std::pair<unsigned, unsigned>
1049 std::pair<unsigned, unsigned> Default,
1050 bool OnlyFirstRequired = false);
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1061std::optional<std::pair<unsigned, std::optional>>
1063 bool OnlyFirstRequired = false);
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1070 unsigned Size,
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1073std::optional<SmallVector>
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1165void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt,
1166 unsigned &Expcnt, unsigned &Lgkmcnt);
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1172 unsigned Vmcnt);
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1176 unsigned Expcnt);
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1180 unsigned Lgkmcnt);
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1201 unsigned Expcnt, unsigned Lgkmcnt);
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1259namespace Hwreg {
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1272}
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1347}
1348
1349namespace Exp {
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1359}
1360
1361namespace MTBUFFormat {
1362
1364int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1365
1366void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
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1368int64_t getDfmt(const StringRef Name);
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1371
1372int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
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1374StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
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1376bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
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1378bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
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1380int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
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1387 const MCSubtargetInfo &STI);
1388
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1392
1393}
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1398bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
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1401bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1402 bool Strict = true);
1403
1406 const MCSubtargetInfo &STI, bool Strict = true);
1407
1409bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1410
1412bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1413
1414void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1415 uint16_t &StreamId, const MCSubtargetInfo &STI);
1416
1418uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId);
1419
1420}
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1436 switch (CC) {
1446 return true;
1447 default:
1448 return false;
1449 }
1450}
1451
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1462
1465 switch (CC) {
1475 return true;
1476 default:
1477 return false;
1478 }
1479}
1480
1483 switch (CC) {
1486 return true;
1487 default:
1488 return false;
1489 }
1490}
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1500 switch (CC) {
1502 return true;
1503 default:
1505 }
1506}
1507
1510 switch (CC) {
1513 return true;
1514 default:
1515 return false;
1516 }
1517}
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1529 switch (CC) {
1533 return true;
1534 default:
1536 }
1537}
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1588int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
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1637 switch (OpInfo.OperandType) {
1649 return 4;
1650
1657 return 8;
1658
1672 return 2;
1673
1674 default:
1676 }
1677}
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1742 int64_t EncodedOffset);
1743
1746 int64_t EncodedOffset, bool IsBuffer);
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1757 int64_t ByteOffset, bool IsBuffer,
1758 bool HasSOffset = false);
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1763 int64_t ByteOffset);
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1820std::pair<const AMDGPU::OpName *, const AMDGPU::OpName *>
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1832public:
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1855 const std::array<unsigned, 3> &getDims() const;
1856
1858 return AttrKind == RHS.AttrKind && Dims == RHS.Dims;
1859 }
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1865private:
1866 enum Encoding { EncoNoCluster = 0, EncoVariableDims = 1024 };
1867
1869
1870 std::array<unsigned, 3> Dims = {0, 0, 0};
1871
1873};
1874
1875}
1876
1879
1880}
1881
1882#endif
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Base class for AMDGPU specific classes of TargetSubtarget.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Module.h This file contains the declarations for the Module class.
Register const TargetRegisterInfo * TRI
unsigned unsigned DefaultVal
Definition AMDGPUBaseInfo.h:1831
bool isNoCluster() const
Definition AMDGPUBaseInfo.h:1841
void setUnknown()
Definition AMDGPUBaseInfo.h:1847
static ClusterDimsAttr get(const Function &F)
bool isFixedDims() const
Definition AMDGPUBaseInfo.h:1843
Kind
Definition AMDGPUBaseInfo.h:1833
@ FixedDims
Definition AMDGPUBaseInfo.h:1833
@ NoCluster
Definition AMDGPUBaseInfo.h:1833
@ Unknown
Definition AMDGPUBaseInfo.h:1833
@ VariableDims
Definition AMDGPUBaseInfo.h:1833
Kind getKind() const
Definition AMDGPUBaseInfo.h:1837
ClusterDimsAttr()=default
void setNoCluster()
Definition AMDGPUBaseInfo.h:1849
bool isUnknown() const
Definition AMDGPUBaseInfo.h:1839
void setVariableDims()
Definition AMDGPUBaseInfo.h:1851
bool operator==(const ClusterDimsAttr &RHS) const
Definition AMDGPUBaseInfo.h:1857
std::string to_string() const
const std::array< unsigned, 3 > & getDims() const
bool isVariableDims() const
Definition AMDGPUBaseInfo.h:1845
bool isSramEccSupported() const
Definition AMDGPUBaseInfo.h:190
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Definition AMDGPUBaseInfo.h:185
bool isSramEccOnOrAny() const
Definition AMDGPUBaseInfo.h:195
TargetIDSetting getXnackSetting() const
Definition AMDGPUBaseInfo.h:182
bool isXnackOnOrAny() const
Definition AMDGPUBaseInfo.h:168
AMDGPUTargetID(const MCSubtargetInfo &STI)
bool isXnackOnOrOff() const
Definition AMDGPUBaseInfo.h:175
bool isXnackSupported() const
Definition AMDGPUBaseInfo.h:163
void setTargetIDFromTargetIDStream(StringRef TargetID)
~AMDGPUTargetID()=default
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
Definition AMDGPUBaseInfo.h:212
bool isSramEccOnOrOff() const
Definition AMDGPUBaseInfo.h:202
std::string toString() const
TargetIDSetting getSramEccSetting() const
Definition AMDGPUBaseInfo.h:209
Definition AMDGPUBaseInfo.h:885
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE, bool VOP3Layout=false)
Definition AMDGPUBaseInfo.h:888
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps, bool VOP3Layout=false)
Definition AMDGPUBaseInfo.h:895
unsigned getIndexOfDstInMCOperands() const
Definition AMDGPUBaseInfo.h:843
unsigned getIndexOfDstInParsedOperands() const
Definition AMDGPUBaseInfo.h:862
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx, bool VOPD3) const
Definition AMDGPUBaseInfo.h:846
ComponentLayout(const ComponentProps &OpXProps, unsigned VOPD3ModsNum, int BitOp3Idx)
Definition AMDGPUBaseInfo.h:836
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
Definition AMDGPUBaseInfo.h:867
ComponentLayout(ComponentKind Kind, unsigned VOPD3ModsNum, int BitOp3Idx)
Definition AMDGPUBaseInfo.h:830
Definition AMDGPUBaseInfo.h:696
bool hasMandatoryLiteral() const
Definition AMDGPUBaseInfo.h:718
int getBitOp3OperandIdx() const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
Definition AMDGPUBaseInfo.h:729
bool hasSrc2Acc() const
Definition AMDGPUBaseInfo.h:735
unsigned getCompSrcOperandsNum() const
Definition AMDGPUBaseInfo.h:710
unsigned getMandatoryLiteralCompOperandIndex() const
Definition AMDGPUBaseInfo.h:722
unsigned isVOP3() const
Definition AMDGPUBaseInfo.h:744
unsigned getOpcode() const
Definition AMDGPUBaseInfo.h:741
unsigned getCompVOPD3ModsNum() const
Definition AMDGPUBaseInfo.h:738
unsigned getCompParsedSrcOperandsNum() const
Definition AMDGPUBaseInfo.h:713
std::optional< unsigned > getInvalidCompOperandIndex(std::function< MCRegister(unsigned, unsigned)> GetRegIdx, const MCRegisterInfo &MRI, bool SkipSrc=false, bool AllowSameVGPR=false, bool VOPD3=false) const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
Definition AMDGPUBaseInfo.h:917
bool hasInvalidOperand(std::function< MCRegister(unsigned, unsigned)> GetRegIdx, const MCRegisterInfo &MRI, bool SkipSrc=false, bool AllowSameVGPR=false, bool VOPD3=false) const
Definition AMDGPUBaseInfo.h:936
const ComponentInfo & operator[](size_t ComponentIdx) const
Definition AMDGPUBaseInfo.h:920
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
Definition AMDGPUBaseInfo.h:914
std::array< MCRegister, Component::MAX_OPR_NUM > RegIndices
Definition AMDGPUBaseInfo.h:912
This class represents an incoming formal argument to a Function.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
This holds information about one operand of a machine instruction, indicating the register class for ...
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Triple - Helper class for working with autoconf configuration names.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned decodeFieldVaVcc(unsigned Encoded)
unsigned encodeFieldVaVcc(unsigned Encoded, unsigned VaVcc)
unsigned encodeFieldHoldCnt(unsigned Encoded, unsigned HoldCnt)
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaSsrc(unsigned Encoded, unsigned VaSsrc)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned decodeFieldVaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
unsigned decodeFieldVaSsrc(unsigned Encoded)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
unsigned decodeFieldHoldCnt(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
unsigned encodeFieldVaSdst(unsigned Encoded, unsigned VaSdst)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
Generic target versions emitted by this version of LLVM.
Definition AMDGPUBaseInfo.h:52
static constexpr unsigned GFX9_4
Definition AMDGPUBaseInfo.h:54
static constexpr unsigned GFX10_1
Definition AMDGPUBaseInfo.h:55
static constexpr unsigned GFX10_3
Definition AMDGPUBaseInfo.h:56
static constexpr unsigned GFX11
Definition AMDGPUBaseInfo.h:57
static constexpr unsigned GFX9
Definition AMDGPUBaseInfo.h:53
static constexpr unsigned GFX12
Definition AMDGPUBaseInfo.h:58
EncodingField< 10, 6 > HwregOffset
Definition AMDGPUBaseInfo.h:1262
EncodingField< 5, 0 > HwregId
Definition AMDGPUBaseInfo.h:1261
EncodingFields< HwregId, HwregOffset, HwregSize > HwregEncoding
Definition AMDGPUBaseInfo.h:1270
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
@ TRAP_NUM_SGPRS
Definition AMDGPUBaseInfo.h:147
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition AMDGPUBaseInfo.h:146
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getArchVGPRAllocGranule()
For subtargets with a unified VGPR file and mixed ArchVGPR/AGPR usage, returns the allocation granule...
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs, unsigned DynamicVGPRBlockSize)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, unsigned DynamicVGPRBlockSize, std::optional< bool > EnableWavefrontSize32)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, unsigned DynamicVGPRBlockSize)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
TargetIDSetting
Definition AMDGPUBaseInfo.h:150
@ On
Definition AMDGPUBaseInfo.h:150
@ Unsupported
Definition AMDGPUBaseInfo.h:150
@ Off
Definition AMDGPUBaseInfo.h:150
@ Any
Definition AMDGPUBaseInfo.h:150
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, unsigned DynamicVGPRBlockSize)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, unsigned DynamicVGPRBlockSize, std::optional< bool > EnableWavefrontSize32)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI, unsigned DynamicVGPRBlockSize)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
Definition AMDGPUBaseInfo.h:688
constexpr unsigned COMPONENTS_NUM
Definition AMDGPUBaseInfo.h:693
constexpr unsigned VOPD3_VGPR_BANK_MASKS[]
Definition AMDGPUBaseInfo.h:689
ComponentIndex
Definition AMDGPUBaseInfo.h:691
@ X
Definition AMDGPUBaseInfo.h:691
@ Y
Definition AMDGPUBaseInfo.h:691
ComponentKind
Definition AMDGPUBaseInfo.h:756
@ COMPONENT_X
Definition AMDGPUBaseInfo.h:758
@ SINGLE
Definition AMDGPUBaseInfo.h:757
@ MAX
Definition AMDGPUBaseInfo.h:760
@ COMPONENT_Y
Definition AMDGPUBaseInfo.h:759
constexpr unsigned COMPONENTS[]
Definition AMDGPUBaseInfo.h:692
Component
Definition AMDGPUBaseInfo.h:675
@ MAX_SRC_NUM
Definition AMDGPUBaseInfo.h:682
@ MAX_OPR_NUM
Definition AMDGPUBaseInfo.h:683
@ DST
Definition AMDGPUBaseInfo.h:676
@ SRC2
Definition AMDGPUBaseInfo.h:679
@ DST_NUM
Definition AMDGPUBaseInfo.h:681
@ SRC1
Definition AMDGPUBaseInfo.h:678
@ SRC0
Definition AMDGPUBaseInfo.h:677
bool isPackedFP32Inst(unsigned Opc)
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isInlineValue(MCRegister Reg)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
EncodingField< Bit, Bit, D > EncodingBit
Definition AMDGPUBaseInfo.h:399
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool getWMMAIsXDL(unsigned Opc)
uint8_t wmmaScaleF8F6F4FormatToNumRegs(unsigned Fmt)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
LLVM_READNONE constexpr bool isShader(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1435
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
bool isDPMACCInstruction(unsigned Opc)
int getMTBUFElements(unsigned Opc)
bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI)
unsigned getTemporalHintType(const MCInstrDesc TID)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
FPType getFPDstSelType(unsigned Opc)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
@ AMDHSA_COV4
Definition AMDGPUBaseInfo.h:61
@ AMDHSA_COV5
Definition AMDGPUBaseInfo.h:61
@ AMDHSA_COV6
Definition AMDGPUBaseInfo.h:61
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
const MCRegisterClass * getVGPRPhysRegClass(MCRegister Reg, const MCRegisterInfo &MRI)
LLVM_READNONE constexpr bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1499
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool hasValueInRangeLikeMetadata(const MDNode &MD, int64_t Val)
Checks if Val is inside MD, a !range-like metadata.
LLVM_READONLY bool isInvalidSingleUseProducerInst(unsigned Opc)
uint8_t mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal)
LLVM_READONLY bool isInvalidSingleUseConsumerInst(unsigned Opc)
unsigned getVOPDOpcode(unsigned Opc, bool VOPD3)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
CanBeVOPD getCanBeVOPD(unsigned Opc, unsigned EncodingFamily, bool VOPD3)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
LLVM_READNONE bool isLegalDPALU_DPPControl(const MCSubtargetInfo &ST, unsigned DC)
Definition AMDGPUBaseInfo.h:1779
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
LLVM_READNONE constexpr bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition AMDGPUBaseInfo.h:1528
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx)
Definition AMDGPUBaseInfo.h:414
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool isDPALU_DPP32BitOpc(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
std::tuple< char, unsigned, unsigned > parseAsmPhysRegName(StringRef RegName)
Returns a valid charcode or 0 in the first entry if this is a valid physical register name.
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
LLVM_READNONE constexpr bool isKernel(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1509
bool getMUBUFHasVAddr(unsigned Opc)
bool isTrue16Inst(unsigned Opc)
LLVM_READNONE constexpr bool isEntryFunctionCC(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1464
unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
LLVM_READNONE constexpr bool isCompute(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1459
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isAsyncStore(unsigned Opc)
unsigned getDynamicVGPRBlockSize(const Function &F)
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getKmcntBitMask(const IsaVersion &Version)
MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs, const MCRegisterInfo &MRI)
If Reg is a low VGPR return a corresponding high VGPR with MSBs set.
unsigned getVmcntBitMask(const IsaVersion &Version)
FPType
Definition AMDGPUBaseInfo.h:63
@ FP4
Definition AMDGPUBaseInfo.h:63
@ FP8
Definition AMDGPUBaseInfo.h:63
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
unsigned getBitOp2(unsigned Opc)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
constexpr bool isSISrcOperand(const MCOperandInfo &OpInfo)
Is this an AMDGPU specific source operand?
Definition AMDGPUBaseInfo.h:1611
unsigned getXcntBitMask(const IsaVersion &Version)
bool isGenericAtomic(unsigned Opc)
const MFMA_F8F6F4_Info * getWMMA_F8F6F4_WithFormatArgs(unsigned FmtA, unsigned FmtB, unsigned F8F8Opcode)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition AMDGPUBaseInfo.h:1687
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFTfe(unsigned Opc)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > getVGPRLoweringOperandTables(const MCInstrDesc &Desc)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
std::tuple< char, unsigned, unsigned > parseAsmConstraintPhysReg(StringRef Constraint)
Returns a valid charcode or 0 in the first entry if this is a valid physical register constraint.
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
bool isGlobalSegment(const GlobalValue *GV)
int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_BF16
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_INT32
Operands with register, 32-bit, or 64-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_IMM_NOINLINE_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_INT32
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)
bool isNotGFX9Plus(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
bool isGFX1250(const MCSubtargetInfo &STI)
bool supportsWave32(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.h:1584
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
bool isTensorStore(unsigned Opc)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode)
MCRegister mc2PseudoReg(MCRegister Reg)
Convert hardware register Reg to a pseudo register.
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool supportsWGP(const MCSubtargetInfo &STI)
bool hasDynamicVGPR(const Function &F)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
Definition AMDGPUBaseInfo.h:1636
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)
LLVM_READNONE constexpr bool isChainCC(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1482
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
LLVM_READNONE constexpr bool canGuaranteeTCO(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1522
LLVM_READNONE constexpr bool isGraphics(CallingConv::ID CC)
Definition AMDGPUBaseInfo.h:1453
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily, bool VOPD3)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
const MFMA_F8F6F4_Info * getMFMA_F8F6F4_WithFormatArgs(unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
constexpr uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
FunctionAddr VTableAddr uintptr_t uintptr_t Version
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
Definition AMDGPUBaseInfo.h:611
bool X
Definition AMDGPUBaseInfo.h:612
bool Y
Definition AMDGPUBaseInfo.h:613
Definition AMDGPUBaseInfo.h:113
unsigned Opcode
Definition AMDGPUBaseInfo.h:114
Definition AMDGPUBaseInfo.h:382
static constexpr unsigned Width
Definition AMDGPUBaseInfo.h:385
unsigned ValueType
Definition AMDGPUBaseInfo.h:387
constexpr EncodingField(ValueType Value)
Definition AMDGPUBaseInfo.h:391
static constexpr unsigned Offset
Definition AMDGPUBaseInfo.h:384
ValueType Value
Definition AMDGPUBaseInfo.h:390
static constexpr ValueType Default
Definition AMDGPUBaseInfo.h:388
static ValueType decode(uint64_t Encoded)
Definition AMDGPUBaseInfo.h:394
constexpr uint64_t encode() const
Definition AMDGPUBaseInfo.h:393
Definition AMDGPUBaseInfo.h:402
static constexpr uint64_t encode(Fields... Values)
Definition AMDGPUBaseInfo.h:403
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
Definition AMDGPUBaseInfo.h:407
Definition AMDGPUBaseInfo.h:92
unsigned BitsPerComp
Definition AMDGPUBaseInfo.h:94
unsigned Format
Definition AMDGPUBaseInfo.h:93
unsigned DataFormat
Definition AMDGPUBaseInfo.h:97
unsigned NumFormat
Definition AMDGPUBaseInfo.h:96
unsigned NumComponents
Definition AMDGPUBaseInfo.h:95
Definition AMDGPUBaseInfo.h:1264
constexpr EncodingField(ValueType Value)
Definition AMDGPUBaseInfo.h:391
constexpr uint64_t encode() const
Definition AMDGPUBaseInfo.h:1266
static ValueType decode(uint64_t Encoded)
Definition AMDGPUBaseInfo.h:1267
Definition AMDGPUBaseInfo.h:100
bool is_gfx940_xdl
Definition AMDGPUBaseInfo.h:103
uint16_t Opcode
Definition AMDGPUBaseInfo.h:101
bool is_dgemm
Definition AMDGPUBaseInfo.h:102
Definition AMDGPUBaseInfo.h:106
unsigned F8F8Opcode
Definition AMDGPUBaseInfo.h:108
uint8_t NumRegsSrcB
Definition AMDGPUBaseInfo.h:110
unsigned Opcode
Definition AMDGPUBaseInfo.h:107
uint8_t NumRegsSrcA
Definition AMDGPUBaseInfo.h:109
Definition AMDGPUBaseInfo.h:421
bool Gather4
Definition AMDGPUBaseInfo.h:427
bool Gradients
Definition AMDGPUBaseInfo.h:430
bool G16
Definition AMDGPUBaseInfo.h:431
bool AtomicX2
Definition AMDGPUBaseInfo.h:425
bool Sampler
Definition AMDGPUBaseInfo.h:426
MIMGBaseOpcode BaseOpcode
Definition AMDGPUBaseInfo.h:422
bool NoReturn
Definition AMDGPUBaseInfo.h:438
bool HasD16
Definition AMDGPUBaseInfo.h:434
bool LodOrClampOrMip
Definition AMDGPUBaseInfo.h:433
bool Coordinates
Definition AMDGPUBaseInfo.h:432
bool MSAA
Definition AMDGPUBaseInfo.h:435
bool Store
Definition AMDGPUBaseInfo.h:423
bool Atomic
Definition AMDGPUBaseInfo.h:424
bool A16
Definition AMDGPUBaseInfo.h:437
bool PointSampleAccel
Definition AMDGPUBaseInfo.h:439
bool BVH
Definition AMDGPUBaseInfo.h:436
uint8_t NumExtraArgs
Definition AMDGPUBaseInfo.h:429
Definition AMDGPUBaseInfo.h:477
MIMGBaseOpcode NoBias
Definition AMDGPUBaseInfo.h:479
MIMGBaseOpcode Bias
Definition AMDGPUBaseInfo.h:478
Definition AMDGPUBaseInfo.h:448
uint8_t NumCoords
Definition AMDGPUBaseInfo.h:450
bool MSAA
Definition AMDGPUBaseInfo.h:452
const char * AsmSuffix
Definition AMDGPUBaseInfo.h:455
MIMGDim Dim
Definition AMDGPUBaseInfo.h:449
uint8_t NumGradients
Definition AMDGPUBaseInfo.h:451
uint8_t Encoding
Definition AMDGPUBaseInfo.h:454
bool DA
Definition AMDGPUBaseInfo.h:453
Definition AMDGPUBaseInfo.h:487
MIMGBaseOpcode G
Definition AMDGPUBaseInfo.h:488
MIMGBaseOpcode G16
Definition AMDGPUBaseInfo.h:489
Definition AMDGPUBaseInfo.h:524
uint8_t VDataDwords
Definition AMDGPUBaseInfo.h:528
uint16_t BaseOpcode
Definition AMDGPUBaseInfo.h:526
uint16_t Opcode
Definition AMDGPUBaseInfo.h:525
uint8_t VAddrDwords
Definition AMDGPUBaseInfo.h:529
uint8_t VAddrOperands
Definition AMDGPUBaseInfo.h:530
uint8_t MIMGEncoding
Definition AMDGPUBaseInfo.h:527
Definition AMDGPUBaseInfo.h:467
MIMGBaseOpcode LZ
Definition AMDGPUBaseInfo.h:469
MIMGBaseOpcode L
Definition AMDGPUBaseInfo.h:468
Definition AMDGPUBaseInfo.h:472
MIMGBaseOpcode NONMIP
Definition AMDGPUBaseInfo.h:474
MIMGBaseOpcode MIP
Definition AMDGPUBaseInfo.h:473
Definition AMDGPUBaseInfo.h:482
MIMGBaseOpcode Offset
Definition AMDGPUBaseInfo.h:483
MIMGBaseOpcode NoOffset
Definition AMDGPUBaseInfo.h:484
Definition AMDGPUBaseInfo.h:117
unsigned T16Op
Definition AMDGPUBaseInfo.h:118
unsigned HiOp
Definition AMDGPUBaseInfo.h:119
unsigned LoOp
Definition AMDGPUBaseInfo.h:120
Definition AMDGPUBaseInfo.h:123
bool is_wmma_xdl
Definition AMDGPUBaseInfo.h:125
uint16_t Opcode
Definition AMDGPUBaseInfo.h:124
Definition AMDGPUBaseInfo.h:495
unsigned Opcode3Addr
Definition AMDGPUBaseInfo.h:497
unsigned Opcode2Addr
Definition AMDGPUBaseInfo.h:496
Represents the counter values to wait for in an s_waitcnt instruction.
Definition AMDGPUBaseInfo.h:1083
unsigned ExpCnt
Definition AMDGPUBaseInfo.h:1085
unsigned XCnt
Definition AMDGPUBaseInfo.h:1091
unsigned LoadCnt
Definition AMDGPUBaseInfo.h:1084
bool hasWait() const
Definition AMDGPUBaseInfo.h:1104
unsigned BvhCnt
Definition AMDGPUBaseInfo.h:1089
unsigned StoreCnt
Definition AMDGPUBaseInfo.h:1087
unsigned SampleCnt
Definition AMDGPUBaseInfo.h:1088
Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt, unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt, unsigned XCnt)
Definition AMDGPUBaseInfo.h:1099
unsigned KmCnt
Definition AMDGPUBaseInfo.h:1090
bool hasWaitExceptStoreCnt() const
Definition AMDGPUBaseInfo.h:1106
bool hasWaitStoreCnt() const
Definition AMDGPUBaseInfo.h:1111
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Definition AMDGPUBaseInfo.h:1095
Waitcnt combined(const Waitcnt &Other) const
Definition AMDGPUBaseInfo.h:1113
unsigned DsCnt
Definition AMDGPUBaseInfo.h:1086
friend raw_ostream & operator<<(raw_ostream &OS, const AMDGPU::Waitcnt &Wait)