ARMCallLowering.cpp Source File (original) (raw)

45#include

46#include

47#include

48#include

49#include

51using namespace llvm;

58 cl::desc("Enable Global-ISel Big Endian Lowering"));

65 if (T->isArrayTy())

68 if (T->isStructTy()) {

71 auto StructT = cast(T);

72 for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)

73 if (StructT->getElementType(i) != StructT->getElementType(0))

74 return false;

76 }

81 return false;

85 if (VTSize == 64)

89 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;

90}

92namespace {

99 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}

100

105 "Unsupported size");

106

109 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));

110

111 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);

112

113 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);

114

116 return AddrReg.getReg(0);

117 }

118

121 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");

122 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");

123

126

127 Register ExtReg = extendRegister(ValVReg, VA);

128 MIRBuilder.buildCopy(PhysReg, ExtReg);

130 }

131

135 Register ExtReg = extendRegister(ValVReg, VA);

136 auto MMO = MIRBuilder.getMF().getMachineMemOperand(

138 MIRBuilder.buildStore(ExtReg, Addr, *MMO);

139 }

140

143 std::function<void()> *Thunk) override {

144 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");

145

147 assert(VA.needsCustom() && "Value doesn't need custom handling");

148

149

150 if (VA.getValVT() != MVT::f64)

151 return 0;

152

154 assert(NextVA.needsCustom() && "Value doesn't need custom handling");

155 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");

156

158 "Values belong to different arguments");

159

161 assert(NextVA.isRegLoc() && "Value should be in reg");

162

165 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);

166

167 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();

168 if (!IsLittle)

169 std::swap(NewRegs[0], NewRegs[1]);

170

171 if (Thunk) {

173 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);

174 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);

175 };

176 return 2;

177 }

178 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);

179 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);

180 return 2;

181 }

182

184};

185

186}

187

188

189

190bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,

193 if (!Val)

194

195 return true;

196

197 auto &MF = MIRBuilder.getMF();

198 const auto &F = MF.getFunction();

199

200 const auto &DL = MF.getDataLayout();

201 auto &TLI = *getTLI();

203 return false;

204

207

210

212 TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());

213

214 OutgoingValueAssigner RetAssigner(AssignFn);

215 ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);

217 MIRBuilder, F.getCallingConv(),

218 F.isVarArg());

219}

220

224 assert(!Val == VRegs.empty() && "Return value without a vreg");

225

227 unsigned Opcode = ST.getReturnOpcode();

229

230 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))

231 return false;

232

234 return true;

235}

236

237namespace {

238

239

240

244 : IncomingValueHandler(MIRBuilder, MRI) {}

245

250 "Unsupported size");

251

253

254

255

256 const bool IsImmutable = !Flags.isByVal();

257

258 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);

260

263 }

264

270

271

273 assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");

274

275 auto LoadVReg = buildLoad(LLT::scalar(32), Addr, MemTy, MPO);

276 MIRBuilder.buildTrunc(ValVReg, LoadVReg);

277 } else {

278

279 buildLoad(ValVReg, Addr, MemTy, MPO);

280 }

281 }

282

286

290 }

291

294 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");

295 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");

296

299

300 assert(ValSize <= 64 && "Unsupported value size");

301 assert(LocSize <= 64 && "Unsupported location size");

302

303 markPhysRegUsed(PhysReg);

304 if (ValSize == LocSize) {

305 MIRBuilder.buildCopy(ValVReg, PhysReg);

306 } else {

307 assert(ValSize < LocSize && "Extensions not supported");

308

309

310

311

313 MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);

314 }

315 }

316

319 std::function<void()> *Thunk) override {

320 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");

321

323 assert(VA.needsCustom() && "Value doesn't need custom handling");

324

325

326 if (VA.getValVT() != MVT::f64)

327 return 0;

328

330 assert(NextVA.needsCustom() && "Value doesn't need custom handling");

331 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");

332

334 "Values belong to different arguments");

335

337 assert(NextVA.isRegLoc() && "Value should be in reg");

338

341

342 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);

343 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);

344

346 if (!IsLittle)

347 std::swap(NewRegs[0], NewRegs[1]);

348

350

351 return 2;

352 }

353

354

355

356

357 virtual void markPhysRegUsed(unsigned PhysReg) = 0;

358};

359

363

364 void markPhysRegUsed(unsigned PhysReg) override {

367 }

368};

369

370}

371

376 auto &TLI = *getTLI();

377 auto Subtarget = TLI.getSubtarget();

378

379 if (Subtarget->isThumb1Only())

380 return false;

381

382

383 if (F.arg_empty())

384 return true;

385

386 if (F.isVarArg())

387 return false;

388

389 auto &MF = MIRBuilder.getMF();

392

393 for (auto &Arg : F.args()) {

395 return false;

396 if (Arg.hasPassPointeeByValueCopyAttr())

397 return false;

398 }

399

401 TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());

402

405

407 unsigned Idx = 0;

408 for (auto &Arg : F.args()) {

409 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType(), Idx);

410

413

415 }

416

419

421 MIRBuilder, F.getCallingConv(),

422 F.isVarArg()))

423 return false;

424

425

427 return true;

428}

429

430namespace {

431

432struct CallReturnHandler : public ARMIncomingValueHandler {

435 : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}

436

437 void markPhysRegUsed(unsigned PhysReg) override {

439 }

440

442};

443

444

446 bool isDirect) {

447 if (isDirect)

448 return STI.isThumb() ? ARM::tBL : ARM::BL;

449

450 if (STI.isThumb())

452

453 if (STI.hasV5TOps())

455

456 if (STI.hasV4TOps())

457 return ARM::BX_CALL;

458

459 return ARM::BMOVPCRX_CALL;

460}

461}

462

465 const auto &TLI = *getTLI();

470

471 if (STI.genLongCalls())

472 return false;

473

475 return false;

476

477 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);

478

479

480

481 bool IsDirect = Info .Callee.isReg();

482 auto CallOpcode = getCallOpcode(MF, STI, IsDirect);

484

485 bool IsThumb = STI.isThumb();

486 if (IsThumb)

488

489 MIB.add(Info.Callee);

490 if (!IsDirect) {

491 auto CalleeReg = Info.Callee.getReg();

492 if (CalleeReg && !CalleeReg.isPhysical()) {

493 unsigned CalleeIdx = IsThumb ? 2 : 0;

496 *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));

497 }

498 }

499

500 MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));

501

503 for (auto Arg : Info.OrigArgs) {

505 return false;

506

507 if (Arg.Flags[0].isByVal())

508 return false;

509

511 }

512

513 auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, Info.IsVarArg);

515 ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB);

517 MIRBuilder, Info.CallConv, Info.IsVarArg))

518 return false;

519

520

522

523 if ( Info .OrigRet.Ty->isVoidTy()) {

525 return false;

526

527 ArgInfos.clear();

529 auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg);

531 CallReturnHandler RetHandler(MIRBuilder, MRI, MIB);

533 MIRBuilder, Info.CallConv,

534 Info.IsVarArg))

535 return false;

536 }

537

538

539

541

542 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)

546

547 return true;

548}

549

unsigned const MachineRegisterInfo * MRI

static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall, std::optional< CallLowering::PtrAuthInfo > &PAI, MachineRegisterInfo &MRI)

static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI, Type *T)

static cl::opt< bool > EnableGISelBigEndian("enable-arm-gisel-bigendian", cl::Hidden, cl::init(false), cl::desc("Enable Global-ISel Big Endian Lowering"))

This file describes how to lower LLVM calls to machine code calls.

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file contains the simple types necessary to represent the attributes associated with functions a...

Analysis containing CSE Info

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Implement a low-level type suitable for MachineInstr level instruction selection.

This file declares the MachineIRBuilder class.

unsigned const TargetRegisterInfo * TRI

static constexpr Register SPReg

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallVector class.

ARMCallLowering(const ARMTargetLowering &TLI)

bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override

This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...

bool enableBigEndian() const override

For targets which want to use big-endian can enable it with enableBigEndian() hook.

bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override

This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...

bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override

This hook must be implemented to lower the given call instruction, including argument and return valu...

const RegisterBankInfo * getRegBankInfo() const override

const ARMBaseInstrInfo * getInstrInfo() const override

bool isThumb1Only() const

const ARMBaseRegisterInfo * getRegisterInfo() const override

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool empty() const

empty - Check if the array is empty.

CCValAssign - Represent assignment of one arg/retval to a location.

LocInfo getLocInfo() const

unsigned getValNo() const

void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const

Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.

bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs={}) const

Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...

void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const

A parsed version of the target data layout string in and methods for querying it.

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)

Get a low-level pointer in the given address space.

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Helper class to build MachineInstr.

MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)

Insert an existing instruction at the insertion point.

void setInstr(MachineInstr &MI)

Set the insertion point to before MI.

MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...

MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert Res = G_LOAD Addr, MMO.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)

Build and insert Res = G_FRAME_INDEX Idx.

MachineFunction & getMF()

Getter for the function we currently build.

MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_TRUNC Op.

const MachineBasicBlock & getMBB() const

Getter for the basic block we currently build.

void setMBB(MachineBasicBlock &MBB)

Set the insertion point to the end of MBB.

MachineRegisterInfo * getMRI()

Getter for MRI.

MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)

Build but don't insert = Opcode .

MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)

Build and insert Res = COPY Op.

Get the register for the operand index.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

void addLiveIn(MCRegister Reg, Register vreg=Register())

addLiveIn - Add the specified register as a live-in.

Wrapper class representing virtual and physical registers.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

Return the EVT corresponding to this LLVM type.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

@ Implicit

Not emitted register (e.g. carry, or temporary result).

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)

Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...

static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)

Get the operands corresponding to the given Pred value.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

unsigned gettBLXrOpcode(const MachineFunction &MF)

unsigned getBLXOpcode(const MachineFunction &MF)

Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Helper struct shared between Function Specialization and SCCP Solver.

SmallVector< Register, 4 > Regs

SmallVector< ISD::ArgFlagsTy, 4 > Flags

Base class for ValueHandlers used for arguments coming into the current function, or for return value...

Base class for ValueHandlers used for arguments passed to a function call, or for return values.

uint64_t StackSize

The size of the currently allocated portion of the stack.

MachineIRBuilder & MIRBuilder

MachineRegisterInfo & MRI

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

bool isFloatingPoint() const

Return true if this is a FP or a vector FP type.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

bool isVector() const

Return true if this is a vector value type.

bool isInteger() const

Return true if this is an integer or a vector integer type.

This class contains a discriminated union of information about pointers in memory operands,...

unsigned getAddrSpace() const

Return the LLVM IR address space number that this pointer points into.

static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)

Stack pointer relative access.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.