AVRDisassembler.cpp Source File (original) (raw)

26using namespace llvm;

28#define DEBUG_TYPE "avr-disassembler"

32namespace {

36public:

39 virtual ~AVRDisassembler() = default;

44};

45}

50 return new AVRDisassembler(STI, Ctx);

51}

57}

60 AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6,

61 AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,

62 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,

63 AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,

64 AVR::R28, AVR::R29, AVR::R30, AVR::R31,

65};

70 if (RegNo > 31)

76}

81 if (RegNo > 15)

87}

101

104

107

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128

132

136

137#include "AVRGenDisassemblerTables.inc"

138

141 unsigned addr = 0;

142 addr |= fieldFromInstruction(Insn, 0, 4);

143 addr |= fieldFromInstruction(Insn, 9, 2) << 4;

144 unsigned reg = fieldFromInstruction(Insn, 4, 5);

150}

151

154 unsigned addr = 0;

155 addr |= fieldFromInstruction(Insn, 0, 4);

156 addr |= fieldFromInstruction(Insn, 9, 2) << 4;

157 unsigned reg = fieldFromInstruction(Insn, 4, 5);

163}

164

167 unsigned addr = fieldFromInstruction(Insn, 3, 5);

168 unsigned b = fieldFromInstruction(Insn, 0, 3);

172}

173

177

178

181}

182

185 unsigned d = fieldFromInstruction(Insn, 4, 5);

190}

191

198}

199

203 unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;

204 unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;

212}

213

217 unsigned r = fieldFromInstruction(Insn, 4, 4) * 2;

218 unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;

226}

227

230 unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24;

231 unsigned k = 0;

232 k |= fieldFromInstruction(Insn, 0, 4);

233 k |= fieldFromInstruction(Insn, 6, 2) << 4;

242}

243

247 unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;

248 unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;

256}

257

260

261

262

263 if (Insn > 127)

265

266

269

271

273}

274

277

278 switch (Insn & 0xf000) {

279 case 0xc000:

281 break;

282 case 0xd000:

284 break;

285 default:

287 }

288

289 int16_t Offset = ((int16_t)((Insn & 0xfff) << 4)) >> 3;

292}

293

297

299 {0x000, AVR::BRLOk}, {0x400, AVR::BRSHk}, {0x001, AVR::BREQk},

300 {0x401, AVR::BRNEk}, {0x002, AVR::BRMIk}, {0x402, AVR::BRPLk},

301 {0x004, AVR::BRLTk}, {0x404, AVR::BRGEk}};

302

303

304 int16_t Offset = ((int16_t)((Insn & 0x3f8) << 6)) >> 8;

305

306

307 auto NotAlias = [&Insn](const std::pair<unsigned, unsigned> &I) {

308 return (Insn & 0x407) != I.first;

309 };

312

313

314 if (It != brInsts.end()) {

315

318 } else {

319

320 Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk);

323 }

324

326}

327

331

333

334

335 if ((Insn & 0xf000) == 0x8000) {

336 unsigned RegBase = (Insn & 0x8) ? AVR::R29R28 : AVR::R31R30;

337 unsigned Offset = Insn & 7;

338 if ((Insn & 0x200) == 0) {

343 } else {

348 }

350 }

351

352

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369

370 if ((Insn & 0xfc00) != 0x9000 || (Insn & 0xf) == 0)

372

373

374 unsigned RegBase;

375 switch (Insn & 0xc) {

376 case 0xc:

377 RegBase = AVR::R27R26;

378 break;

379 case 0x8:

380 RegBase = AVR::R29R28;

381 break;

382 case 0x0:

383 RegBase = AVR::R31R30;

384 break;

385 default:

387 }

388

389

390 switch (Insn & 0x203) {

391 case 0x200:

396 case 0x201:

398 break;

399 case 0x202:

401 break;

402 case 0:

407 case 1:

409 break;

410 case 2:

412 break;

413 default:

415 }

416

417

418 if ((Insn & 0x200) == 0) {

422 } else {

426

428 }

429

431}

432

435 if (Bytes.size() < 2) {

438 }

439

441 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);

442

444}

445

448

449 if (Bytes.size() < 4) {

452 }

453

456 (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);

457

459}

460

462

463 switch (Size) {

464 case 2:

465 return DecoderTable16;

466 case 4:

467 return DecoderTable32;

468 default:

470 }

471}

472

478

480

481

482 {

484

487

488

489 if (STI.hasFeature(AVR::FeatureTinyEncoding)) {

490 Result = decodeInstruction(DecoderTableAVRTiny16, Instr, Insn, Address,

491 this, STI);

494 }

495

496

498 this, STI);

501

502

503

507 }

508

509

510 {

512

515

517 this, STI);

518

521 }

522

524 }

525}

526

SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn

static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

MCDisassembler::DecodeStatus DecodeStatus

static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static const uint16_t GPRDecoderTable[]

static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static MCDisassembler * createAVRDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler()

static const uint8_t * getDecoderTable(uint64_t Size)

static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

#define LLVM_EXTERNAL_VISIBILITY

This file defines the DenseMap class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

DecodeStatus

Ternary decode status.

virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0

Returns the disassembly of a single instruction.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Wrapper class representing virtual and physical registers.

Target - Wrapper for Target specific information.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheAVRTarget()

auto partition_point(R &&Range, Predicate P)

Binary search for the first iterator in a range where a predicate is false.

auto partition(R &&Range, UnaryPredicate P)

Provide wrappers to std::partition which take ranges instead of having to pass begin/end explicitly.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.