CSKYAsmParser.cpp Source File (original) (raw)

38using namespace llvm;

40#define DEBUG_TYPE "csky-asm-parser"

43#define GEN_COMPRESS_INSTR

44#include "CSKYGenCompressInstEmitter.inc"

47 "Number of C-SKY Compressed instructions emitted");

52 cl::desc("Enable C-SKY asm compressed instruction"));

54namespace {

55struct CSKYOperand;

62 unsigned Kind) override;

66 const Twine &Msg);

68 SMLoc getLoc() const { return getParser().getTok().getLoc(); }

70 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,

72 uint64_t &ErrorInfo,

73 bool MatchingInlineAsm) override;

75 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;

77 bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,

80 ParseStatus parseDirective(AsmToken DirectiveID) override;

84 void emitToStreamer(MCStreamer &S, const MCInst &Inst);

86 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,

87 SMLoc &EndLoc) override;

89 bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,

90 MCStreamer &Out);

91 bool processLRW(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);

92 bool processJSRI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);

93 bool processJMPI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);

95 CSKYTargetStreamer &getTargetStreamer() {

96 assert(getParser().getStreamer().getTargetStreamer() &&

97 "do not have a target streamer");

98 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();

99 return static_cast<CSKYTargetStreamer &>(TS);

100 }

101

102

103#define GET_ASSEMBLER_HEADER

104#include "CSKYGenAsmMatcher.inc"

105

115

117

118 bool parseDirectiveAttribute();

119

120public:

121 enum CSKYMatchResultTy {

122 Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,

123 Match_RequiresSameSrcAndDst,

124 Match_InvalidRegOutOfRange,

125#define GET_OPERAND_DIAGNOSTIC_TYPES

126#include "CSKYGenAsmMatcher.inc"

127#undef GET_OPERAND_DIAGNOSTIC_TYPES

128 };

129

130 CSKYAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,

131 const MCInstrInfo &MII, const MCTargetOptions &Options)

132 : MCTargetAsmParser(Options, STI, MII) {

133

135

136

137 MRI = getContext().getRegisterInfo();

138

139 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));

140 getTargetStreamer().emitTargetAttributes(STI);

141 }

142};

143

144

146

147 enum KindTy {

148 Token,

149 Register,

150 Immediate,

151 RegisterSeq,

152 CPOP,

153 RegisterList

154 } Kind;

155

156 struct RegOp {

157 MCRegister RegNum;

158 };

159

160 struct ImmOp {

161 const MCExpr *Val;

162 };

163

164 struct ConstpoolOp {

165 const MCExpr *Val;

166 };

167

168 struct RegSeqOp {

169 MCRegister RegNumFrom;

170 MCRegister RegNumTo;

171 };

172

173 struct RegListOp {

174 MCRegister List1From;

175 MCRegister List1To;

176 MCRegister List2From;

177 MCRegister List2To;

178 MCRegister List3From;

179 MCRegister List3To;

180 MCRegister List4From;

181 MCRegister List4To;

182 };

183

184 SMLoc StartLoc, EndLoc;

185 union {

186 StringRef Tok;

187 RegOp Reg;

188 ImmOp Imm;

189 ConstpoolOp CPool;

190 RegSeqOp RegSeq;

191 RegListOp RegList;

192 };

193

194 CSKYOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}

195

196public:

197 CSKYOperand(const CSKYOperand &o) : MCParsedAsmOperand() {

198 Kind = o.Kind;

199 StartLoc = o.StartLoc;

200 EndLoc = o.EndLoc;

201 switch (Kind) {

202 case Register:

204 break;

205 case RegisterSeq:

206 RegSeq = o.RegSeq;

207 break;

208 case CPOP:

209 CPool = o.CPool;

210 break;

211 case Immediate:

213 break;

214 case Token:

215 Tok = o.Tok;

216 break;

217 case RegisterList:

218 RegList = o.RegList;

219 break;

220 }

221 }

222

223 bool isToken() const override { return Kind == Token; }

224 bool isReg() const override { return Kind == Register; }

225 bool isImm() const override { return Kind == Immediate; }

226 bool isRegisterSeq() const { return Kind == RegisterSeq; }

227 bool isRegisterList() const { return Kind == RegisterList; }

228 bool isConstPoolOp() const { return Kind == CPOP; }

229

230 bool isMem() const override { return false; }

231

232 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm) {

234 Imm = CE->getValue();

235 return true;

236 }

237

238 return false;

239 }

240

241 template <unsigned num, unsigned shift = 0> bool isUImm() const {

242 if (!isImm())

243 return false;

244

245 int64_t Imm;

246 bool IsConstantImm = evaluateConstantImm(getImm(), Imm);

248 }

249

250 template bool isOImm() const {

251 if (!isImm())

252 return false;

253

254 int64_t Imm;

255 bool IsConstantImm = evaluateConstantImm(getImm(), Imm);

256 return IsConstantImm && isUInt(Imm - 1);

257 }

258

259 template <unsigned num, unsigned shift = 0> bool isSImm() const {

260 if (!isImm())

261 return false;

262

263 int64_t Imm;

264 bool IsConstantImm = evaluateConstantImm(getImm(), Imm);

266 }

267

268 bool isUImm1() const { return isUImm<1>(); }

269 bool isUImm2() const { return isUImm<2>(); }

270 bool isUImm3() const { return isUImm<3>(); }

271 bool isUImm4() const { return isUImm<4>(); }

272 bool isUImm5() const { return isUImm<5>(); }

273 bool isUImm6() const { return isUImm<6>(); }

274 bool isUImm7() const { return isUImm<7>(); }

275 bool isUImm8() const { return isUImm<8>(); }

276 bool isUImm12() const { return isUImm<12>(); }

277 bool isUImm16() const { return isUImm<16>(); }

278 bool isUImm20() const { return isUImm<20>(); }

279 bool isUImm24() const { return isUImm<24>(); }

280

281 bool isOImm3() const { return isOImm<3>(); }

282 bool isOImm4() const { return isOImm<4>(); }

283 bool isOImm5() const { return isOImm<5>(); }

284 bool isOImm6() const { return isOImm<6>(); }

285 bool isOImm8() const { return isOImm<8>(); }

286 bool isOImm12() const { return isOImm<12>(); }

287 bool isOImm16() const { return isOImm<16>(); }

288

289 bool isSImm8() const { return isSImm<8>(); }

290

291 bool isUImm5Shift1() { return isUImm<5, 1>(); }

292 bool isUImm5Shift2() { return isUImm<5, 2>(); }

293 bool isUImm7Shift1() { return isUImm<7, 1>(); }

294 bool isUImm7Shift2() { return isUImm<7, 2>(); }

295 bool isUImm7Shift3() { return isUImm<7, 3>(); }

296 bool isUImm8Shift2() { return isUImm<8, 2>(); }

297 bool isUImm8Shift3() { return isUImm<8, 3>(); }

298 bool isUImm8Shift8() { return isUImm<8, 8>(); }

299 bool isUImm8Shift16() { return isUImm<8, 16>(); }

300 bool isUImm8Shift24() { return isUImm<8, 24>(); }

301 bool isUImm12Shift1() { return isUImm<12, 1>(); }

302 bool isUImm12Shift2() { return isUImm<12, 2>(); }

303 bool isUImm16Shift8() { return isUImm<16, 8>(); }

304 bool isUImm16Shift16() { return isUImm<16, 16>(); }

305 bool isUImm24Shift8() { return isUImm<24, 8>(); }

306

307 bool isSImm16Shift1() { return isSImm<16, 1>(); }

308

309 bool isCSKYSymbol() const { return isImm(); }

310

311 bool isConstpool() const { return isConstPoolOp(); }

312 bool isDataSymbol() const { return isConstPoolOp(); }

313

314 bool isPSRFlag() const {

315 int64_t Imm;

316

317 if (!isImm() || !evaluateConstantImm(getImm(), Imm))

318 return false;

319

321 }

322

323 template <unsigned MIN, unsigned MAX> bool isRegSeqTemplate() const {

324 if (!isRegisterSeq())

325 return false;

326

327 std::pair<unsigned, unsigned> regSeq = getRegSeq();

328

329 return MIN <= regSeq.first && regSeq.first <= regSeq.second &&

330 regSeq.second <= MAX;

331 }

332

333 bool isRegSeq() const { return isRegSeqTemplate<CSKY::R0, CSKY::R31>(); }

334

335 bool isRegSeqV1() const {

336 return isRegSeqTemplate<CSKY::F0_32, CSKY::F15_32>();

337 }

338

339 bool isRegSeqV2() const {

340 return isRegSeqTemplate<CSKY::F0_32, CSKY::F31_32>();

341 }

342

343 static bool isLegalRegList(unsigned from, unsigned to) {

344 if (from == 0 && to == 0)

345 return true;

346

347 if (from == to) {

348 if (from != CSKY::R4 && from != CSKY::R15 && from != CSKY::R16 &&

349 from != CSKY::R28)

350 return false;

351

352 return true;

353 } else {

354 if (from != CSKY::R4 && from != CSKY::R16)

355 return false;

356

357 if (from == CSKY::R4 && to > CSKY::R4 && to < CSKY::R12)

358 return true;

359 else if (from == CSKY::R16 && to > CSKY::R16 && to < CSKY::R18)

360 return true;

361 else

362 return false;

363 }

364 }

365

366 bool isRegList() const {

367 if (!isRegisterList())

368 return false;

369

370 auto regList = getRegList();

371

372 if (!isLegalRegList(regList.List1From, regList.List1To))

373 return false;

374 if (!isLegalRegList(regList.List2From, regList.List2To))

375 return false;

376 if (!isLegalRegList(regList.List3From, regList.List3To))

377 return false;

378 if (!isLegalRegList(regList.List4From, regList.List4To))

379 return false;

380

381 return true;

382 }

383

384 bool isExtImm6() {

385 if (!isImm())

386 return false;

387

388 int64_t Imm;

389 bool IsConstantImm = evaluateConstantImm(getImm(), Imm);

390 if (!IsConstantImm)

391 return false;

392

393 int uimm4 = Imm & 0xf;

394

396 }

397

398

399 SMLoc getStartLoc() const override { return StartLoc; }

400

401 SMLoc getEndLoc() const override { return EndLoc; }

402

403 MCRegister getReg() const override {

404 assert(Kind == Register && "Invalid type access!");

405 return Reg.RegNum;

406 }

407

408 std::pair<MCRegister, MCRegister> getRegSeq() const {

409 assert(Kind == RegisterSeq && "Invalid type access!");

410 return {RegSeq.RegNumFrom, RegSeq.RegNumTo};

411 }

412

413 RegListOp getRegList() const {

414 assert(Kind == RegisterList && "Invalid type access!");

415 return RegList;

416 }

417

418 const MCExpr *getImm() const {

419 assert(Kind == Immediate && "Invalid type access!");

420 return Imm.Val;

421 }

422

423 const MCExpr *getConstpoolOp() const {

424 assert(Kind == CPOP && "Invalid type access!");

425 return CPool.Val;

426 }

427

429 assert(Kind == Token && "Invalid type access!");

430 return Tok;

431 }

432

433 void print(raw_ostream &OS, const MCAsmInfo &MAI) const override {

437 else

438 return "noreg";

439 };

440

441 switch (Kind) {

442 case CPOP:

443 MAI.printExpr(OS, *getConstpoolOp());

444 break;

445 case Immediate:

447 break;

448 case KindTy::Register:

450 break;

451 case RegisterSeq:

452 OS << "<register-seq ";

453 OS << RegName(getRegSeq().first) << "-" << RegName(getRegSeq().second)

454 << ">";

455 break;

456 case RegisterList:

457 OS << "<register-list ";

458 OS << RegName(getRegList().List1From) << "-"

459 << RegName(getRegList().List1To) << ",";

460 OS << RegName(getRegList().List2From) << "-"

461 << RegName(getRegList().List2To) << ",";

462 OS << RegName(getRegList().List3From) << "-"

463 << RegName(getRegList().List3To) << ",";

464 OS << RegName(getRegList().List4From) << "-"

465 << RegName(getRegList().List4To);

466 break;

467 case Token:

468 OS << "'" << getToken() << "'";

469 break;

470 }

471 }

472

473 static std::unique_ptr createToken(StringRef Str, SMLoc S) {

474 auto Op = std::make_unique(Token);

475 Op->Tok = Str;

476 Op->StartLoc = S;

477 Op->EndLoc = S;

478 return Op;

479 }

480

481 static std::unique_ptr createReg(MCRegister RegNo, SMLoc S,

482 SMLoc E) {

483 auto Op = std::make_unique(Register);

484 Op->Reg.RegNum = RegNo;

485 Op->StartLoc = S;

486 Op->EndLoc = E;

487 return Op;

488 }

489

490 static std::unique_ptr

491 createRegSeq(MCRegister RegNoFrom, MCRegister RegNoTo, SMLoc S) {

492 auto Op = std::make_unique(RegisterSeq);

493 Op->RegSeq.RegNumFrom = RegNoFrom;

494 Op->RegSeq.RegNumTo = RegNoTo;

495 Op->StartLoc = S;

496 Op->EndLoc = S;

497 return Op;

498 }

499

500 static std::unique_ptr

502 auto Op = std::make_unique(RegisterList);

503 Op->RegList.List1From = 0;

504 Op->RegList.List1To = 0;

505 Op->RegList.List2From = 0;

506 Op->RegList.List2To = 0;

507 Op->RegList.List3From = 0;

508 Op->RegList.List3To = 0;

509 Op->RegList.List4From = 0;

510 Op->RegList.List4To = 0;

511

512 for (unsigned i = 0; i < reglist.size(); i += 2) {

513 if (Op->RegList.List1From == 0) {

514 Op->RegList.List1From = reglist[i];

515 Op->RegList.List1To = reglist[i + 1];

516 } else if (Op->RegList.List2From == 0) {

517 Op->RegList.List2From = reglist[i];

518 Op->RegList.List2To = reglist[i + 1];

519 } else if (Op->RegList.List3From == 0) {

520 Op->RegList.List3From = reglist[i];

521 Op->RegList.List3To = reglist[i + 1];

522 } else if (Op->RegList.List4From == 0) {

523 Op->RegList.List4From = reglist[i];

524 Op->RegList.List4To = reglist[i + 1];

525 } else {

527 }

528 }

529

530 Op->StartLoc = S;

531 Op->EndLoc = S;

532 return Op;

533 }

534

535 static std::unique_ptr createImm(const MCExpr *Val, SMLoc S,

536 SMLoc E) {

537 auto Op = std::make_unique(Immediate);

538 Op->Imm.Val = Val;

539 Op->StartLoc = S;

540 Op->EndLoc = E;

541 return Op;

542 }

543

544 static std::unique_ptr createConstpoolOp(const MCExpr *Val,

545 SMLoc S, SMLoc E) {

546 auto Op = std::make_unique(CPOP);

547 Op->CPool.Val = Val;

548 Op->StartLoc = S;

549 Op->EndLoc = E;

550 return Op;

551 }

552

553 void addExpr(MCInst &Inst, const MCExpr *Expr) const {

554 assert(Expr && "Expr shouldn't be null!");

557 else

559 }

560

561

562 void addRegOperands(MCInst &Inst, unsigned N) const {

563 assert(N == 1 && "Invalid number of operands!");

565 }

566

567 void addImmOperands(MCInst &Inst, unsigned N) const {

568 assert(N == 1 && "Invalid number of operands!");

569 addExpr(Inst, getImm());

570 }

571

572 void addConstpoolOperands(MCInst &Inst, unsigned N) const {

573 assert(N == 1 && "Invalid number of operands!");

575 }

576

577 void addRegSeqOperands(MCInst &Inst, unsigned N) const {

578 assert(N == 2 && "Invalid number of operands!");

579 auto regSeq = getRegSeq();

580

583 }

584

585 static unsigned getListValue(unsigned ListFrom, unsigned ListTo) {

586 if (ListFrom == ListTo && ListFrom == CSKY::R15)

587 return (1 << 4);

588 else if (ListFrom == ListTo && ListFrom == CSKY::R28)

589 return (1 << 8);

590 else if (ListFrom == CSKY::R4)

591 return ListTo - ListFrom + 1;

592 else if (ListFrom == CSKY::R16)

593 return ((ListTo - ListFrom + 1) << 5);

594 else

595 return 0;

596 }

597

598 void addRegListOperands(MCInst &Inst, unsigned N) const {

599 assert(N == 1 && "Invalid number of operands!");

600 auto regList = getRegList();

601

602 unsigned V = 0;

603

604 unsigned T = getListValue(regList.List1From, regList.List1To);

605 if (T != 0)

606 V = V | T;

607

608 T = getListValue(regList.List2From, regList.List2To);

609 if (T != 0)

610 V = V | T;

611

612 T = getListValue(regList.List3From, regList.List3To);

613 if (T != 0)

614 V = V | T;

615

616 T = getListValue(regList.List4From, regList.List4To);

617 if (T != 0)

618 V = V | T;

619

621 }

622

623 bool isValidForTie(const CSKYOperand &Other) const {

624 if (Kind != Other.Kind)

625 return false;

626

627 switch (Kind) {

628 default:

630 return false;

631 case Register:

632 return Reg.RegNum == Other.Reg.RegNum;

633 }

634 }

635};

636}

637

638#define GET_REGISTER_MATCHER

639#define GET_SUBTARGET_FEATURE_NAME

640#define GET_MATCHER_IMPLEMENTATION

641#define GET_MNEMONIC_SPELL_CHECKER

642#include "CSKYGenAsmMatcher.inc"

643

645 assert(Reg >= CSKY::F0_32 && Reg <= CSKY::F31_32 && "Invalid register");

646 return Reg - CSKY::F0_32 + CSKY::F0_64;

647}

648

650 unsigned VariantID = 0);

651

652bool CSKYAsmParser::generateImmOutOfRangeError(

654 const Twine &Msg = "immediate must be an integer in the range") {

655 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

657}

658

659bool CSKYAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,

661 MCStreamer &Out,

662 uint64_t &ErrorInfo,

663 bool MatchingInlineAsm) {

664 MCInst Inst;

665 FeatureBitset MissingFeatures;

666

667 auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,

668 MatchingInlineAsm);

669 switch (Result) {

670 default:

671 break;

672 case Match_Success:

673 return processInstruction(Inst, IDLoc, Operands, Out);

674 case Match_MissingFeature: {

675 assert(MissingFeatures.any() && "Unknown missing features!");

676 ListSeparator LS;

677 std::string Msg = "instruction requires the following: ";

678 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {

679 if (MissingFeatures[i]) {

680 Msg += LS;

682 }

683 }

684 return Error(IDLoc, Msg);

685 }

686 case Match_MnemonicFail: {

687 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());

688 std::string Suggestion =

690 return Error(IDLoc, "unrecognized instruction mnemonic" + Suggestion);

691 }

692 case Match_InvalidTiedOperand:

693 case Match_InvalidOperand: {

694 SMLoc ErrorLoc = IDLoc;

695 if (ErrorInfo != ~0U) {

696 if (ErrorInfo >= Operands.size())

697 return Error(ErrorLoc, "too few operands for instruction");

698

699 ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

700 if (ErrorLoc == SMLoc())

701 ErrorLoc = IDLoc;

702 }

703 return Error(ErrorLoc, "invalid operand for instruction");

704 }

705 }

706

707

708

709

710 if (Result > FIRST_TARGET_MATCH_RESULT_TY) {

711 SMLoc ErrorLoc = IDLoc;

712 if (ErrorInfo != ~0U && ErrorInfo >= Operands.size())

713 return Error(ErrorLoc, "too few operands for instruction");

714 }

715

716 switch (Result) {

717 default:

718 break;

719 case Match_InvalidSImm8:

720 return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 7),

721 (1 << 7) - 1);

722 case Match_InvalidOImm3:

723 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 3));

724 case Match_InvalidOImm4:

725 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 4));

726 case Match_InvalidOImm5:

727 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5));

728 case Match_InvalidOImm6:

729 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6));

730 case Match_InvalidOImm8:

731 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 8));

732 case Match_InvalidOImm12:

733 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 12));

734 case Match_InvalidOImm16:

735 return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 16));

736 case Match_InvalidUImm1:

737 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 1) - 1);

738 case Match_InvalidUImm2:

739 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);

740 case Match_InvalidUImm3:

741 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);

742 case Match_InvalidUImm4:

743 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);

744 case Match_InvalidUImm5:

745 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);

746 case Match_InvalidUImm6:

747 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);

748 case Match_InvalidUImm7:

749 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1);

750 case Match_InvalidUImm8:

751 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 1);

752 case Match_InvalidUImm12:

753 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 12) - 1);

754 case Match_InvalidUImm16:

755 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 16) - 1);

756 case Match_InvalidUImm5Shift1:

757 return generateImmOutOfRangeError(

758 Operands, ErrorInfo, 0, (1 << 5) - 2,

759 "immediate must be a multiple of 2 bytes in the range");

760 case Match_InvalidUImm12Shift1:

761 return generateImmOutOfRangeError(

762 Operands, ErrorInfo, 0, (1 << 12) - 2,

763 "immediate must be a multiple of 2 bytes in the range");

764 case Match_InvalidUImm5Shift2:

765 return generateImmOutOfRangeError(

766 Operands, ErrorInfo, 0, (1 << 5) - 4,

767 "immediate must be a multiple of 4 bytes in the range");

768 case Match_InvalidUImm7Shift1:

769 return generateImmOutOfRangeError(

770 Operands, ErrorInfo, 0, (1 << 7) - 2,

771 "immediate must be a multiple of 2 bytes in the range");

772 case Match_InvalidUImm7Shift2:

773 return generateImmOutOfRangeError(

774 Operands, ErrorInfo, 0, (1 << 7) - 4,

775 "immediate must be a multiple of 4 bytes in the range");

776 case Match_InvalidUImm8Shift2:

777 return generateImmOutOfRangeError(

778 Operands, ErrorInfo, 0, (1 << 8) - 4,

779 "immediate must be a multiple of 4 bytes in the range");

780 case Match_InvalidUImm8Shift3:

781 return generateImmOutOfRangeError(

782 Operands, ErrorInfo, 0, (1 << 8) - 8,

783 "immediate must be a multiple of 8 bytes in the range");

784 case Match_InvalidUImm8Shift8:

785 return generateImmOutOfRangeError(

786 Operands, ErrorInfo, 0, (1 << 8) - 256,

787 "immediate must be a multiple of 256 bytes in the range");

788 case Match_InvalidUImm12Shift2:

789 return generateImmOutOfRangeError(

790 Operands, ErrorInfo, 0, (1 << 12) - 4,

791 "immediate must be a multiple of 4 bytes in the range");

792 case Match_InvalidCSKYSymbol: {

793 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

794 return Error(ErrorLoc, "operand must be a symbol name");

795 }

796 case Match_InvalidConstpool: {

797 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

798 return Error(ErrorLoc, "operand must be a constpool symbol name");

799 }

800 case Match_InvalidPSRFlag: {

801 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

802 return Error(ErrorLoc, "psrset operand is not valid");

803 }

804 case Match_InvalidRegSeq: {

805 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

806 return Error(ErrorLoc, "Register sequence is not valid");

807 }

808 case Match_InvalidRegOutOfRange: {

809 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

810 return Error(ErrorLoc, "register is out of range");

811 }

812 case Match_RequiresSameSrcAndDst: {

813 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

814 return Error(ErrorLoc, "src and dst operand must be same");

815 }

816 case Match_InvalidRegList: {

817 SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();

818 return Error(ErrorLoc, "invalid register list");

819 }

820 }

823}

824

825bool CSKYAsmParser::processLRW(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) {

827

828 unsigned Opcode;

829 MCOperand Op;

830 if (Inst.getOpcode() == CSKY::PseudoLRW16)

831 Opcode = CSKY::LRW16;

832 else

833 Opcode = CSKY::LRW32;

834

838 Opcode = CSKY::MOVI16;

839 } else if (getSTI().hasFeature(CSKY::HasE2) &&

841 Opcode = CSKY::MOVI32;

842 } else {

843 auto *Expr = getTargetStreamer().addConstantPoolEntry(

846 Inst.erase(std::prev(Inst.end()));

848 }

849 } else {

850 const MCExpr *AdjustExpr = nullptr;

851 if (const auto *CSKYExpr =

859 }

860 }

861 auto *Expr = getTargetStreamer().addConstantPoolEntry(

863 Inst.erase(std::prev(Inst.end()));

865 }

866

868

870 return false;

871}

872

873bool CSKYAsmParser::processJSRI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) {

875

877 const MCExpr *Expr = getTargetStreamer().addConstantPoolEntry(

881 Inst.erase(std::prev(Inst.end()));

883 } else {

884 const MCExpr *Expr = getTargetStreamer().addConstantPoolEntry(

888 }

889

891 return false;

892}

893

894bool CSKYAsmParser::processJMPI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) {

896

898 const MCExpr *Expr = getTargetStreamer().addConstantPoolEntry(

902 Inst.erase(std::prev(Inst.end()));

904 } else {

905 const MCExpr *Expr = getTargetStreamer().addConstantPoolEntry(

909 }

910

912 return false;

913}

914

915bool CSKYAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,

917 MCStreamer &Out) {

918

920 default:

921 break;

922 case CSKY::LDQ32:

923 case CSKY::STQ32:

926 return Error(IDLoc, "Register sequence is not valid. 'r4-r7' expected");

927 }

928 Inst.setOpcode(Inst.getOpcode() == CSKY::LDQ32 ? CSKY::LDM32 : CSKY::STM32);

929 break;

930 case CSKY::SEXT32:

931 case CSKY::ZEXT32:

933 return Error(IDLoc, "msb must be greater or equal to lsb");

934 break;

935 case CSKY::INS32:

937 return Error(IDLoc, "msb must be greater or equal to lsb");

938 break;

939 case CSKY::IDLY32:

941 return Error(IDLoc, "n must be in range [0,32]");

942 break;

943 case CSKY::ADDC32:

944 case CSKY::SUBC32:

945 case CSKY::ADDC16:

946 case CSKY::SUBC16:

948 Inst.erase(std::prev(Inst.end()));

951 break;

952 case CSKY::CMPNEI32:

953 case CSKY::CMPNEI16:

954 case CSKY::CMPNE32:

955 case CSKY::CMPNE16:

956 case CSKY::CMPHSI32:

957 case CSKY::CMPHSI16:

958 case CSKY::CMPHS32:

959 case CSKY::CMPHS16:

960 case CSKY::CMPLTI32:

961 case CSKY::CMPLTI16:

962 case CSKY::CMPLT32:

963 case CSKY::CMPLT16:

964 case CSKY::BTSTI32:

967 break;

968 case CSKY::MVCV32:

971 break;

972 case CSKY::PseudoLRW16:

973 case CSKY::PseudoLRW32:

974 return processLRW(Inst, IDLoc, Out);

975 case CSKY::PseudoJSRI32:

976 return processJSRI(Inst, IDLoc, Out);

977 case CSKY::PseudoJMPI32:

978 return processJMPI(Inst, IDLoc, Out);

979 case CSKY::JBSR32:

980 case CSKY::JBR16:

981 case CSKY::JBT16:

982 case CSKY::JBF16:

983 case CSKY::JBR32:

984 case CSKY::JBT32:

985 case CSKY::JBF32:

988

989 const MCExpr *Expr = getTargetStreamer().addConstantPoolEntry(

991

993 break;

994 }

995

996 emitToStreamer(Out, Inst);

997 return false;

998}

999

1000

1001

1002

1006

1007 if (Reg == CSKY::NoRegister)

1009

1010 return Reg == CSKY::NoRegister;

1011}

1012

1013bool CSKYAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,

1014 SMLoc &EndLoc) {

1015 const AsmToken &Tok = getParser().getTok();

1016 StartLoc = Tok.getLoc();

1018 StringRef Name = getLexer().getTok().getIdentifier();

1019

1021 getParser().Lex();

1022 return false;

1023 }

1024

1025 return true;

1026}

1027

1028ParseStatus CSKYAsmParser::parseRegister(OperandVector &Operands) {

1029 SMLoc S = getLoc();

1031

1032 switch (getLexer().getKind()) {

1033 default:

1036 StringRef Name = getLexer().getTok().getIdentifier();

1037 MCRegister Reg;

1038

1041

1042 getLexer().Lex();

1043 Operands.push_back(CSKYOperand::createReg(Reg, S, E));

1044

1046 }

1047 }

1048}

1049

1050ParseStatus CSKYAsmParser::parseBaseRegImm(OperandVector &Operands) {

1052

1053 Operands.push_back(CSKYOperand::createToken("(", getLoc()));

1054

1055 auto Tok = getParser().Lex();

1056

1057 if (!parseRegister(Operands).isSuccess()) {

1058 getLexer().UnLex(Tok);

1061 }

1062

1064 Operands.push_back(CSKYOperand::createToken(")", getLoc()));

1065 getParser().Lex();

1067 }

1068

1070 return Error(getLoc(), "expected ','");

1071

1072 getParser().Lex();

1073

1074 if (parseRegister(Operands).isSuccess()) {

1076 return Error(getLoc(), "expected '<<'");

1077

1078 Operands.push_back(CSKYOperand::createToken("<<", getLoc()));

1079

1080 getParser().Lex();

1081

1083 return Error(getLoc(), "expected imm");

1084

1086 return Error(getLoc(), "expected imm");

1087 }

1088

1090 return Error(getLoc(), "expected ')'");

1091

1092 Operands.push_back(CSKYOperand::createToken(")", getLoc()));

1093

1094 getParser().Lex();

1095

1097}

1098

1099ParseStatus CSKYAsmParser::parseImmediate(OperandVector &Operands) {

1100 switch (getLexer().getKind()) {

1101 default:

1108 break;

1109 }

1110

1111 const MCExpr *IdVal;

1112 SMLoc S = getLoc();

1113 if (getParser().parseExpression(IdVal))

1114 return Error(getLoc(), "unknown expression");

1115

1117 Operands.push_back(CSKYOperand::createImm(IdVal, S, E));

1119}

1120

1121

1122

1123

1124bool CSKYAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {

1125

1126

1127 ParseStatus Result =

1128 MatchOperandParserImpl(Operands, Mnemonic, true);

1129 if (Result.isSuccess())

1130 return false;

1131 if (Result.isFailure())

1132 return true;

1133

1134

1135 auto Res = parseRegister(Operands);

1136 if (Res.isSuccess())

1137 return false;

1138 if (Res.isFailure())

1139 return true;

1140

1141

1143 Res = parseBaseRegImm(Operands);

1144 if (Res.isSuccess())

1145 return false;

1146 if (Res.isFailure())

1147 return true;

1148 }

1149

1151 if (Res.isSuccess())

1152 return false;

1153 if (Res.isFailure())

1154 return true;

1155

1156

1157 Error(getLoc(), "unknown operand");

1158 return true;

1159}

1160

1161ParseStatus CSKYAsmParser::parseCSKYSymbol(OperandVector &Operands) {

1162 SMLoc S = getLoc();

1164 const MCExpr *Res;

1165

1168

1170 AsmToken Tok = getLexer().getTok();

1171

1172 if (getParser().parseIdentifier(Identifier))

1173 return Error(getLoc(), "unknown identifier");

1174

1176 if (Identifier.consume_back("@GOT"))

1178 else if (Identifier.consume_back("@GOTOFF"))

1180 else if (Identifier.consume_back("@PLT"))

1182 else if (Identifier.consume_back("@GOTPC"))

1184 else if (Identifier.consume_back("@TLSGD32"))

1186 else if (Identifier.consume_back("@GOTTPOFF"))

1188 else if (Identifier.consume_back("@TPOFF"))

1190 else if (Identifier.consume_back("@TLSLDM32"))

1192 else if (Identifier.consume_back("@TLSLDO32"))

1194

1196

1197 if (!Sym)

1198 Sym = getContext().getOrCreateSymbol(Identifier);

1199

1203 getLexer().UnLex(Tok);

1204 return Error(getLoc(), "unknown symbol");

1205 }

1206 Res = V;

1207 } else

1209

1211 switch (getLexer().getKind()) {

1212 default:

1215

1216 Operands.push_back(CSKYOperand::createImm(Res, S, E));

1220 break;

1223 break;

1224 }

1225

1226 getLexer().Lex();

1227

1228 const MCExpr *Expr;

1229 if (getParser().parseExpression(Expr))

1230 return Error(getLoc(), "unknown expression");

1232 Operands.push_back(CSKYOperand::createImm(Res, S, E));

1234}

1235

1236ParseStatus CSKYAsmParser::parseDataSymbol(OperandVector &Operands) {

1237 SMLoc S = getLoc();

1239 const MCExpr *Res;

1240

1244 const MCExpr *Expr;

1245 if (getParser().parseExpression(Expr))

1246 return Error(getLoc(), "unknown expression");

1247

1250

1251 Operands.push_back(CSKYOperand::createConstpoolOp(Expr, S, E));

1253 }

1254

1255 AsmToken Tok = getLexer().getTok();

1257

1258 if (getParser().parseIdentifier(Identifier))

1259 return Error(getLoc(), "unknown identifier " + Identifier);

1260

1262 if (Identifier.consume_back("@GOT"))

1264 else if (Identifier.consume_back("@PLT"))

1266

1268

1269 if (!Sym)

1270 Sym = getContext().getOrCreateSymbol(Identifier);

1271

1275 getLexer().UnLex(Tok);

1276 return Error(getLoc(), "unknown symbol");

1277 }

1278 Res = V;

1279 } else {

1281 }

1282

1284 switch (getLexer().getKind()) {

1285 default:

1286 return Error(getLoc(), "unknown symbol");

1288

1289 getLexer().Lex();

1290

1293

1294 Operands.push_back(CSKYOperand::createConstpoolOp(Res, S, E));

1298 break;

1301 break;

1302 }

1303

1304 getLexer().Lex();

1305

1306 const MCExpr *Expr;

1307 if (getParser().parseExpression(Expr))

1308 return Error(getLoc(), "unknown expression");

1311

1313 Operands.push_back(CSKYOperand::createConstpoolOp(Res, S, E));

1315}

1316

1317ParseStatus CSKYAsmParser::parseConstpoolSymbol(OperandVector &Operands) {

1318 SMLoc S = getLoc();

1320 const MCExpr *Res;

1321

1324

1326 const MCExpr *Expr;

1327 if (getParser().parseExpression(Expr))

1328 return Error(getLoc(), "unknown expression");

1331

1332 Operands.push_back(CSKYOperand::createConstpoolOp(Expr, S, E));

1334 }

1335

1336 AsmToken Tok = getLexer().getTok();

1338

1339 if (getParser().parseIdentifier(Identifier))

1340 return Error(getLoc(), "unknown identifier");

1341

1343

1344 if (!Sym)

1345 Sym = getContext().getOrCreateSymbol(Identifier);

1346

1350 getLexer().UnLex(Tok);

1351 return Error(getLoc(), "unknown symbol");

1352 }

1353 Res = V;

1354 } else {

1356 }

1357

1359 switch (getLexer().getKind()) {

1360 default:

1361 return Error(getLoc(), "unknown symbol");

1363

1364 getLexer().Lex();

1365

1366 Operands.push_back(CSKYOperand::createConstpoolOp(Res, S, E));

1370 break;

1373 break;

1374 }

1375

1376 getLexer().Lex();

1377

1378 const MCExpr *Expr;

1379 if (getParser().parseExpression(Expr))

1380 return Error(getLoc(), "unknown expression");

1383

1385 Operands.push_back(CSKYOperand::createConstpoolOp(Res, S, E));

1387}

1388

1389ParseStatus CSKYAsmParser::parsePSRFlag(OperandVector &Operands) {

1390 SMLoc S = getLoc();

1392

1393 unsigned Flag = 0;

1394

1397 if (getParser().parseIdentifier(Identifier))

1398 return Error(getLoc(), "unknown identifier " + Identifier);

1399

1400 if (Identifier == "sie")

1401 Flag = (1 << 4) | Flag;

1402 else if (Identifier == "ee")

1403 Flag = (1 << 3) | Flag;

1404 else if (Identifier == "ie")

1405 Flag = (1 << 2) | Flag;

1406 else if (Identifier == "fe")

1407 Flag = (1 << 1) | Flag;

1408 else if (Identifier == "af")

1409 Flag = (1 << 0) | Flag;

1410 else

1411 return Error(getLoc(), "expected " + Identifier);

1412

1414 break;

1415

1418 }

1419

1423}

1424

1425ParseStatus CSKYAsmParser::parseRegSeq(OperandVector &Operands) {

1426 SMLoc S = getLoc();

1427

1428 if (!parseRegister(Operands).isSuccess())

1430

1431 auto Ry = Operands.back()->getReg();

1433

1436 if (!parseRegister(Operands).isSuccess())

1437 return Error(getLoc(), "invalid register");

1438

1439 auto Rz = Operands.back()->getReg();

1441

1442 Operands.push_back(CSKYOperand::createRegSeq(Ry, Rz, S));

1444}

1445

1446ParseStatus CSKYAsmParser::parseRegList(OperandVector &Operands) {

1447 SMLoc S = getLoc();

1449 while (true) {

1450

1451 if (!parseRegister(Operands).isSuccess())

1452 return Error(getLoc(), "invalid register");

1453

1454 auto Ry = Operands.back()->getReg();

1456

1458 if (!parseRegister(Operands).isSuccess())

1459 return Error(getLoc(), "invalid register");

1460

1461 auto Rz = Operands.back()->getReg();

1463

1466

1468 break;

1476 break;

1477 } else {

1478 return Error(getLoc(), "invalid register list");

1479 }

1480 }

1481

1482 Operands.push_back(CSKYOperand::createRegList(reglist, S));

1484}

1485

1486bool CSKYAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,

1488

1489 Operands.push_back(CSKYOperand::createToken(Name, NameLoc));

1490

1491

1493 return false;

1494

1495

1496 if (parseOperand(Operands, Name))

1497 return true;

1498

1499

1501 if (parseOperand(Operands, Name))

1502 return true;

1503

1505 SMLoc Loc = getLexer().getLoc();

1506 getParser().eatToEndOfStatement();

1507 return Error(Loc, "unexpected token");

1508 }

1509

1510 getParser().Lex();

1511 return false;

1512}

1513

1514ParseStatus CSKYAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,

1515 SMLoc &EndLoc) {

1516 const AsmToken &Tok = getParser().getTok();

1517 StartLoc = Tok.getLoc();

1519

1520 StringRef Name = getLexer().getTok().getIdentifier();

1521

1524

1525 getParser().Lex();

1527}

1528

1529ParseStatus CSKYAsmParser::parseDirective(AsmToken DirectiveID) {

1530 StringRef IDVal = DirectiveID.getString();

1531

1532 if (IDVal == ".csky_attribute")

1533 return parseDirectiveAttribute();

1534

1536}

1537

1538

1539

1540bool CSKYAsmParser::parseDirectiveAttribute() {

1541 MCAsmParser &Parser = getParser();

1542 int64_t Tag;

1543 SMLoc TagLoc;

1547 std::optional Ret =

1549 if (!Ret)

1550 return Error(TagLoc, "attribute name not recognised: " + Name);

1551 Tag = *Ret;

1552 Parser.Lex();

1553 } else {

1554 const MCExpr *AttrExpr;

1555

1558 return true;

1559

1561 if (!CE)

1562 return Error(TagLoc, "expected numeric constant");

1563

1564 Tag = CE->getValue();

1565 }

1566

1568 return true;

1569

1570 StringRef StringValue;

1571 int64_t IntegerValue = 0;

1575

1576 SMLoc ValueExprLoc = Parser.getTok().getLoc();

1577 if (IsIntegerValue) {

1578 const MCExpr *ValueExpr;

1580 return true;

1581

1583 if (!CE)

1584 return Error(ValueExprLoc, "expected numeric constant");

1585 IntegerValue = CE->getValue();

1586 } else {

1588 return Error(Parser.getTok().getLoc(), "expected string constant");

1589

1591 Parser.Lex();

1592 }

1593

1595 return true;

1596

1597 if (IsIntegerValue)

1598 getTargetStreamer().emitAttribute(Tag, IntegerValue);

1600 getTargetStreamer().emitTextAttribute(Tag, StringValue);

1601 else {

1605 if (ID == CSKY::ArchKind::INVALID)

1607 ? "unknown arch name"

1608 : "unknown cpu name");

1609

1610 getTargetStreamer().emitTextAttribute(Tag, StringValue);

1611 }

1612

1613 return false;

1614}

1615

1616unsigned CSKYAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,

1617 unsigned Kind) {

1618 CSKYOperand &Op = static_cast<CSKYOperand &>(AsmOp);

1619

1620 if (.isReg())

1621 return Match_InvalidOperand;

1622

1623 MCRegister Reg = Op.getReg();

1624

1625 if (CSKYMCRegisterClasses[CSKY::FPR32RegClassID].contains(Reg)) {

1626

1627

1628 if (Kind == MCK_FPR64 || Kind == MCK_sFPR64) {

1630 if (Kind == MCK_sFPR64 &&

1631 (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F15_64))

1632 return Match_InvalidRegOutOfRange;

1633 if (Kind == MCK_FPR64 &&

1634 (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F31_64))

1635 return Match_InvalidRegOutOfRange;

1636 return Match_Success;

1637 }

1638 }

1639

1640 if (CSKYMCRegisterClasses[CSKY::GPRRegClassID].contains(Reg)) {

1641 if (Kind == MCK_GPRPair) {

1642 Op.Reg.RegNum = MRI->getEncodingValue(Reg) + CSKY::R0_R1;

1643 return Match_Success;

1644 }

1645 }

1646

1647 return Match_InvalidOperand;

1648}

1649

1650void CSKYAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {

1651 MCInst CInst;

1652 bool Res = false;

1654 Res = compressInst(CInst, Inst, getSTI());

1655 if (Res)

1656 ++CSKYNumInstrsCompressed;

1658}

1659

unsigned const MachineRegisterInfo * MRI

static MCRegister MatchRegisterName(StringRef Name)

static const char * getSubtargetFeatureName(uint64_t Val)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)

static MCRegister MatchRegisterAltName(StringRef Name)

Maps from the set of all alternative registernames to a register number.

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

Analysis containing CSE Info

static bool matchRegisterNameHelper(const MCSubtargetInfo &STI, MCRegister &Reg, StringRef Name)

Definition CSKYAsmParser.cpp:1003

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYAsmParser()

Definition CSKYAsmParser.cpp:1660

static MCRegister convertFPR32ToFPR64(MCRegister Reg)

Definition CSKYAsmParser.cpp:644

static std::string CSKYMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)

static cl::opt< bool > EnableCompressedInst("enable-csky-asm-compressed-inst", cl::Hidden, cl::init(false), cl::desc("Enable C-SKY asm compressed instruction"))

#define LLVM_EXTERNAL_VISIBILITY

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

static bool isReg(const MCInst &MI, unsigned OpNo)

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes)

LLVM_ABI SMLoc getLoc() const

bool isNot(TokenKind K) const

StringRef getString() const

Get the string for the current token, this includes all characters (for example, the quotes on string...

StringRef getStringContents() const

Get the contents of a string token (without quotes).

bool is(TokenKind K) const

LLVM_ABI SMLoc getEndLoc() const

StringRef getIdentifier() const

Get the identifier string for the current token, which should be an identifier or a string.

static const char * getRegisterName(MCRegister Reg)

Base class for user error types.

Container class for subtarget features.

constexpr size_t size() const

void printExpr(raw_ostream &, const MCExpr &) const

virtual void Initialize(MCAsmParser &Parser)

Initialize the extension for parsing using the given Parser.

virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0

Parse an arbitrary expression.

const AsmToken & getTok() const

Get the current AsmToken from the stream.

virtual const AsmToken & Lex()=0

Get the next AsmToken in the stream, possibly handling file inclusion first.

static LLVM_ABI const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

unsigned getNumOperands() const

unsigned getOpcode() const

iterator insert(iterator I, const MCOperand &Op)

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

static const MCSpecifierExpr * create(const MCExpr *Expr, Spec S, MCContext &Ctx, SMLoc Loc=SMLoc())

virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)

Emit the given Instruction into the current section.

virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())

Emit a label for Symbol into the current section.

Generic base class for all target subtargets.

const FeatureBitset & getFeatureBits() const

static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())

bool isVariable() const

isVariable - Check if this is a variable symbol.

const MCExpr * getVariableValue() const

Get the expression of the variable symbol.

MCTargetAsmParser - Generic interface to target specific assembly parsers.

Ternary parse status returned by various parse* methods.

static constexpr StatusTy Failure

static constexpr StatusTy Success

static constexpr StatusTy NoMatch

Represents a location in source code.

static SMLoc getFromPointer(const char *Ptr)

constexpr const char * getPointer() const

void push_back(const T &Elt)

StringRef - Represent a constant reference to a string, i.e.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

LLVM_ABI const TagNameMap & getCSKYAttributeTags()

LLVM_ABI ArchKind parseCPUArch(StringRef CPU)

LLVM_ABI ArchKind parseArch(StringRef Arch)

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

LLVM_ABI std::optional< unsigned > attrTypeFromString(StringRef tag, TagNameMap tagNameMap)

Flag

These should be considered private to the implementation of the MCInstrDesc class.

@ CE

Windows NT (Windows on ARM)

initializer< Ty > init(const Ty &Val)

Context & getContext() const

This is an optimization pass for GlobalISel generic memory operations.

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

static bool isMem(const MachineInstr &MI, unsigned Op)

LLVM_ABI std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")

getToken - This function extracts one token from source, ignoring any leading characters that appear ...

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

SmallVectorImpl< std::unique_ptr< MCParsedAsmOperand > > OperandVector

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

Target & getTheCSKYTarget()

DWARFExpression::Operation Op

constexpr bool isShiftedInt(int64_t x)

Checks if a signed integer is an N bit number shifted left by S.

constexpr bool isShiftedUInt(uint64_t x)

Checks if a unsigned integer is an N bit number shifted left by S.

RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...